| /* |
| * Copyright (c) 2017 Linaro Limited |
| * Copyright (c) 2019 Centaur Analytics, Inc |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| #include <dt-bindings/clock/stm32_clock.h> |
| #include <dt-bindings/i2c/i2c.h> |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| chosen { |
| zephyr,flash-controller = &flash; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m3"; |
| reg = <0>; |
| }; |
| }; |
| |
| |
| sram0: memory@20000000 { |
| compatible = "mmio-sram"; |
| }; |
| |
| soc { |
| |
| flash: flash-controller@40022000 { |
| compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller"; |
| label = "FLASH_CTRL"; |
| reg = <0x40022000 0x400>; |
| interrupts = <3 0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "soc-nv-flash"; |
| label = "FLASH_STM32"; |
| |
| write-block-size = <2>; |
| }; |
| }; |
| |
| rcc: rcc@40021000 { |
| compatible = "st,stm32-rcc"; |
| #clock-cells = <2>; |
| reg = <0x40021000 0x400>; |
| label = "STM32_CLK_RCC"; |
| }; |
| |
| pinctrl: pin-controller@40010800 { |
| compatible = "st,stm32-pinmux"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x40010800 0x1C00>; |
| |
| gpioa: gpio@40010800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40010800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000005>; |
| label = "GPIOA"; |
| }; |
| |
| gpiob: gpio@40010c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40010c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000009>; |
| label = "GPIOB"; |
| }; |
| |
| gpioc: gpio@40011000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40011000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000011>; |
| label = "GPIOC"; |
| }; |
| |
| gpiod: gpio@40011400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40011400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000021>; |
| label = "GPIOD"; |
| }; |
| |
| gpioe: gpio@40011800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40011800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000041>; |
| label = "GPIOE"; |
| }; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; |
| interrupts = <37 0>; |
| status = "disabled"; |
| label = "UART_1"; |
| }; |
| |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; |
| interrupts = <38 0>; |
| status = "disabled"; |
| label = "UART_2"; |
| }; |
| |
| usart3: serial@40004800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; |
| interrupts = <39 0>; |
| status = "disabled"; |
| label = "UART_3"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v1"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; |
| interrupts = <31 0>, <32 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| label= "I2C_1"; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v1"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; |
| interrupts = <33 0>, <34 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| label= "I2C_2"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>; |
| interrupts = <35 5>; |
| status = "disabled"; |
| label = "SPI_1"; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| label = "IWDG"; |
| status = "disabled"; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002C00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; |
| label = "WWDG"; |
| interrupts = <0 7>; |
| status = "disabled"; |
| }; |
| |
| timers1: timers@40012c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40012c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>; |
| status = "disabled"; |
| label = "TIMERS_1"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_1"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers2: timers@40000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>; |
| status = "disabled"; |
| label = "TIMERS_2"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <0>; |
| label = "PWM_2"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers3: timers@40000400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; |
| status = "disabled"; |
| label = "TIMERS_3"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_3"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers4: timers@40000800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; |
| status = "disabled"; |
| label = "TIMERS_4"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_4"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| adc1: adc@40012400 { |
| compatible = "st,stm32-adc"; |
| reg = <0x40012400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| label = "ADC_1"; |
| #io-channel-cells = <1>; |
| }; |
| |
| dma1: dma@40020000 { |
| compatible = "st,stm32-dma"; |
| #dma-cells = <4>; |
| reg = <0x40020000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; |
| interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; |
| status = "disabled"; |
| label = "DMA_1"; |
| }; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
