| /* |
| * Copyright (c) 2023 Nuvoton Technology Corporation. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| #include <mem.h> |
| #include <zephyr/dt-bindings/pinctrl/numaker-m46x-pinctrl.h> |
| #include <zephyr/dt-bindings/clock/numaker_m46x_clock.h> |
| #include <zephyr/dt-bindings/reset/numaker_m46x_reset.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| |
| / { |
| chosen { |
| zephyr,flash-controller = &fmc; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m4f"; |
| reg = <0>; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "mmio-sram"; |
| reg = <0x20000000 DT_SIZE_K(512)>; |
| }; |
| |
| sysclk: system-clock { |
| compatible = "fixed-clock"; |
| clock-frequency = <200000000>; |
| #clock-cells = <0>; |
| }; |
| |
| soc { |
| scc: system-clock-controller@40000200 { |
| compatible = "nuvoton,numaker-scc"; |
| reg = <0x40000200 0x100>; |
| #clock-cells = <0>; |
| /* hxt = "enable"; */ |
| /* lxt = "enable"; */ |
| clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 | |
| NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>; |
| core-clock = <200000000>; |
| |
| pcc: peripheral-clock-controller { |
| compatible = "nuvoton,numaker-pcc"; |
| #clock-cells = <3>; |
| }; |
| }; |
| |
| rst: reset-controller@40000000 { |
| compatible = "nuvoton,numaker-rst"; |
| reg = <0x40000000 0x20>; |
| #reset-cells = <1>; |
| status = "okay"; |
| }; |
| |
| fmc: flash-controller@4000c000 { |
| compatible = "nuvoton,numaker-fmc"; |
| reg = <0x4000c000 0x110>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@0 { |
| compatible = "soc-nv-flash"; |
| reg = <0 DT_SIZE_K(1024)>; |
| erase-block-size = <4096>; |
| write-block-size = <4>; |
| }; |
| }; |
| |
| uart0: serial@40070000 { |
| compatible = "nuvoton,numaker-uart"; |
| reg = <0x40070000 0x1000>; |
| interrupts = <36 0>; |
| resets = <&rst NUMAKER_UART0_RST>; |
| clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC |
| NUMAKER_CLK_CLKDIV0_UART0(1)>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@40071000 { |
| compatible = "nuvoton,numaker-uart"; |
| reg = <0x40071000 0x1000>; |
| interrupts = <37 0>; |
| resets = <&rst NUMAKER_UART1_RST>; |
| clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC |
| NUMAKER_CLK_CLKDIV0_UART1(1)>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@40072000 { |
| compatible = "nuvoton,numaker-uart"; |
| reg = <0x40072000 0x1000>; |
| interrupts = <48 0>; |
| resets = <&rst NUMAKER_UART2_RST>; |
| clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC |
| NUMAKER_CLK_CLKDIV4_UART2(1)>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@40073000 { |
| compatible = "nuvoton,numaker-uart"; |
| reg = <0x40073000 0x1000>; |
| interrupts = <49 0>; |
| resets = <&rst NUMAKER_UART3_RST>; |
| clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC |
| NUMAKER_CLK_CLKDIV4_UART3(1)>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@40074000 { |
| compatible = "nuvoton,numaker-uart"; |
| reg = <0x40074000 0x1000>; |
| interrupts = <74 0>; |
| resets = <&rst NUMAKER_UART4_RST>; |
| clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC |
| NUMAKER_CLK_CLKDIV4_UART4(1)>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@40075000 { |
| compatible = "nuvoton,numaker-uart"; |
| reg = <0x40075000 0x1000>; |
| interrupts = <75 0>; |
| resets = <&rst NUMAKER_UART5_RST>; |
| clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC |
| NUMAKER_CLK_CLKDIV4_UART5(1)>; |
| status = "disabled"; |
| }; |
| |
| uart6: serial@40076000 { |
| compatible = "nuvoton,numaker-uart"; |
| reg = <0x40076000 0x1000>; |
| interrupts = <102 0>; |
| resets = <&rst NUMAKER_UART6_RST>; |
| clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC |
| NUMAKER_CLK_CLKDIV4_UART6(1)>; |
| status = "disabled"; |
| }; |
| |
| uart7: serial@40077000 { |
| compatible = "nuvoton,numaker-uart"; |
| reg = <0x40077000 0x1000>; |
| interrupts = <103 0>; |
| resets = <&rst NUMAKER_UART7_RST>; |
| clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC |
| NUMAKER_CLK_CLKDIV4_UART7(1)>; |
| status = "disabled"; |
| }; |
| |
| uart8: serial@40078000 { |
| compatible = "nuvoton,numaker-uart"; |
| reg = <0x40078000 0x1000>; |
| interrupts = <99 0>; |
| resets = <&rst NUMAKER_UART8_RST>; |
| clocks = <&pcc NUMAKER_UART8_MODULE NUMAKER_CLK_CLKSEL2_UART8SEL_HIRC |
| NUMAKER_CLK_CLKDIV5_UART8(1)>; |
| status = "disabled"; |
| }; |
| |
| uart9: serial@40079000 { |
| compatible = "nuvoton,numaker-uart"; |
| reg = <0x40079000 0x1000>; |
| interrupts = <100 0>; |
| resets = <&rst NUMAKER_UART9_RST>; |
| clocks = <&pcc NUMAKER_UART9_MODULE NUMAKER_CLK_CLKSEL2_UART9SEL_HIRC |
| NUMAKER_CLK_CLKDIV5_UART9(1)>; |
| status = "disabled"; |
| }; |
| |
| pinctrl: pin-controller@40000080 { |
| compatible = "nuvoton,numaker-pinctrl"; |
| reg = <0x40000080 0x28 |
| 0x40000500 0xa0>; |
| reg-names = "mfos", "mfp"; |
| status = "okay"; |
| }; |
| |
| gpioa: gpio@40004000 { |
| compatible = "nuvoton,numaker-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40004000 0x40>; |
| clocks = <&pcc NUMAKER_GPA_MODULE 0 0>; |
| status = "disabled"; |
| interrupts = <16 2>; |
| }; |
| |
| gpiob: gpio@40004040 { |
| compatible = "nuvoton,numaker-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40004040 0x40>; |
| clocks = <&pcc NUMAKER_GPB_MODULE 0 0>; |
| status = "disabled"; |
| interrupts = <17 2>; |
| }; |
| |
| gpioc: gpio@40004080 { |
| compatible = "nuvoton,numaker-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40004080 0x40>; |
| clocks = <&pcc NUMAKER_GPC_MODULE 0 0>; |
| status = "disabled"; |
| interrupts = <18 2>; |
| }; |
| |
| gpiod: gpio@400040c0 { |
| compatible = "nuvoton,numaker-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x400040c0 0x40>; |
| clocks = <&pcc NUMAKER_GPD_MODULE 0 0>; |
| status = "disabled"; |
| interrupts = <19 2>; |
| }; |
| |
| gpioe: gpio@40004100 { |
| compatible = "nuvoton,numaker-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40004100 0x40>; |
| clocks = <&pcc NUMAKER_GPE_MODULE 0 0>; |
| status = "disabled"; |
| interrupts = <20 2>; |
| }; |
| |
| gpiof: gpio@40004140 { |
| compatible = "nuvoton,numaker-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40004140 0x40>; |
| clocks = <&pcc NUMAKER_GPF_MODULE 0 0>; |
| status = "disabled"; |
| interrupts = <21 2>; |
| }; |
| |
| gpiog: gpio@40004180 { |
| compatible = "nuvoton,numaker-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40004180 0x40>; |
| clocks = <&pcc NUMAKER_GPG_MODULE 0 0>; |
| status = "disabled"; |
| interrupts = <72 2>; |
| }; |
| |
| gpioh: gpio@400041c0 { |
| compatible = "nuvoton,numaker-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x400041c0 0x40>; |
| clocks = <&pcc NUMAKER_GPH_MODULE 0 0>; |
| status = "disabled"; |
| interrupts = <88 2>; |
| }; |
| |
| gpioi: gpio@40004200 { |
| compatible = "nuvoton,numaker-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40004200 0x40>; |
| clocks = <&pcc NUMAKER_GPI_MODULE 0 0>; |
| status = "disabled"; |
| interrupts = <110 2>; |
| }; |
| |
| gpioj: gpio@40004240 { |
| compatible = "nuvoton,numaker-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40004240 0x40>; |
| clocks = <&pcc NUMAKER_GPJ_MODULE 0 0>; |
| status = "disabled"; |
| interrupts = <61 2>; |
| }; |
| |
| spi0: spi@40061000 { |
| compatible = "nuvoton,numaker-spi"; |
| reg = <0x40061000 0x6c>; |
| interrupts = <23 0>; |
| resets = <&rst NUMAKER_SPI0_RST>; |
| clocks = <&pcc NUMAKER_SPI0_MODULE NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@40062000 { |
| compatible = "nuvoton,numaker-spi"; |
| reg = <0x40062000 0x6c>; |
| interrupts = <51 0>; |
| resets = <&rst NUMAKER_SPI1_RST>; |
| clocks = <&pcc NUMAKER_SPI1_MODULE NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@40063000 { |
| compatible = "nuvoton,numaker-spi"; |
| reg = <0x40063000 0x6c>; |
| interrupts = <52 0>; |
| resets = <&rst NUMAKER_SPI2_RST>; |
| clocks = <&pcc NUMAKER_SPI2_MODULE NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@40064000 { |
| compatible = "nuvoton,numaker-spi"; |
| reg = <0x40064000 0x6c>; |
| interrupts = <62 0>; |
| resets = <&rst NUMAKER_SPI3_RST>; |
| clocks = <&pcc NUMAKER_SPI3_MODULE NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@40065000 { |
| compatible = "nuvoton,numaker-spi"; |
| reg = <0x40065000 0x6c>; |
| interrupts = <63 0>; |
| resets = <&rst NUMAKER_SPI4_RST>; |
| clocks = <&pcc NUMAKER_SPI4_MODULE NUMAKER_CLK_CLKSEL4_SPI4SEL_HIRC 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@40066000 { |
| compatible = "nuvoton,numaker-spi"; |
| reg = <0x40066000 0x6c>; |
| interrupts = <57 0>; |
| resets = <&rst NUMAKER_SPI5_RST>; |
| clocks = <&pcc NUMAKER_SPI5_MODULE NUMAKER_CLK_CLKSEL4_SPI5SEL_HIRC 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi6: spi@40067000 { |
| compatible = "nuvoton,numaker-spi"; |
| reg = <0x40067000 0x6c>; |
| interrupts = <70 0>; |
| resets = <&rst NUMAKER_SPI6_RST>; |
| clocks = <&pcc NUMAKER_SPI6_MODULE NUMAKER_CLK_CLKSEL4_SPI6SEL_HIRC 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi7: spi@40068000 { |
| compatible = "nuvoton,numaker-spi"; |
| reg = <0x40068000 0x6c>; |
| interrupts = <77 0>; |
| resets = <&rst NUMAKER_SPI7_RST>; |
| clocks = <&pcc NUMAKER_SPI7_MODULE NUMAKER_CLK_CLKSEL4_SPI7SEL_HIRC 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi8: spi@4006b000 { |
| compatible = "nuvoton,numaker-spi"; |
| reg = <0x4006b000 0x6c>; |
| interrupts = <108 0>; |
| resets = <&rst NUMAKER_SPI8_RST>; |
| clocks = <&pcc NUMAKER_SPI8_MODULE NUMAKER_CLK_CLKSEL4_SPI8SEL_HIRC 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi9: spi@4006c000 { |
| compatible = "nuvoton,numaker-spi"; |
| reg = <0x4006c000 0x6c>; |
| interrupts = <111 0>; |
| resets = <&rst NUMAKER_SPI9_RST>; |
| clocks = <&pcc NUMAKER_SPI9_MODULE NUMAKER_CLK_CLKSEL4_SPI9SEL_HIRC 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi10: spi@4006d000 { |
| compatible = "nuvoton,numaker-spi"; |
| reg = <0x4006d000 0x6c>; |
| interrupts = <119 0>; |
| resets = <&rst NUMAKER_SPI10_RST>; |
| clocks = <&pcc NUMAKER_SPI10_MODULE NUMAKER_CLK_CLKSEL4_SPI10SEL_HIRC 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| epwm0: epwm@40058000 { |
| compatible = "nuvoton,numaker-pwm"; |
| reg = <0x40058000 0x37c>; |
| interrupts = <25 0>, <26 0>, <27 0>; |
| interrupt-names = "pair0", "pair1", "pair2"; |
| resets = <&rst NUMAKER_EPWM0_RST>; |
| prescaler = <19>; |
| clocks = <&pcc NUMAKER_EPWM0_MODULE NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0 0>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| epwm1: epwm@40059000 { |
| compatible = "nuvoton,numaker-pwm"; |
| reg = <0x40059000 0x37c>; |
| interrupts = <29 0>, <30 0>, <31 0>; |
| interrupt-names = "pair0", "pair1", "pair2"; |
| resets = <&rst NUMAKER_EPWM1_RST>; |
| prescaler = <19>; |
| clocks = <&pcc NUMAKER_EPWM1_MODULE NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1 0>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
