| /* |
| * Copyright (c) 2022 Linaro Limited |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| /* Clocks clean up config |
| * Aim is to avoid conflict with specific default board configuration |
| */ |
| |
| &clk_hse { |
| status = "disabled"; |
| /delete-property/ hse-bypass; |
| /delete-property/ clock-frequency; |
| }; |
| |
| &clk_hsi { |
| status = "disabled"; |
| }; |
| |
| &clk_msi { |
| status = "disabled"; |
| /delete-property/ msi-range; |
| }; |
| |
| &pll { |
| /delete-property/ div-m; |
| /delete-property/ mul-n; |
| /delete-property/ div-p; |
| /delete-property/ div-q; |
| /delete-property/ div-r; |
| /delete-property/ clocks; |
| status = "disabled"; |
| }; |
| |
| &rcc { |
| /delete-property/ clocks; |
| /delete-property/ clock-frequency; |
| }; |
| |
| |
| /* Core set up |
| * Aim of this part is to provide a base working clock config |
| */ |
| |
| &clk_hsi { |
| status = "okay"; |
| }; |
| |
| &clk_lse { |
| status = "okay"; |
| }; |
| |
| &pll { |
| div-m = <1>; |
| mul-n = <20>; |
| div-p = <7>; |
| div-q = <2>; |
| div-r = <4>; |
| clocks = <&clk_hsi>; |
| status = "okay"; |
| }; |
| |
| &rcc { |
| clocks = <&pll>; |
| clock-frequency = <DT_FREQ_M(80)>; |
| ahb-prescaler = <1>; |
| apb1-prescaler = <1>; |
| apb2-prescaler = <1>; |
| }; |
| |
| &i2c1 { |
| /delete-property/ clocks; |
| /* an extra clock at index 2 to check if switching clocks works */ |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, |
| <&rcc STM32_SRC_HSI I2C1_SEL(2)>, |
| <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; |
| status = "okay"; |
| }; |
| |
| &lptim1 { |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, |
| <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; |
| status = "okay"; |
| }; |
| |
| &adc1 { |
| /* Basic test only. Don't configure domain clock. */ |
| status = "okay"; |
| }; |