blob: a462d48a266c8e2b73604013e0892abce580711c [file] [log] [blame]
/*
* Copyright (c) 2017 Linaro Limited
* Copyright (c) 2021 Marius Scholtz, RIC Electronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f401.dtsi>
/ {
chosen {
zephyr,entropy = &rng;
};
soc {
compatible = "st,stm32f405", "st,stm32f4", "simple-bus";
pinctrl: pin-controller@40020000 {
reg = <0x40020000 0x2400>;
gpiof: gpio@40021400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
};
gpiog: gpio@40021800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
};
gpioi: gpio@40022000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
};
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
uart4: serial@40004c00 {
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <53 0>;
status = "disabled";
};
timers6: timers@40001000 {
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
resets = <&rctl STM32_RESET(APB1, 4U)>;
interrupts = <54 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
counter {
compatible = "st,stm32-counter";
status = "disabled";
};
};
timers7: timers@40001400 {
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
resets = <&rctl STM32_RESET(APB1, 5U)>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
counter {
compatible = "st,stm32-counter";
status = "disabled";
};
};
timers8: timers@40010400 {
compatible = "st,stm32-timers";
reg = <0x40010400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
resets = <&rctl STM32_RESET(APB2, 1U)>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
qdec {
compatible = "st,stm32-qdec";
status = "disabled";
st,input-filter-level = <NO_FILTER>;
};
};
timers12: timers@40001800 {
compatible = "st,stm32-timers";
reg = <0x40001800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
resets = <&rctl STM32_RESET(APB1, 6U)>;
interrupts = <43 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
};
};
timers13: timers@40001c00 {
compatible = "st,stm32-timers";
reg = <0x40001c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
resets = <&rctl STM32_RESET(APB1, 7U)>;
interrupts = <44 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
};
};
timers14: timers@40002000 {
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
resets = <&rctl STM32_RESET(APB1, 8U)>;
interrupts = <45 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
};
};
usbotg_hs: usb@40040000 {
compatible = "st,stm32-otghs";
reg = <0x40040000 0x40000>;
interrupts = <77 0>, <74 0>, <75 0>;
interrupt-names = "otghs", "ep1_out", "ep1_in";
num-bidir-endpoints = <6>;
ram-size = <4096>;
maximum-speed = "full-speed";
phys = <&otghs_fs_phy>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>,
<&rcc STM32_SRC_PLL_Q NO_SEL>;
status = "disabled";
};
can1: can@40006400 {
compatible = "st,stm32-bxcan";
reg = <0x40006400 0x400>;
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
sample-point = <875>;
};
can2: can@40006800 {
compatible = "st,stm32-bxcan";
reg = <0x40006800 0x400>;
interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
/* also enabling clock for can1 (master instance) */
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
master-can-reg = <0x40006400>;
status = "disabled";
sample-point = <875>;
};
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
interrupts = <80 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
status = "disabled";
};
backup_sram: memory@40024000 {
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
reg = <0x40024000 DT_SIZE_K(4)>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
zephyr,memory-region = "BACKUP_SRAM";
status = "disabled";
};
adc2: adc@40012100 {
compatible = "st,stm32-adc";
reg = <0x40012100 0x050>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
STM32_ADC_RES(8, 0x02)
STM32_ADC_RES(6, 0x03)>;
sampling-times = <3 15 28 56 84 112 144 480>;
st,adc-clock-source = <SYNC>;
st,adc-sequencer = <FULLY_CONFIGURABLE>;
};
adc3: adc@40012200 {
compatible = "st,stm32-adc";
reg = <0x40012200 0x050>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
STM32_ADC_RES(8, 0x02)
STM32_ADC_RES(6, 0x03)>;
sampling-times = <3 15 28 56 84 112 144 480>;
st,adc-clock-source = <SYNC>;
st,adc-sequencer = <FULLY_CONFIGURABLE>;
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
#io-channel-cells = <1>;
};
};
otghs_fs_phy: otghs_fs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};