dts/arc/emsk.dtsi

/*
 * Copyright (c) 2018, Synopsys, Inc. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include "skeleton.dtsi"
#include <arc/emsk_dt.h>
#include <dt-bindings/i2c/i2c.h>


/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "snps,arcem";
			reg = <1>;
		};

		intc: arcv2-intc@0 {
			compatible = "snps,arcv2-intc";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	iccm0: iccm@0 {
		device_type = "memory";
		compatible = "arc,iccm";
		reg = <0x0 DT_ICCM_SIZE>;
	};

	dccm0: dccm@80000000 {
		device_type = "memory";
		compatible = "arc,dccm";
		reg = <0x80000000 DT_DCCM_SIZE>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		ddr0: memory@10000000 {
			device_type = "memory";
			compatible = "mmio-sram";
			reg = <0x10000000 0x8000000>;
		};


		i2c0: i2c@f0004000 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xf0004000 0x1000>;
			label = "I2C_0";
			interrupts = <DT_I2C0_INTNO 1>;
			interrupt-parent = <&intc>;
		};

		i2c1: i2c@f0005000 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xf0005000 0x1000>;
			label = "I2C_1";
			interrupts = <DT_I2C1_INTNO 1>;
			interrupt-parent = <&intc>;
		};

		uart0: uart@f0008000 {
			compatible = "ns16550";
			clock-frequency = <DT_APB_CLK_HZ>;
			reg = <0xf0008000 0x1000>;
			label = "UART_0";
			interrupts = <DT_UART0_INTNO 1>;
			interrupt-parent = <&intc>;
		};

		uart1: uart@f0009000 {
			compatible = "ns16550";
			clock-frequency = <DT_APB_CLK_HZ>;
			reg = <0xf0009000 0x1000>;
			label = "UART_1";
			interrupts = <DT_UART1_INTNO 1>;
			interrupt-parent = <&intc>;

		};

		uart2: uart@f000a000 {
			compatible = "ns16550";
			clock-frequency = <DT_APB_CLK_HZ>;
			reg = <0xf000a000 0x1000>;
			label = "UART_2";
			interrupts = <DT_UART2_INTNO 1>;
			interrupt-parent = <&intc>;

		};

		gpio0: gpio@f0002000 {
			compatible = "snps,designware-gpio";
			reg = <0xF0002000 0xc>;
			bits = <32>;
			label = "GPIO_0";
			interrupts = <DT_GPIO0_INTNO 1>;
			interrupt-parent = <&intc>;

		};

		gpio1: gpio@f000200C {
			compatible = "snps,designware-gpio";
			reg = <0xF000200C 0xc>;
			bits = <9>;
			label = "GPIO_1";
			interrupts = <DT_GPIO1_INTNO 1>;
			interrupt-parent = <&intc>;

		};

		gpio2: gpio@f0002018 {
			compatible = "snps,designware-gpio";
			reg = <0xF0002018 0xc>;
			bits = <32>;
			label = "GPIO_2";

			interrupts = <DT_GPIO2_INTNO 1>;
			interrupt-parent = <&intc>;

		};

		gpio3: gpio@f0002024 {
			compatible = "snps,designware-gpio";
			reg = <0xF0002024 0xc>;
			bits = <12>;
			label = "GPIO_3";

			interrupts = <DT_GPIO3_INTNO 1>;
			interrupt-parent = <&intc>;

		};

		spi0: spi@f0006000 {
			compatible = "snps,designware-spi";
			reg = <0xf0006000 0x1000>;
			label = "SPI_0";
			interrupts = <DT_SPI0_INTNO 1>;
			interrupt-parent = <&intc>;

			#address-cells = <1>;
			#size-cells = <0>;

		};

		spi1: spi@f0007000 {
			compatible = "snps,designware-spi";
			reg = <0xf0007000 0x1000>;
			label = "SPI_1";
			interrupts = <DT_SPI1_INTNO 1>;
			interrupt-parent = <&intc>;

			#address-cells = <1>;
			#size-cells = <0>;

		};

	};
};