| # XTENSA board configuration |
| |
| # Copyright (c) 2017 Intel Corporation |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| if SOC_INTEL_S1000 |
| |
| config SOC |
| default "intel_s1000" |
| |
| config IRQ_OFFLOAD_INTNUM |
| default 0 |
| |
| # S1000 does not have MISC0. |
| # Since EXCSAVE7 is unused by Zephyr, use it instead. |
| config XTENSA_KERNEL_CPU_PTR_SR |
| default "EXCSAVE7" |
| |
| config SPI_DW_FIFO_DEPTH |
| default 32 |
| |
| config SYS_CLOCK_HW_CYCLES_PER_SEC |
| default 400000000 if XTENSA_TIMER |
| default 38400000 if CAVS_TIMER |
| |
| if SMP |
| |
| config MP_NUM_CPUS |
| default 2 |
| |
| config XTENSA_TIMER |
| default n |
| |
| config CAVS_TIMER |
| default y |
| |
| config IPM |
| default y |
| |
| config IPM_CAVS_IDC |
| default y if IPM |
| |
| config SCHED_IPI_SUPPORTED |
| default y if IPM_CAVS_IDC |
| |
| endif |
| |
| endif |
