soc/riscv32/openisa_rv32m1/Kconfig.defconfig

# Kconfig.defconfig: RV32M1 SoC RISC-V core default configuration values
#
# Copyright (c) 2018 Foundries.io Ltd
#
# SPDX-License-Identifier: Apache-2.0

if SOC_OPENISA_RV32M1_RISCV32

config SOC
	string
	default "openisa_rv32m1"

# 32 from event unit + 32 * (1 + max enabled INTMUX channel)
config NUM_IRQS
	int
	default 288 if RV32M1_INTMUX_CHANNEL_7
	default 256 if RV32M1_INTMUX_CHANNEL_6
	default 224 if RV32M1_INTMUX_CHANNEL_5
	default 192 if RV32M1_INTMUX_CHANNEL_4
	default 160 if RV32M1_INTMUX_CHANNEL_3
	default 128 if RV32M1_INTMUX_CHANNEL_2
	default 96 if RV32M1_INTMUX_CHANNEL_1
	default 64 if RV32M1_INTMUX_CHANNEL_0
	default 32

config XIP
	bool
	default y

config RISCV_GENERIC_TOOLCHAIN
	bool
	default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr"
	default n

config RISCV_SOC_CONTEXT_SAVE
	bool
	default y if SOC_OPENISA_RV32M1_RI5CY

config RISCV_SOC_INTERRUPT_INIT
	bool
	default y

# We need to disable the watchdog out of reset, as it's enabled by
# default. Use the WDOG_INIT hook for doing that.
config WDOG_INIT
	def_bool y

# Built-in flash allocated to each chip. This configuration
# assumes the Arm cores are disabled, as these base addresses
# contain the Arm core vector tables if they are used.
config RISCV32_RV32M1_ROM_BASE_ADDR
	hex
	default 0x00000000 if SOC_OPENISA_RV32M1_RI5CY
	default 0x01000000 if SOC_OPENISA_RV32M1_ZERO_RISCY

config RISCV32_RV32M1_ROM_SIZE
	hex
	default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY
	default 0x0003FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY

config RISCV32_RV32M1_RAM_BASE_ADDR
	hex
	default 0x20000000 if SOC_OPENISA_RV32M1_RI5CY
	default 0x09000000 if SOC_OPENISA_RV32M1_ZERO_RISCY

config RISCV32_RV32M1_RAM_SIZE
	hex
	default 0x00030000 if SOC_OPENISA_RV32M1_RI5CY
	default 0x00020000 if SOC_OPENISA_RV32M1_ZERO_RISCY

# The event unit looks for vector tables at the end of each core's
# flash space. These vector tables are not relocatable.
config RISCV32_RV32M1_VECTOR_BASE_ADDR
	hex
	default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY
	default 0x0103FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY

config RISCV32_RV32M1_VECTOR_SIZE
	hex
	default 0x100

config SYS_CLOCK_HW_CYCLES_PER_SEC
	int
	default 8000000 if SOC_OPENISA_RV32M1_RI5CY # SIRC at 8MHz

if MULTI_LEVEL_INTERRUPTS

config MAX_IRQ_PER_AGGREGATOR
	int
	default 32

config 2ND_LEVEL_INTERRUPTS
	def_bool y

config 2ND_LVL_ISR_TBL_OFFSET
	int
	default 32

config NUM_2ND_LEVEL_AGGREGATORS
	int
	default 8 if RV32M1_INTMUX_CHANNEL_7
	default 7 if RV32M1_INTMUX_CHANNEL_6
	default 6 if RV32M1_INTMUX_CHANNEL_5
	default 5 if RV32M1_INTMUX_CHANNEL_4
	default 4 if RV32M1_INTMUX_CHANNEL_3
	default 3 if RV32M1_INTMUX_CHANNEL_2
	default 2 if RV32M1_INTMUX_CHANNEL_1
	default 1		# just channel 0

config 2ND_LVL_INTR_00_OFFSET
	int
	default 24

config 2ND_LVL_INTR_01_OFFSET
	int
	default 25

config 2ND_LVL_INTR_02_OFFSET
	int
	default 26

config 2ND_LVL_INTR_03_OFFSET
	int
	default 27

config 2ND_LVL_INTR_04_OFFSET
	int
	default 28

config 2ND_LVL_INTR_05_OFFSET
	int
	default 29

config 2ND_LVL_INTR_06_OFFSET
	int
	default 30

config 2ND_LVL_INTR_07_OFFSET
	int
	default 31

config RV32M1_INTMUX
	def_bool y

config RV32M1_INTMUX_CHANNEL_0
	def_bool y

config RV32M1_INTMUX_CHANNEL_1
	def_bool y

config RV32M1_INTMUX_CHANNEL_2
	def_bool y

config RV32M1_INTMUX_CHANNEL_3
	def_bool y

config RV32M1_INTMUX_CHANNEL_4
	def_bool y

config RV32M1_INTMUX_CHANNEL_5
	def_bool y

config RV32M1_INTMUX_CHANNEL_6
	def_bool y

config RV32M1_INTMUX_CHANNEL_7
	def_bool y

endif # MULTI_LEVEL_INTERRUPTS

config PINMUX_RV32M1
	def_bool y

if GPIO

config GPIO_RV32M1
	def_bool y

endif # GPIO

if SERIAL

config UART_RV32M1_LPUART
	def_bool y

endif # SERIAL

endif # SOC_OPENISA_RV32M1_RISCV32