| /* |
| * Copyright (c) 2016 Open-RnD Sp. z o.o. |
| * |
| * Licensed under the Apache License, Version 2.0 (the "License"); |
| * you may not use this file except in compliance with the License. |
| * You may obtain a copy of the License at |
| * |
| * http://www.apache.org/licenses/LICENSE-2.0 |
| * |
| * Unless required by applicable law or agreed to in writing, software |
| * distributed under the License is distributed on an "AS IS" BASIS, |
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| * See the License for the specific language governing permissions and |
| * limitations under the License. |
| */ |
| |
| /** |
| * @file |
| * @brief System/hardware module for STM32F1 processor |
| */ |
| |
| #include <nanokernel.h> |
| #include <device.h> |
| #include <init.h> |
| #include <soc.h> |
| #include <arch/cpu.h> |
| |
| /** |
| * @brief Perform basic hardware initialization at boot. |
| * |
| * This needs to be run from the very beginning. |
| * So the init priority has to be 0 (zero). |
| * |
| * @return 0 |
| */ |
| static int stm32f1_init(struct device *arg) |
| { |
| uint32_t key; |
| |
| ARG_UNUSED(arg); |
| |
| key = irq_lock(); |
| |
| /* Setup the vector table offset register (VTOR), |
| * which is located at the beginning of flash area. |
| */ |
| _scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS); |
| |
| /* Clear all faults */ |
| _ScbMemFaultAllFaultsReset(); |
| _ScbBusFaultAllFaultsReset(); |
| _ScbUsageFaultAllFaultsReset(); |
| |
| _ScbHardFaultAllFaultsReset(); |
| |
| /* Install default handler that simply resets the CPU |
| * if configured in the kernel, NOP otherwise |
| */ |
| NMI_INIT(); |
| |
| irq_unlock(key); |
| |
| return 0; |
| } |
| |
| SYS_INIT(stm32f1_init, PRIMARY, 0); |