| /* |
| * Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com> |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <st/l0/stm32l0-pinctrl.dtsi> |
| #include <arm/armv6-m.dtsi> |
| #include <dt-bindings/clock/stm32_clock.h> |
| #include <dt-bindings/i2c/i2c.h> |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m0+"; |
| reg = <0>; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "mmio-sram"; |
| }; |
| |
| soc { |
| flash-controller@40022000 { |
| compatible = "st,stm32l0-flash-controller"; |
| label = "FLASH_CTRL"; |
| reg = <0x40022000 0x400>; |
| interrupts = <3 0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "soc-nv-flash"; |
| label = "FLASH_STM32"; |
| |
| write-block-size = <4>; |
| }; |
| }; |
| |
| rcc: rcc@40021000 { |
| compatible = "st,stm32-rcc"; |
| #clock-cells = <2>; |
| reg = <0x40021000 0x400>; |
| label = "STM32_CLK_RCC"; |
| }; |
| |
| pinctrl: pin-controller@50000000 { |
| compatible = "st,stm32-pinmux"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x50000000 0x2000>; |
| |
| gpioa: gpio@50000000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x50000000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>; |
| label = "GPIOA"; |
| }; |
| |
| gpiob: gpio@50000400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x50000400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>; |
| label = "GPIOB"; |
| }; |
| |
| gpioc: gpio@50000800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x50000800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>; |
| label = "GPIOC"; |
| }; |
| |
| gpiod: gpio@50000c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x50000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>; |
| label = "GPIOD"; |
| }; |
| |
| gpioh: gpio@50001c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x50001c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000080>; |
| label = "GPIOH"; |
| }; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| label = "IWDG"; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; |
| interrupts = <27 0>; |
| status = "disabled"; |
| label = "UART_1"; |
| }; |
| |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; |
| interrupts = <28 0>; |
| status = "disabled"; |
| label = "UART_2"; |
| }; |
| |
| lpuart1: serial@40004800 { |
| compatible = "st,stm32-lpuart", "st,stm32-uart"; |
| reg = <0x40004800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; |
| interrupts = <29 0>; |
| status = "disabled"; |
| label = "LPUART_1"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; |
| interrupts = <23 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| label= "I2C_1"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>; |
| interrupts = <25 3>; |
| status = "disabled"; |
| label = "SPI_1"; |
| }; |
| |
| adc1: adc@40012400 { |
| compatible = "st,stm32-adc"; |
| reg = <0x40012400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>; |
| interrupts = <12 0>; |
| status = "disabled"; |
| label = "ADC_1"; |
| }; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <2>; |
| }; |