boards/arc/nsim/nsim.dtsi

/*
 * Copyright (c) 2018, 2019, Synopsys, Inc. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;

#include "skeleton.dtsi"
#include <mem.h>

#ifndef ICCM_ADDR
#define ICCM_ADDR 0
#endif

#ifndef ICCM_SIZE
#define ICCM_SIZE DT_SIZE_K(512)
#endif

#ifndef DCCM_ADDR
#define DCCM_ADDR 80000000
#endif

#ifndef DCCM_SIZE
#define DCCM_SIZE DT_SIZE_K(512)
#endif

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		intc: arcv2-intc {
			compatible = "snps,arcv2-intc";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	iccm0: iccm@ICCM_ADDR {
		device_type = "memory";
		compatible = "arc,iccm";
		reg = <DT_ADDR(ICCM_ADDR) ICCM_SIZE>;
	};

	dccm0: dccm@DCCM_ADDR {
		compatible = "arc,dccm";
		device_type = "memory";
		reg = <DT_ADDR(DCCM_ADDR) DCCM_SIZE>;
	};

	uart0: uart@f0000000 {
		compatible = "snps,nsim-uart";
		reg = <0xf0000000 0x100>;
		label = "UART_0";
	};

	chosen {
		zephyr,sram = &dccm0;
		zephyr,console = &uart0;
		zephyr,shell-uart = &uart0;
	};
};