blob: 83c2dd94a76eeb497db9d4df15fa33895bd21b8b [file] [log] [blame]
/*
* Copyright (c) 2019 STMicroelectronics.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/g4/stm32g4.dtsi>
/ {
soc {
can {
can2: can@40006800 {
compatible = "st,stm32-fdcan";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40006800 0x400>, <0x4000A800 0x350>;
reg-names = "m_can", "message_ram";
interrupts = <86 0>, <87 0>;
interrupt-names = "LINE_0", "LINE_1";
status = "disabled";
label = "CAN_2";
};
can3: can@40006C00 {
compatible = "st,stm32-fdcan";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40006C00 0x400>, <0x4000AC00 0x350>;
reg-names = "m_can", "message_ram";
interrupts = <88 0>, <89 0>;
interrupt-names = "LINE_0", "LINE_1";
status = "disabled";
label = "CAN_3";
};
};
dac2: dac@50000c00 {
compatible = "st,stm32-dac";
reg = <0x50000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00020000>;
status = "disabled";
label = "DAC_2";
#io-channel-cells = <1>;
};
dac4: dac@50001400 {
compatible = "st,stm32-dac";
reg = <0x50001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00080000>;
status = "disabled";
label = "DAC_4";
#io-channel-cells = <1>;
};
dma1: dma@40020000 {
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 96 0>;
dma-requests = <8>;
};
dma2: dma@40020400 {
interrupts = <56 0 57 0 58 0 59 0 60 0 97 0 98 0 99 0>;
dma-requests = <8>;
dma-offset = <8>;
};
dmamux1: dmamux@40020800 {
dma-channels = <16>;
};
i2c4: i2c@40008400 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40008400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
interrupts = <82 0>, <83 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_4";
};
spi4: spi@40013c00 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
interrupts = <84 5>;
status = "disabled";
label = "SPI_4";
};
};
};