blob: c3071cd1abab54fd8d4d15afbefb4f1482b505b1 [file] [log] [blame]
/*
* Copyright (c) 2018-2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/armv8.1-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include <mem.h>
/ {
compatible = "arm,mps3-an547";
#address-cells = <1>;
#size-cells = <1>;
aliases {
led0 = &led_0;
led1 = &led_1;
sw0 = &user_button_0;
sw1 = &user_button_1;
};
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &dtcm;
zephyr,flash = &itcm;
};
leds {
compatible = "gpio-leds";
led_0: led_0 {
gpios = <&gpio_led0 0>;
label = "USERLED0";
};
led_1: led_1 {
gpios = <&gpio_led0 1>;
label = "USERLED1";
};
led_2: led_2 {
gpios = <&gpio_led0 2>;
label = "USERLED2";
};
led_3: led_3 {
gpios = <&gpio_led0 3>;
label = "USERLED3";
};
led_4: led_4 {
gpios = <&gpio_led0 4>;
label = "USERLED4";
};
led_5: led_5 {
gpios = <&gpio_led0 5>;
label = "USERLED5";
};
led_6: led_6 {
gpios = <&gpio_led0 6>;
label = "USERLED6";
};
led_7: led_7 {
gpios = <&gpio_led0 7>;
label = "USERLED7";
};
led_8: led_8 {
gpios = <&gpio_led0 8>;
label = "PB1LED";
};
led_9: led_9 {
gpios = <&gpio_led0 9>;
label = "PB2LED";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_0: button_0 {
label = "USERPB0";
gpios = <&gpio_button 0>;
};
user_button_1: button_1 {
label = "USERPB1";
gpios = <&gpio_button 1>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m55";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8.1m-mpu";
reg = <0xe000ed90 0x40>;
arm,num-mpu-regions = <16>;
};
};
};
/* We utilize the secure addresses, if you subtract 0x10000000
* you'll get the non-secure alias
*/
itcm: itcm@10000000 { /* alias @ 0x0 */
reg = <0x10000000 DT_SIZE_K(512)>;
};
sram: sram@11000000 { /* alias @ 0x01000000 */
compatible = "mmio-sram";
reg = <0x11000000 DT_SIZE_M(2)>;
};
dtcm: dtcm@30000000 { /* alias @ 0x20000000 */
reg = <0x30000000 DT_SIZE_K(512)>;
};
isram: sram@31000000 {/* alias @ 0x21000000 */
compatible = "mmio-sram";
reg = <0x31000000 DT_SIZE_M(4)>;
};
/* DDR4 - 2G, alternates non-secure/secure every 256M */
ddr4: memory@60000000 {
device_type = "memory";
reg = <0x60000000 DT_SIZE_M(256)
0x70000000 DT_SIZE_M(256)
0x80000000 DT_SIZE_M(256)
0x90000000 DT_SIZE_M(256)
0xa0000000 DT_SIZE_M(256)
0xb0000000 DT_SIZE_M(256)
0xc0000000 DT_SIZE_M(256)
0xd0000000 DT_SIZE_M(256)>;
};
soc {
peripheral@50000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x50000000 0x10000000>;
#include "mps3_an547-common.dtsi"
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};