| /* |
| * Copyright (c) 2018-2019 Linaro Limited |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| /dts-v1/; |
| |
| #include <mem.h> |
| #include <arm/armv8-m.dtsi> |
| #include <dt-bindings/i2c/i2c.h> |
| |
| / { |
| compatible = "arm,mps2"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| aliases { |
| led0 = &led_0; |
| led1 = &led_1; |
| sw0 = &user_button_0; |
| sw1 = &user_button_1; |
| watchdog0 = &wdog0; |
| }; |
| |
| chosen { |
| zephyr,console = &uart0; |
| zephyr,shell-uart = &uart0; |
| zephyr,sram = &ram; |
| zephyr,flash = &code; |
| }; |
| |
| leds { |
| compatible = "gpio-leds"; |
| led_0: led_0 { |
| gpios = <&gpio_led0 0>; |
| label = "USERLED0"; |
| }; |
| led_1: led_1 { |
| gpios = <&gpio_led0 1>; |
| label = "USERLED1"; |
| }; |
| }; |
| |
| gpio_keys { |
| compatible = "gpio-keys"; |
| user_button_0: button_0 { |
| label = "USERPB0"; |
| gpios = <&gpio_button 0>; |
| }; |
| user_button_1: button_1 { |
| label = "USERPB1"; |
| gpios = <&gpio_button 1>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m33"; |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mpu: mpu@e000ed90 { |
| compatible = "arm,armv8m-mpu"; |
| reg = <0xe000ed90 0x40>; |
| arm,num-mpu-regions = <16>; |
| }; |
| }; |
| }; |
| |
| /* |
| * The memory regions defined below are according to AN521: |
| * https://documentation-service.arm.com/static/5fa12fe9b1a7c5445f29017f |
| * Please see tables from 3-1 to 3-4. |
| */ |
| |
| sram1: memory@0 { |
| compatible = "mmio-sram"; |
| reg = <0x0 DT_SIZE_M(4)>; |
| }; |
| |
| sram2_3: memory@28000000 { |
| compatible = "mmio-sram"; |
| reg = <0x28000000 DT_SIZE_M(4)>; |
| }; |
| |
| psram: memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 DT_SIZE_M(16)>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| code: memory@100000 { |
| reg = <0x00100000 DT_SIZE_K(512)>; |
| }; |
| |
| ram: memory@28100000 { |
| reg = <0x28100000 DT_SIZE_M(1)>; |
| }; |
| }; |
| |
| soc { |
| peripheral@40000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x40000000 0x10000000>; |
| |
| #include "mps2_an521-common.dtsi" |
| }; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <3>; |
| }; |