| # Nordic Semiconductor nRF53 MCU line |
| |
| # Copyright (c) 2019 Nordic Semiconductor ASA |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| config SOC_NRF5340_CPUAPP |
| depends on SOC_SERIES_NRF53X |
| bool |
| select CPU_HAS_NRF_IDAU |
| select CPU_HAS_FPU |
| select ARMV8_M_DSP |
| select HAS_HW_NRF_CC312 |
| select HAS_HW_NRF_COMP |
| select HAS_HW_NRF_CLOCK |
| select HAS_HW_NRF_DPPIC |
| select HAS_HW_NRF_EGU0 |
| select HAS_HW_NRF_EGU1 |
| select HAS_HW_NRF_EGU2 |
| select HAS_HW_NRF_EGU3 |
| select HAS_HW_NRF_EGU4 |
| select HAS_HW_NRF_EGU5 |
| select HAS_HW_NRF_GPIO0 |
| select HAS_HW_NRF_GPIO1 |
| select HAS_HW_NRF_GPIOTE |
| select HAS_HW_NRF_I2S |
| select HAS_HW_NRF_IPC |
| select HAS_HW_NRF_KMU |
| select HAS_HW_NRF_LPCOMP |
| select HAS_HW_NRF_NFCT |
| select HAS_HW_NRF_NVMC_PE |
| select HAS_HW_NRF_PDM |
| select HAS_HW_NRF_POWER |
| select HAS_HW_NRF_PWM0 |
| select HAS_HW_NRF_PWM1 |
| select HAS_HW_NRF_PWM2 |
| select HAS_HW_NRF_PWM3 |
| select HAS_HW_NRF_QDEC0 |
| select HAS_HW_NRF_QDEC1 |
| select HAS_HW_NRF_QSPI |
| select HAS_HW_NRF_RTC0 |
| select HAS_HW_NRF_RTC1 |
| select HAS_HW_NRF_SAADC |
| select HAS_HW_NRF_SPIM0 |
| select HAS_HW_NRF_SPIM1 |
| select HAS_HW_NRF_SPIM2 |
| select HAS_HW_NRF_SPIM3 |
| select HAS_HW_NRF_SPIM4 |
| select HAS_HW_NRF_SPIS0 |
| select HAS_HW_NRF_SPIS1 |
| select HAS_HW_NRF_SPIS2 |
| select HAS_HW_NRF_SPIS3 |
| select HAS_HW_NRF_SPU |
| select HAS_HW_NRF_TIMER0 |
| select HAS_HW_NRF_TIMER1 |
| select HAS_HW_NRF_TIMER2 |
| select HAS_HW_NRF_TWIM0 |
| select HAS_HW_NRF_TWIM1 |
| select HAS_HW_NRF_TWIM2 |
| select HAS_HW_NRF_TWIM3 |
| select HAS_HW_NRF_TWIS0 |
| select HAS_HW_NRF_TWIS1 |
| select HAS_HW_NRF_TWIS2 |
| select HAS_HW_NRF_TWIS3 |
| select HAS_HW_NRF_UARTE0 |
| select HAS_HW_NRF_UARTE1 |
| select HAS_HW_NRF_UARTE2 |
| select HAS_HW_NRF_UARTE3 |
| select HAS_HW_NRF_USBD |
| select HAS_HW_NRF_USBREG |
| select HAS_HW_NRF_WDT0 |
| select HAS_HW_NRF_WDT1 |
| |
| config SOC_NRF5340_CPUNET |
| depends on SOC_SERIES_NRF53X |
| bool |
| select HAS_HW_NRF_ACL |
| select HAS_HW_NRF_CLOCK |
| select HAS_HW_NRF_CCM |
| select HAS_HW_NRF_CCM_LFLEN_8BIT |
| select HAS_HW_NRF_DPPIC |
| select HAS_HW_NRF_ECB |
| select HAS_HW_NRF_EGU0 |
| select HAS_HW_NRF_GPIO0 |
| select HAS_HW_NRF_GPIO1 |
| select HAS_HW_NRF_GPIOTE |
| select HAS_HW_NRF_IPC |
| select HAS_HW_NRF_NVMC_PE |
| select HAS_HW_NRF_POWER |
| select HAS_HW_NRF_RADIO_BLE_2M |
| select HAS_HW_NRF_RADIO_BLE_CODED |
| select HAS_HW_NRF_RADIO_IEEE802154 |
| select HAS_HW_NRF_RNG |
| select HAS_HW_NRF_RTC0 |
| select HAS_HW_NRF_RTC1 |
| select HAS_HW_NRF_SPIM0 |
| select HAS_HW_NRF_SPIS0 |
| select HAS_HW_NRF_SWI0 |
| select HAS_HW_NRF_SWI1 |
| select HAS_HW_NRF_SWI2 |
| select HAS_HW_NRF_SWI3 |
| select HAS_HW_NRF_TEMP |
| select HAS_HW_NRF_TIMER0 |
| select HAS_HW_NRF_TIMER1 |
| select HAS_HW_NRF_TIMER2 |
| select HAS_HW_NRF_TWIM0 |
| select HAS_HW_NRF_TWIS0 |
| select HAS_HW_NRF_UARTE0 |
| select HAS_HW_NRF_WDT |
| select HAS_NO_SYS_PM |
| |
| choice |
| prompt "nRF53x MCU Selection" |
| depends on SOC_SERIES_NRF53X |
| |
| config SOC_NRF5340_CPUAPP_QKAA |
| bool "NRF5340_CPUAPP_QKAA" |
| select SOC_NRF5340_CPUAPP |
| |
| config SOC_NRF5340_CPUNET_QKAA |
| bool "NRF5340_CPUNET_QKAA" |
| select SOC_NRF5340_CPUNET |
| |
| endchoice |
| |
| |
| if SOC_NRF5340_CPUAPP |
| |
| config SOC_DCDC_NRF53X_APP |
| bool |
| help |
| Enable nRF53 series System on Chip Application MCU DC/DC converter. |
| |
| config SOC_DCDC_NRF53X_NET |
| bool |
| help |
| Enable nRF53 series System on Chip Network MCU DC/DC converter. |
| |
| config SOC_DCDC_NRF53X_HV |
| bool |
| help |
| Enable nRF53 series System on Chip High Voltage DC/DC converter. |
| |
| if !TRUSTED_EXECUTION_NONSECURE |
| |
| config SOC_ENABLE_LFXO |
| bool "Enable LFXO" |
| default y |
| help |
| Enable the low-frequency oscillator (LFXO) functionality on XL1 and |
| XL2 pins. |
| This option must be enabled if either application or network core is |
| to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular |
| GPIOs. |
| |
| choice SOC_LFXO_LOAD_CAPACITANCE |
| prompt "LFXO load capacitance" |
| depends on SOC_ENABLE_LFXO |
| default SOC_LFXO_CAP_INT_7PF |
| |
| config SOC_LFXO_CAP_EXTERNAL |
| bool "Use external load capacitors" |
| |
| config SOC_LFXO_CAP_INT_6PF |
| bool "6 pF internal load capacitance" |
| |
| config SOC_LFXO_CAP_INT_7PF |
| bool "7 pF internal load capacitance" |
| |
| config SOC_LFXO_CAP_INT_9PF |
| bool "9 pF internal load capacitance" |
| |
| endchoice |
| |
| choice SOC_HFXO_LOAD_CAPACITANCE |
| prompt "HFXO load capacitance" |
| default SOC_HFXO_CAP_DEFAULT |
| |
| config SOC_HFXO_CAP_DEFAULT |
| bool "SoC default" |
| help |
| When this option is used, the SoC initialization routine does not |
| touch the XOSC32MCAPS register value, so the default setting for |
| the SoC is in effect. Please note that this may not necessarily be |
| the reset value (0) for the register, as the register can be set |
| during the device trimming in the SystemInit() function. |
| |
| config SOC_HFXO_CAP_EXTERNAL |
| bool "Use external load capacitors" |
| |
| config SOC_HFXO_CAP_INTERNAL |
| bool "Use internal load capacitors" |
| |
| endchoice |
| |
| config SOC_HFXO_CAP_INT_VALUE_X2 |
| int "Doubled value of HFXO internal load capacitors (in pF)" |
| depends on SOC_HFXO_CAP_INTERNAL |
| range 14 40 |
| help |
| Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps |
| can be enabled on pins XC1 and XC2. This option specifies doubled |
| capacitance value for the two capacitors. Set it to 14 to get 7.0 pF |
| for each capacitor, 15 to get 7.5 pF, and so on. |
| |
| endif # !TRUSTED_EXECUTION_NONSECURE |
| |
| endif # SOC_NRF5340_CPUAPP |
| |
| |
| config NRF_ENABLE_CACHE |
| bool "Enable cache" |
| depends on (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) \ |
| || SOC_NRF5340_CPUNET |
| default y |
| help |
| Instruction and Data cache is available on nRF5340 CPUAPP |
| (Application MCU). It may only be accessed by Secure code. |
| |
| Instruction cache only (I-Cache) is available in nRF5340 |
| CPUNET (Network MCU). |