| /* |
| * Copyright (c) 2019, NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <init.h> |
| #include <fsl_iomuxc.h> |
| #include <fsl_gpio.h> |
| |
| static int mimxrt1015_evk_init(const struct device *dev) |
| { |
| ARG_UNUSED(dev); |
| |
| CLOCK_EnableClock(kCLOCK_Iomuxc); |
| CLOCK_EnableClock(kCLOCK_IomuxcSnvs); |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay) |
| IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_GPIO2_IO09, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_PUE(1) | |
| IOMUXC_SW_PAD_CTL_PAD_PUS(2) | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(4)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) |
| /* LPUART1 TX/RX */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart4), okay) |
| /* LPUART4 TX/RX */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_LPUART4_TX, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_LPUART4_RX, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_32_LPUART4_TX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_33_LPUART4_RX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) |
| /* LPI2C1 SCL, SDA */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL, 1); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA, 1); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL, |
| IOMUXC_SW_PAD_CTL_PAD_PUS(3) | |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA, |
| IOMUXC_SW_PAD_CTL_PAD_PUS(3) | |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) && CONFIG_SPI |
| /* LPSPI1 CS, SDO, SDI, CLK exposed as pins 3, 4, 5, and 6 on J19 */ |
| /* GPIO_AD_B0_10 is configured as LPSPI1_SCK */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK, 0U); |
| /* GPIO_AD_B0_11 is configured as LPSPI1_PCS0 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0, 0U); |
| /* GPIO_AD_B0_12 is configured as LPSPI1_SDO */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO, 0U); |
| /* GPIO_AD_B0_13 is configured as LPSPI1_SDI */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI, 0U); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(adc1), okay) & CONFIG_ADC |
| /* ADC1 Channels 1 and 13 exposed as pins 2 and 1 on J18 of eval board */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_GPIO1_IO14, 0U); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, 0U); |
| |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_GPIO1_IO14, |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| return 0; |
| } |
| |
| SYS_INIT(mimxrt1015_evk_init, PRE_KERNEL_1, 0); |