| # Copyright (c) 2022 Intel Corporation |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| if SOC_SERIES_INTEL_ACE |
| |
| config SOC_SERIES |
| string |
| default "ace" |
| |
| config SOC_TOOLCHAIN_NAME |
| string |
| default "intel_s1000" |
| |
| config SMP |
| default y |
| |
| # MTL leaves the upper mapping in the same spot as cAVS, but moves the |
| # lower one inexplicably. |
| config XTENSA_UNCACHED_REGION |
| default 2 |
| |
| # Parameters for gen_isr_tables.py: |
| |
| config 2ND_LVL_INTR_00_OFFSET |
| default 4 |
| |
| config MULTI_LEVEL_INTERRUPTS |
| default y |
| |
| config MAX_IRQ_PER_AGGREGATOR |
| default 29 |
| |
| config NUM_2ND_LEVEL_AGGREGATORS |
| default 1 |
| |
| config 2ND_LVL_ISR_TBL_OFFSET |
| default 9 |
| |
| config 2ND_LEVEL_INTERRUPTS |
| default y |
| |
| config XTENSA_TIMER |
| default n |
| |
| config XTENSA_TIMER_ID |
| default 0 |
| |
| config SYS_CLOCK_HW_CYCLES_PER_SEC |
| default 400000000 if XTENSA_TIMER |
| default 19200000 if INTEL_ADSP_TIMER |
| |
| config SYS_CLOCK_TICKS_PER_SEC |
| default 50000 |
| |
| config DYNAMIC_INTERRUPTS |
| default y |
| |
| if LOG |
| |
| config LOG_BACKEND_ADSP |
| default y |
| |
| endif # LOG |
| |
| source "soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace*" |
| |
| endif # SOC_SERIES_INTEL_ACE |