tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/clear_clocks.overlay

/*
 * Copyright (c) 2021 Linaro Limited
 * Copyright (c) 2023 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Warning: This overlay clears clocks back to a state equivalent to what could
 * be found in stm32h5.dtsi
 */

/* Keep csi on to be the usart1-console clock */
&clk_csi {
	status = "okay";
};

&usart1 {
	clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>,
		<&rcc STM32_SRC_CSI USART1_SEL(4)>;
};

&clk_hse {
	status = "disabled";
	/delete-property/ clock-frequency;
	/delete-property/ hse-bypass;
};

&clk_hsi {
	status = "disabled";
	/delete-property/ hsi-div;
};

&clk_lse {
	status = "disabled";
};

&pll {
	/delete-property/ div-m;
	/delete-property/ mul-n;
	/delete-property/ div-p;
	/delete-property/ div-q;
	/delete-property/ div-r;
	/delete-property/ clocks;
	status = "disabled";
};


&pll2 {
	/delete-property/ div-m;
	/delete-property/ mul-n;
	/delete-property/ div-p;
	/delete-property/ div-q;
	/delete-property/ div-r;
	/delete-property/ clocks;
	status = "disabled";
};

&rcc {
	/delete-property/ clocks;
	/delete-property/ clock-frequency;
	/delete-property/ ahb-prescaler;
	/delete-property/ apb1-prescaler;
	/delete-property/ apb2-prescaler;
	/delete-property/ apb3-prescaler;
};