blob: ddb941b0bac90a5671e60042577f20ae055b2da9 [file] [log] [blame]
/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
status = "okay";
};
&pll {
div-m = <4>;
mul-n = <30>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(240)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};