-arcv2em | |
-core3 | |
-rgf_num_banks=1 | |
-rgf_banked_regs=32 | |
-rgf_num_wr_ports=2 | |
-Xcode_density | |
-Xdiv_rem=radix2 | |
-turbo_boost | |
-Xswap | |
-Xbitscan | |
-Xmpy_option=mpyd | |
-mpu | |
-mpu_regions=16 | |
-Xshift_assist | |
-Xbarrel_shifter | |
-Xdsp2 | |
-Xdsp_complex | |
-Xdsp_divsqrt=radix2 | |
-Xdsp_itu | |
-Xdsp_accshift=full | |
-Xagu_large | |
-Xagu_wb_depth=4 | |
-Xagu_accord | |
-Xxy | |
-Xxy_config=dccm_x_y | |
-Xxy_size=64K | |
-Xxy_interleave | |
-Xxy_x_base=0xc0000000 | |
-Xxy_y_base=0xe0000000 | |
-Xfpus_div | |
-Xfpu_mac | |
-Xfpuda | |
-Xfpus_mpy_slow | |
-Xfpus_div_slow | |
-Xtimer0 | |
-Xtimer0_level=1 | |
-Xtimer1 | |
-Xtimer1_level=0 | |
-action_points=2 | |
-Xstack_check | |
-dmp_peripheral | |
-smart_stack_entries=8 | |
-interrupts=20 | |
-interrupt_priorities=4 | |
-ext_interrupts=16 | |
-interrupt_base=0x0 | |
-dcache=16384,32,2,a | |
-dcache_feature=2 | |
-icache=16384,32,2,a | |
-icache_feature=2 | |
-dccm_size=0x100000 | |
-dccm_base=0x80000000 | |
-dccm_interleave | |
-iccm0_size=0x100000 | |
-iccm0_base=0x00000000 | |
-Xpct_counters=8 | |
-dmac | |
-dmac_channels=2 | |
-dmac_registers=0 | |
-dmac_fifo_depth=2 | |
-dmac_int_config=single_internal | |
-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24 | |
-noprofile | |
-Xunaligned |