blob: 41fd7d9d2101fa4177d680ba397130851a5ad67a [file] [log] [blame]
/*
* NOTE: Autogenerated file by gen_board_pinctrl.py
* for MK82FN256VLL15/signal_configuration.xml
*
* Copyright (c) 2022, NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/kinetis/MK82FN256VLL15-pinctrl.h>
&pinctrl {
adc0_default: adc0_default {
group0 {
pinmux = <ADC0_SE15_PTC1>;
drive-strength = "low";
slew-rate = "fast";
};
};
ftm3_default: ftm3_default {
group0 {
pinmux = <FTM3_CH4_PTC8>,
<FTM3_CH5_PTC9>,
<FTM3_CH6_PTC10>;
drive-strength = "low";
slew-rate = "fast";
};
};
i2c0_default: i2c0_default {
group0 {
pinmux = <I2C0_SCL_PTB2>,
<I2C0_SDA_PTB3>;
drive-strength = "low";
drive-open-drain;
slew-rate = "fast";
};
};
i2c3_default: i2c3_default {
group0 {
pinmux = <I2C3_SCL_PTA2>,
<I2C3_SDA_PTA1>;
drive-strength = "low";
drive-open-drain;
bias-pull-up;
slew-rate = "fast";
};
};
lpuart0_default: lpuart0_default {
group0 {
pinmux = <LPUART0_RX_PTB16>,
<LPUART0_TX_PTB17>;
drive-strength = "low";
slew-rate = "fast";
};
};
lpuart4_default: lpuart4_default {
group0 {
pinmux = <LPUART4_RX_PTC14>,
<LPUART4_TX_PTC15>;
drive-strength = "low";
slew-rate = "fast";
};
};
spi0_default: spi0_default {
group0 {
pinmux = <SPI0_SCK_PTD1>,
<SPI0_SOUT_PTD2>,
<SPI0_SIN_PTD3>,
<SPI0_PCS1_PTD4>;
drive-strength = "low";
slew-rate = "fast";
};
};
spi1_default: spi1_default {
group0 {
pinmux = <SPI1_SCK_PTE1>,
<SPI1_SOUT_PTE2>,
<SPI1_SIN_PTE4>,
<SPI1_PCS0_PTE5>;
drive-strength = "low";
slew-rate = "fast";
};
};
};