| /* |
| * Copyright (c) 2023 Intel Corporation. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include "skeleton.dtsi" |
| #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/pcie/pcie.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "intel,alder-lake"; |
| d-cache-line-size = <64>; |
| reg = <0>; |
| }; |
| |
| }; |
| |
| dram0: memory@0 { |
| device_type = "memory"; |
| reg = <0x0 DT_DRAM_SIZE>; |
| }; |
| |
| intc: ioapic@fec00000 { |
| compatible = "intel,ioapic"; |
| #address-cells = <1>; |
| #interrupt-cells = <3>; |
| reg = <0xfec00000 0x1000>; |
| interrupt-controller; |
| }; |
| |
| intc_loapic: loapic@fee00000 { |
| compatible = "intel,loapic"; |
| reg = <0xfee00000 0x1000>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| #address-cells = <1>; |
| }; |
| |
| pcie0: pcie0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "pcie-controller"; |
| acpi-hid = "PNP0A08"; |
| ranges; |
| |
| smbus0: smbus0 { |
| compatible = "intel,pch-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| vendor-id = <0x8086>; |
| device-id = <0x54a3>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| status = "okay"; |
| }; |
| |
| uart0: uart0 { |
| compatible = "ns16550"; |
| |
| vendor-id = <0x8086>; |
| device-id = <0x54a8>; |
| |
| clock-frequency = <1843200>; |
| current-speed = <115200>; |
| reg-shift = <2>; |
| |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| status = "disabled"; |
| }; |
| |
| uart1_dma: uart1_dma { |
| compatible = "intel,lpss"; |
| #dma-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| uart1: uart1 { |
| compatible = "ns16550"; |
| vendor-id = <0x8086>; |
| device-id = <0x54A9>; |
| clock-frequency = <1843200>; |
| current-speed = <115200>; |
| reg-shift = <2>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| dmas = <&uart1_dma 0>, <&uart1_dma 1>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| uart2_dma: uart2_dma { |
| compatible = "intel,lpss"; |
| #dma-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| uart2: uart2 { |
| compatible = "ns16550"; |
| vendor-id = <0x8086>; |
| device-id = <0x54C7>; |
| clock-frequency = <1843200>; |
| current-speed = <115200>; |
| reg-shift = <2>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| dmas = <&uart2_dma 0>, <&uart2_dma 1>; |
| dma-names = "tx", "rx"; |
| |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c0 { |
| compatible = "snps,designware-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| vendor-id = <0x8086>; |
| device-id = <0x54e8>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| status = "okay"; |
| }; |
| |
| i2c1: i2c1 { |
| compatible = "snps,designware-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| vendor-id = <0x8086>; |
| device-id = <0x54e9>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c2 { |
| compatible = "snps,designware-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| vendor-id = <0x8086>; |
| device-id = <0x54ea>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c3 { |
| compatible = "snps,designware-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| vendor-id = <0x8086>; |
| device-id = <0x54eb>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c4 { |
| compatible = "snps,designware-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| vendor-id = <0x8086>; |
| device-id = <0x54c5>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c5 { |
| compatible = "snps,designware-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| vendor-id = <0x8086>; |
| device-id = <0x54c6>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| status = "disabled"; |
| }; |
| |
| spi0: spi0 { |
| compatible = "intel,penwell-spi"; |
| vendor-id = <0x8086>; |
| device-id = <0x54aa>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pw,cs-mode = <0>; |
| pw,cs-output = <0>; |
| pw,fifo-depth = <64>; |
| cs-gpios = <&gpio_4_e 10 GPIO_ACTIVE_LOW>; |
| clock-frequency = <100000000>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| status = "okay"; |
| }; |
| |
| spi1: spi1 { |
| compatible = "intel,penwell-spi"; |
| vendor-id = <0x8086>; |
| device-id = <0x54ab>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pw,cs-mode = <0>; |
| pw,cs-output = <0>; |
| pw,fifo-depth = <64>; |
| cs-gpios = <&gpio_4_f 16 GPIO_ACTIVE_LOW>; |
| clock-frequency = <100000000>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi2 { |
| compatible = "intel,penwell-spi"; |
| vendor-id = <0x8086>; |
| device-id = <0x54fb>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pw,cs-mode = <0>; |
| pw,cs-output = <0>; |
| pw,fifo-depth = <64>; |
| cs-gpios = <&gpio_1_d 9 GPIO_ACTIVE_LOW>; |
| clock-frequency = <100000000>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| status = "disabled"; |
| }; |
| |
| emmc: emmc0 { |
| compatible = "intel,emmc-host"; |
| vendor-id = <0x8086>; |
| device-id = <0x54C4>; |
| interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| max-bus-freq = <200000000>; |
| min-bus-freq = <400000>; |
| power-delay-ms = <500>; |
| mmc-hs400-1_8v; |
| mmc-hs200-1_8v; |
| |
| mmc { |
| compatible = "zephyr,mmc-disk"; |
| bus-width = <8>; |
| status = "okay"; |
| }; |
| |
| status = "okay"; |
| }; |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| vtd: vtd@fed91000 { |
| compatible = "intel,vt-d"; |
| reg = <0xfed91000 0x1000>; |
| status = "okay"; |
| }; |
| |
| uart0_legacy: uart@3f8 { |
| compatible = "ns16550"; |
| reg = <0x000003f8 0x100>; |
| io-mapped; |
| clock-frequency = <1843200>; |
| interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>; |
| interrupt-parent = <&intc>; |
| reg-shift = <0>; |
| status = "okay"; |
| }; |
| |
| gpio_0_b: gpio@fd6e0700 { |
| compatible = "intel,gpio"; |
| reg = <0xfd6e0700 0x1000>; |
| interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| group-index = <0x0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| ngpios = <24>; |
| pin-offset = <0>; |
| |
| status = "okay"; |
| }; |
| |
| gpio_0_a: gpio@fd6e09a0 { |
| compatible = "intel,gpio"; |
| reg = <0xfd6e09a0 0x1000>; |
| interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| group-index = <0x2>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| ngpios = <24>; |
| pin-offset = <41>; |
| |
| status = "okay"; |
| }; |
| |
| gpio_1_s: gpio@fd6d0700 { |
| compatible = "intel,gpio"; |
| reg = <0xfd6d0700 0x1000>; |
| interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| group-index = <0x0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| ngpios = <8>; |
| pin-offset = <0>; |
| |
| status = "okay"; |
| }; |
| |
| gpio_1_i: gpio@fd6d0780 { |
| compatible = "intel,gpio"; |
| reg = <0xfd6d0780 0x1000>; |
| interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| group-index = <0x1>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| ngpios = <19>; |
| pin-offset = <8>; |
| |
| status = "okay"; |
| }; |
| |
| |
| gpio_1_h: gpio@fd6d08c0 { |
| compatible = "intel,gpio"; |
| reg = <0xfd6d08c0 0x1000>; |
| interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| group-index = <0x2>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| ngpios = <24>; |
| pin-offset = <25>; |
| |
| status = "okay"; |
| }; |
| |
| gpio_1_d: gpio@fd6d0a40 { |
| compatible = "intel,gpio"; |
| reg = <0xfd6d0a40 0x1000>; |
| interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| group-index = <0x3>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| ngpios = <20>; |
| pin-offset = <49>; |
| |
| status = "okay"; |
| }; |
| |
| gpio_4_c: gpio@fd6a0700 { |
| compatible = "intel,gpio"; |
| reg = <0xfd6a0700 0x1000>; |
| interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| group-index = <0x0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| ngpios = <8>; |
| pin-offset = <0>; |
| |
| status = "okay"; |
| }; |
| |
| gpio_4_f: gpio@fd6a0880 { |
| compatible = "intel,gpio"; |
| reg = <0xfd6a0880 0x1000>; |
| interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| group-index = <0x1>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| ngpios = <24>; |
| pin-offset = <24>; |
| |
| status = "okay"; |
| }; |
| |
| gpio_4_e: gpio@fd6a0a70 { |
| compatible = "intel,gpio"; |
| reg = <0xfd6a0a70 0x1000>; |
| interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| group-index = <0x3>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| ngpios = <24>; |
| pin-offset = <57>; |
| |
| status = "okay"; |
| }; |
| |
| gpio_5_r: gpio@fd690700 { |
| compatible = "intel,gpio"; |
| reg = <0xfd690700 0x1000>; |
| interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; |
| interrupt-parent = <&intc>; |
| |
| group-index = <0x0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| ngpios = <8>; |
| pin-offset = <0>; |
| |
| status = "okay"; |
| }; |
| |
| tgpio: tgpio@fe001200 { |
| compatible = "intel,timeaware-gpio"; |
| reg = <0xfe001200 0x100>; |
| timer-clock = <19200000>; |
| max-pins = <2>; |
| status = "okay"; |
| }; |
| |
| hpet: hpet@fed00000 { |
| compatible = "intel,hpet"; |
| reg = <0xfed00000 0x400>; |
| interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; |
| interrupt-parent = <&intc>; |
| |
| status = "okay"; |
| }; |
| |
| rtc: counter: rtc@70 { |
| compatible = "motorola,mc146818"; |
| reg = <0x70 0x0D 0x71 0x0D>; |
| interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>; |
| interrupt-parent = <&intc>; |
| alarms-count = <1>; |
| |
| status = "okay"; |
| }; |
| |
| tco_wdt: tco_wdt@400 { |
| compatible = "intel,tco-wdt"; |
| reg = <0x0400 0x20>; |
| status = "disabled"; |
| }; |
| |
| pwm0: pwm0@fd6d0000 { |
| compatible = "intel,blinky-pwm"; |
| reg = <0xfd6d0000 0x400>; |
| reg-offset = <0x204>; |
| clock-frequency = <32768>; |
| max-pins = <1>; |
| #pwm-cells = <2>; |
| status = "okay"; |
| }; |
| }; |
| }; |
