blob: b53203be760188ca77bb2e9984d03d007f3ead92 [file] [log] [blame]
/*
* Copyright (c) 2023 Rahul Arasikere
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f7/stm32f7.dtsi>
/ {
/* 128KB DTCM @ 20000000, 368KB SRAM1 @ 20020000,
* 16KB SRAM2 @ 2007C000
*/
sram0: memory@20020000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20020000 DT_SIZE_K(384)>;
zephyr,memory-region = "SRAM0";
};
dtcm: memory@20000000 {
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};
soc {
compatible = "st,stm32f765", "st,stm32f7", "simple-bus";
pinctrl: pin-controller@40020000 {
reg = <0x40020000 0x2C00>;
gpioj: gpio@40022400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
};
gpiok: gpio@40022800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
};
};
i2c4: i2c@40006000 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40006000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
interrupts = <95 0>, <96 0>;
interrupt-names = "event", "error";
status = "disabled";
};
spi6: spi@40015400 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
interrupts = <86 5>;
status = "disabled";
};
mac: ethernet@40028000 {
compatible = "st,stm32-ethernet";
reg = <0x40028000 0x8000>;
interrupts = <61 0>;
clock-names = "stmmaceth", "mac-clk-tx",
"mac-clk-rx", "mac-clk-ptp";
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
<&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
<&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
<&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
status = "disabled";
};
sdmmc2: sdmmc@40011c00 {
compatible = "st,stm32-sdmmc";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
resets = <&rctl STM32_RESET(APB2, 7U)>;
interrupts = <103 0>;
status = "disabled";
};
};
smbus4: smbus4 {
compatible = "st,stm32-smbus";
#address-cells = <1>;
#size-cells = <0>;
i2c = <&i2c4>;
status = "disabled";
};
};