| /* |
| * Copyright (c) 2021 Guðni Már Gilbert |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <st/g4/stm32g4.dtsi> |
| |
| / { |
| soc { |
| compatible = "st,stm32g491", "st,stm32g4", "simple-bus"; |
| |
| fdcan2: can@40006800 { |
| compatible = "st,stm32-fdcan"; |
| reg = <0x40006800 0x400>, <0x4000a400 0x6a0>; |
| reg-names = "m_can", "message_ram"; |
| interrupts = <86 0>, <87 0>; |
| interrupt-names = "int0", "int1"; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; |
| bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; |
| sample-point = <875>; |
| sample-point-data = <875>; |
| status = "disabled"; |
| }; |
| |
| timers20: timers@40015000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40015000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>; |
| resets = <&rctl STM32_RESET(APB2, 20U)>; |
| interrupts = <77 0>, <78 0>, <79 0>, <80 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| dma1: dma@40020000 { |
| interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 96 0>; |
| dma-requests = <8>; |
| }; |
| |
| dma2: dma@40020400 { |
| interrupts = <56 0 57 0 58 0 59 0 60 0 97 0 98 0 99 0>; |
| dma-requests = <8>; |
| dma-offset = <8>; |
| }; |
| |
| dmamux1: dmamux@40020800 { |
| dma-channels = <16>; |
| }; |
| |
| adc3: adc@50000400 { |
| compatible = "st,stm32-adc"; |
| reg = <0x50000400 0x100>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00004000>; |
| interrupts = <47 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <3 7 13 25 48 93 248 641>; |
| st,adc-sequencer = <FULLY_CONFIGURABLE>; |
| }; |
| |
| uart5: serial@40005000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40005000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; |
| resets = <&rctl STM32_RESET(APB1L, 20U)>; |
| interrupts = <53 0>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
