blob: 7bb62de1f22f7bef0c7e193d972b3d3e270d34e9 [file] [log] [blame]
/*
* Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com>
* Copyright (c) 2019 Centaur Analytics, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv6-m.dtsi>
#include <zephyr/dt-bindings/clock/stm32l0_clock.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
#include <zephyr/dt-bindings/dma/stm32_dma.h>
#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
#include <zephyr/dt-bindings/reset/stm32l0_reset.h>
#include <freq.h>
/ {
chosen {
zephyr,flash-controller = &flash;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0+";
reg = <0>;
cpu-power-states = <&stop>;
};
power-states {
stop: stop {
compatible = "zephyr,power-state";
power-state-name = "suspend-to-idle";
min-residency-us = <2000>;
exit-latency-us = <750>;
};
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "st,stm32-hse-clock";
status = "disabled";
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(16)>;
status = "disabled";
};
clk_msi: clk-msi {
#clock-cells = <0>;
compatible = "st,stm32l0-msi-clock";
msi-range = <5>; /* 2.1MHz (reset value) */
status = "disabled";
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(37)>;
status = "disabled";
};
pll: pll {
#clock-cells = <0>;
compatible = "st,stm32l0-pll-clock";
status = "disabled";
};
};
soc {
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
interrupts = <2 0>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
prescaler = <32768>;
status = "disabled";
bbram: backup_regs {
compatible = "st,stm32-bbram";
st,backup-regs = <5>;
status = "disabled";
};
};
flash: flash-controller@40022000 {
compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
reg = <0x40022000 0x400>;
interrupts = <3 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "st,stm32-nv-flash", "soc-nv-flash";
write-block-size = <4>;
/* maximum erase time(ms) for a 128B page */
max-erase-time = <4>;
};
};
rcc: rcc@40021000 {
compatible = "st,stm32-rcc";
#clock-cells = <2>;
reg = <0x40021000 0x400>;
rctl: reset-controller {
compatible = "st,stm32-rcc-rctl";
#reset-cells = <1>;
};
};
exti: interrupt-controller@40010400 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
reg = <0x40010400 0x400>;
num-lines = <16>;
interrupts = <5 0>, <6 0>, <7 0>;
interrupt-names = "line0-1", "line2-3", "line4-15";
line-ranges = <0 2>, <2 2>, <4 12>;
};
pinctrl: pin-controller@50000000 {
compatible = "st,stm32-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x2000>;
gpioa: gpio@50000000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x50000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>;
};
gpiob: gpio@50000400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x50000400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>;
};
gpioc: gpio@50000800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x50000800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>;
};
gpiod: gpio@50000c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x50000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>;
};
gpioh: gpio@50001c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x50001c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000080>;
};
};
iwdg: watchdog@40003000 {
compatible = "st,stm32-watchdog";
reg = <0x40003000 0x400>;
status = "disabled";
};
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
interrupts = <0 2>;
status = "disabled";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
interrupts = <28 0>;
status = "disabled";
};
lpuart1: serial@40004800 {
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <29 0>;
status = "disabled";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
interrupts = <23 0>;
interrupt-names = "combined";
status = "disabled";
};
spi1: spi@40013000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <25 3>;
status = "disabled";
};
timers2: timers@40000000 {
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
resets = <&rctl STM32_RESET(APB1, 0U)>;
interrupts = <15 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
};
};
timers21: timers@40010800 {
compatible = "st,stm32-timers";
reg = <0x40010800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000004>;
resets = <&rctl STM32_RESET(APB2, 2U)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
};
};
lptim1: timers@40007c00 {
compatible = "st,stm32-lptim";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40007c00 0x400>;
interrupts = <13 1>;
interrupt-names = "wakeup";
status = "disabled";
};
adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
interrupts = <12 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
STM32_ADC_RES(8, 0x02)
STM32_ADC_RES(6, 0x03)>;
sampling-times = <2 4 8 13 20 40 80 161>;
num-sampling-time-common-channels = <1>;
st,adc-sequencer = <NOT_FULLY_CONFIGURABLE>;
};
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <3>;
reg = <0x40020000 0x400>;
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
status = "disabled";
};
eeprom: eeprom@8080000{
compatible = "st,stm32-eeprom";
status = "disabled";
};
};
die_temp: dietemp {
compatible = "st,stm32-temp-cal";
ts-cal1-addr = <0x1FF8007A>;
ts-cal2-addr = <0x1FF8007E>;
ts-cal1-temp = <30>;
ts-cal2-temp = <130>;
ts-cal-vrefanalog = <3000>;
io-channels = <&adc1 18>;
status = "disabled";
};
vref: vref {
compatible = "st,stm32-vref";
vrefint-cal-addr = <0x1FF80078>;
vrefint-cal-mv = <3000>;
io-channels = <&adc1 17>;
status = "disabled";
};
smbus1: smbus1 {
compatible = "st,stm32-smbus";
#address-cells = <1>;
#size-cells = <0>;
i2c = <&i2c1>;
status = "disabled";
};
};
&nvic {
arm,num-irq-priority-bits = <2>;
};