dts/bindings/clock/renesas,ra-clock-generation-circuit.yaml

# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
# SPDX-License-Identifier: Apache-2.0

description: Renesas RA series Clock Generation Circuit

compatible: "renesas,ra-clock-generation-circuit"

include: [clock-controller.yaml, base.yaml]

properties:
  reg:
    required: true

  iclk-div:
    type: int
    description: Division factor for ICLK

  fclk-div:
    type: int
    description: Division factor for FCLK

  pclka-div:
    type: int
    description: Division factor for PCLKA

  pclkb-div:
    type: int
    description: Division factor for PCLKB

  pclkc-div:
    type: int
    description: Division factor for PCLKC

  pclkd-div:
    type: int
    description: Division factor for PCLKD

  clock-source:
    type: phandle
    description: System clock source

  "#clock-cells":
    const: 1

clock-cells:
  - id