dts/xtensa/nxp/nxp_imx8.dtsi

/*
 * Copyright (c) 2021 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <xtensa/xtensa.dtsi>
#include <mem.h>
#include <zephyr/dt-bindings/clock/imx_ccm.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "cdns,tensilica-xtensa-lx6";
			reg = <0>;

			#address-cells = <1>;
			#size-cells = <0>;

			clic: interrupt-controller@0 {
				compatible = "cdns,xtensa-core-intc";
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <3>;
			};
		};
	};

	sram0: memory@92400000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x92400000 DT_SIZE_K(512)>;
	};

	sram1: memory@92c00000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x92c00000 DT_SIZE_K(512)>;
	};

	/* LSIO MU2, used to interact with the SCFW */
	scu_mu: mailbox@5d1d0000 {
		reg = <0x5d1d0000 DT_SIZE_K(64)>;
	};

	scu: system-controller {
		ccm: clock-controller {
			compatible = "nxp,imx-ccm";
			#clock-cells = <3>;
		};

		iomuxc: iomuxc {
			compatible = "nxp,imx-iomuxc-scu";
			pinctrl: pinctrl {
				compatible = "nxp,imx8-pinctrl";
			};
		};
	};

	lpuart2: serial@5a080000 {
		compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
		reg = <0x5a080000 DT_SIZE_K(4)>;
		/* TODO: THIS INTID IS JUST A DUMMY ONE UNTIL IRQ_STEER
		 * DRIVER CAN BE USED ON i.MX8QM/QXP. DO NOT ATTEMPT TO
		 * ENABLE UART INTERRUPT SUPPORT.
		 *
		 * THE CURRENT INTID VALUE IS CHOSEN SUCH THAT gen_isr_tables.py
		 * WILL BREAK IF YOU ATTEMPT TO IRQ_CONNECT().
		 */
		interrupt-parent = <&clic>;
		interrupts = <259 0 0>;
		/* this is actually LPUART2 clock but the macro indexing starts at 1 */
		clocks = <&ccm IMX_CCM_LPUART3_CLK 0x0 0x0>;
		status = "disabled";
	};
};