| /* |
| * Copyright (c) 2019 Intel Corporation |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| /* SoC level DTS fixup file */ |
| |
| #define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS |
| #define DT_L2_SRAM_SIZE (CONFIG_SRAM_SIZE * 1024) |
| |
| #define DT_LP_SRAM_BASE DT_INST_1_MMIO_SRAM_BASE_ADDRESS |
| #define DT_LP_SRAM_SIZE DT_INST_1_MMIO_SRAM_SIZE |
| |
| #define DT_CAVS_ICTL_BASE_ADDR DT_INTEL_CAVS_INTC_1600_BASE_ADDRESS |
| #define DT_CAVS_ICTL_0_IRQ DT_INTEL_CAVS_INTC_1600_IRQ_0 |
| #define DT_CAVS_ICTL_0_IRQ_PRI DT_INTEL_CAVS_INTC_1600_IRQ_0_PRIORITY |
| #define DT_CAVS_ICTL_0_IRQ_FLAGS DT_INTEL_CAVS_INTC_1600_IRQ_0_SENSE |
| |
| #define DT_CAVS_ICTL_1_IRQ DT_INTEL_CAVS_INTC_1610_IRQ_0 |
| #define DT_CAVS_ICTL_1_IRQ_PRI DT_INTEL_CAVS_INTC_1610_IRQ_0_PRIORITY |
| #define DT_CAVS_ICTL_1_IRQ_FLAGS DT_INTEL_CAVS_INTC_1610_IRQ_0_SENSE |
| |
| #define DT_CAVS_ICTL_2_IRQ DT_INTEL_CAVS_INTC_1620_IRQ_0 |
| #define DT_CAVS_ICTL_2_IRQ_PRI DT_INTEL_CAVS_INTC_1620_IRQ_0_PRIORITY |
| #define DT_CAVS_ICTL_2_IRQ_FLAGS DT_INTEL_CAVS_INTC_1620_IRQ_0_SENSE |
| |
| #define DT_CAVS_ICTL_3_IRQ DT_INTEL_CAVS_INTC_1630_IRQ_0 |
| #define DT_CAVS_ICTL_3_IRQ_PRI DT_INTEL_CAVS_INTC_1630_IRQ_0_PRIORITY |
| #define DT_CAVS_ICTL_3_IRQ_FLAGS DT_INTEL_CAVS_INTC_1630_IRQ_0_SENSE |
| |
| /* End of SoC Level DTS fixup file */ |