boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig

# SPDX-License-Identifier: Apache-2.0

CONFIG_SOC_SERIES_STM32H7X=y
CONFIG_SOC_STM32H723XX=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=550000000

CONFIG_BOARD_NUCLEO_H723ZG=y

# Enable MPU
CONFIG_ARM_MPU=y

# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y

# Enable UART
CONFIG_SERIAL=y

# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

# Enable Pinmux
CONFIG_PINMUX=y

# Enable GPIO
CONFIG_GPIO=y

# Clock Configuration
CONFIG_CLOCK_CONTROL=y

CONFIG_CLOCK_STM32_D1CPRE=1

# HCLK: 275MHz
CONFIG_CLOCK_STM32_HPRE=2

# APB1: 137.5MHz
CONFIG_CLOCK_STM32_D2PPRE1=2

# APB2: 137.5MHz
CONFIG_CLOCK_STM32_D2PPRE2=2

# APB3: 137.5MHz
CONFIG_CLOCK_STM32_D1PPRE=2

# APB4: 137.5MHz
CONFIG_CLOCK_STM32_D3PPRE=2

# STLINK provides 8MHz clock input
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y

# Use HSE (bypass) as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32_HSE_BYPASS=y

# Produce 550MHz clock at PLL1 output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=275
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=1
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2