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Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +02001/*
2 * Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
Martin Jäger2a035f72022-10-06 13:46:54 +02003 * Copyright (c) 2022 Martin Jäger <martin@libre.solar>
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +02004 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#define DT_DRV_COMPAT espressif_esp32_twai
9
Henrik Brix Anderseneb9bbf42023-02-07 10:12:02 +010010#include <zephyr/drivers/can/can_sja1000.h>
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +020011
12#include <zephyr/drivers/can.h>
13#include <zephyr/drivers/clock_control.h>
14#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
15#include <zephyr/drivers/pinctrl.h>
16#include <zephyr/logging/log.h>
17
18#include <soc.h>
19
20LOG_MODULE_REGISTER(can_esp32_twai, CONFIG_CAN_LOG_LEVEL);
21
Martin Jäger2a035f72022-10-06 13:46:54 +020022/*
23 * Newer ESP32-series MCUs like ESP32-C3 and ESP32-S2 have some slightly different registers
24 * compared to the original ESP32, which is fully compatible with the SJA1000 controller.
25 *
26 * The names with TWAI_ prefixes from Espressif reference manuals are used for these incompatible
27 * registers.
28 */
Marek Matej6b57b3b2023-07-20 18:24:09 +020029#ifndef CONFIG_SOC_SERIES_ESP32
Martin Jäger2a035f72022-10-06 13:46:54 +020030
31/* TWAI_BUS_TIMING_0_REG is incompatible with CAN_SJA1000_BTR0 */
32#define TWAI_BUS_TIMING_0_REG (6U)
33#define TWAI_BAUD_PRESC_MASK GENMASK(12, 0)
34#define TWAI_SYNC_JUMP_WIDTH_MASK GENMASK(15, 14)
35#define TWAI_BAUD_PRESC_PREP(brp) FIELD_PREP(TWAI_BAUD_PRESC_MASK, brp)
36#define TWAI_SYNC_JUMP_WIDTH_PREP(sjw) FIELD_PREP(TWAI_SYNC_JUMP_WIDTH_MASK, sjw)
37
38/*
39 * TWAI_BUS_TIMING_1_REG is compatible with CAN_SJA1000_BTR1, but needed here for the custom
40 * set_timing() function.
41 */
42#define TWAI_BUS_TIMING_1_REG (7U)
43#define TWAI_TIME_SEG1_MASK GENMASK(3, 0)
44#define TWAI_TIME_SEG2_MASK GENMASK(6, 4)
45#define TWAI_TIME_SAMP BIT(7)
46#define TWAI_TIME_SEG1_PREP(seg1) FIELD_PREP(TWAI_TIME_SEG1_MASK, seg1)
47#define TWAI_TIME_SEG2_PREP(seg2) FIELD_PREP(TWAI_TIME_SEG2_MASK, seg2)
48
49/* TWAI_CLOCK_DIVIDER_REG is incompatible with CAN_SJA1000_CDR */
50#define TWAI_CLOCK_DIVIDER_REG (31U)
51#define TWAI_CD_MASK GENMASK(7, 0)
52#define TWAI_CLOCK_OFF BIT(8)
53
54/*
55 * Further incompatible registers currently not used by the driver:
56 * - TWAI_STATUS_REG has new bit 8: TWAI_MISS_ST
57 * - TWAI_INT_RAW_REG has new bit 8: TWAI_BUS_STATE_INT_ST
58 * - TWAI_INT_ENA_REG has new bit 8: TWAI_BUS_STATE_INT_ENA
59 */
60#else
61
62/* Redefinitions of the SJA1000 CDR bits to simplify driver config */
63#define TWAI_CD_MASK GENMASK(2, 0)
64#define TWAI_CLOCK_OFF BIT(3)
65
Marek Matej6b57b3b2023-07-20 18:24:09 +020066#endif /* !CONFIG_SOC_SERIES_ESP32 */
Martin Jäger2a035f72022-10-06 13:46:54 +020067
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +020068struct can_esp32_twai_config {
69 mm_reg_t base;
70 const struct pinctrl_dev_config *pcfg;
71 const struct device *clock_dev;
72 const clock_control_subsys_t clock_subsys;
73 int irq_source;
Marek Matej6b57b3b2023-07-20 18:24:09 +020074#ifndef CONFIG_SOC_SERIES_ESP32
Martin Jäger2a035f72022-10-06 13:46:54 +020075 /* 32-bit variant of output clock divider register required for non-ESP32 MCUs */
76 uint32_t cdr32;
Marek Matej6b57b3b2023-07-20 18:24:09 +020077#endif /* !CONFIG_SOC_SERIES_ESP32 */
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +020078};
79
80static uint8_t can_esp32_twai_read_reg(const struct device *dev, uint8_t reg)
81{
82 const struct can_sja1000_config *sja1000_config = dev->config;
83 const struct can_esp32_twai_config *twai_config = sja1000_config->custom;
84 mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t);
85
86 return sys_read32(addr) & 0xFF;
87}
88
89static void can_esp32_twai_write_reg(const struct device *dev, uint8_t reg, uint8_t val)
90{
91 const struct can_sja1000_config *sja1000_config = dev->config;
92 const struct can_esp32_twai_config *twai_config = sja1000_config->custom;
93 mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t);
94
95 sys_write32(val & 0xFF, addr);
96}
97
Marek Matej6b57b3b2023-07-20 18:24:09 +020098#ifndef CONFIG_SOC_SERIES_ESP32
Martin Jäger2a035f72022-10-06 13:46:54 +020099
100/*
101 * Required for newer ESP32-series MCUs which violate the original SJA1000 8-bit register size.
102 */
103static void can_esp32_twai_write_reg32(const struct device *dev, uint8_t reg, uint32_t val)
104{
105 const struct can_sja1000_config *sja1000_config = dev->config;
106 const struct can_esp32_twai_config *twai_config = sja1000_config->custom;
107 mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t);
108
109 sys_write32(val, addr);
110}
111
112/*
113 * Custom implementation instead of can_sja1000_set_timing required because TWAI_BUS_TIMING_0_REG
114 * is incompatible with CAN_SJA1000_BTR0.
115 */
116static int can_esp32_twai_set_timing(const struct device *dev, const struct can_timing *timing)
117{
118 struct can_sja1000_data *data = dev->data;
119 uint8_t btr0;
120 uint8_t btr1;
Martin Jäger2a035f72022-10-06 13:46:54 +0200121
Henrik Brix Andersenb41714b2024-01-17 19:52:49 +0100122 if (data->common.started) {
Martin Jäger2a035f72022-10-06 13:46:54 +0200123 return -EBUSY;
124 }
125
126 k_mutex_lock(&data->mod_lock, K_FOREVER);
127
Martin Jäger2a035f72022-10-06 13:46:54 +0200128 btr0 = TWAI_BAUD_PRESC_PREP(timing->prescaler - 1) |
Henrik Brix Andersena9d39352023-09-22 12:07:16 +0200129 TWAI_SYNC_JUMP_WIDTH_PREP(timing->sjw - 1);
Martin Jäger2a035f72022-10-06 13:46:54 +0200130 btr1 = TWAI_TIME_SEG1_PREP(timing->phase_seg1 - 1) |
131 TWAI_TIME_SEG2_PREP(timing->phase_seg2 - 1);
132
Henrik Brix Andersenb41714b2024-01-17 19:52:49 +0100133 if ((data->common.mode & CAN_MODE_3_SAMPLES) != 0) {
Martin Jäger2a035f72022-10-06 13:46:54 +0200134 btr1 |= TWAI_TIME_SAMP;
135 }
136
137 can_esp32_twai_write_reg32(dev, TWAI_BUS_TIMING_0_REG, btr0);
138 can_esp32_twai_write_reg32(dev, TWAI_BUS_TIMING_1_REG, btr1);
139
140 k_mutex_unlock(&data->mod_lock);
141
142 return 0;
143}
144
Marek Matej6b57b3b2023-07-20 18:24:09 +0200145#endif /* !CONFIG_SOC_SERIES_ESP32 */
Martin Jäger2a035f72022-10-06 13:46:54 +0200146
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200147static int can_esp32_twai_get_core_clock(const struct device *dev, uint32_t *rate)
148{
149 ARG_UNUSED(dev);
150
151 /* The internal clock operates at half of the oscillator frequency */
152 *rate = APB_CLK_FREQ / 2;
153
154 return 0;
155}
156
157static void IRAM_ATTR can_esp32_twai_isr(void *arg)
158{
159 const struct device *dev = (const struct device *)arg;
160
161 can_sja1000_isr(dev);
162}
163
164static int can_esp32_twai_init(const struct device *dev)
165{
166 const struct can_sja1000_config *sja1000_config = dev->config;
167 const struct can_esp32_twai_config *twai_config = sja1000_config->custom;
168 int err;
169
Henrik Brix Andersen035c7d22022-08-08 13:31:51 +0200170 if (!device_is_ready(twai_config->clock_dev)) {
171 LOG_ERR("clock control device not ready");
172 return -ENODEV;
173 }
174
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200175 err = pinctrl_apply_state(twai_config->pcfg, PINCTRL_STATE_DEFAULT);
176 if (err != 0) {
177 LOG_ERR("failed to configure TWAI pins (err %d)", err);
178 return err;
179 }
180
Henrik Brix Andersen035c7d22022-08-08 13:31:51 +0200181 err = clock_control_on(twai_config->clock_dev, twai_config->clock_subsys);
182 if (err != 0) {
183 LOG_ERR("failed to enable CAN clock (err %d)", err);
184 return err;
185 }
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200186
187 err = can_sja1000_init(dev);
188 if (err != 0) {
189 LOG_ERR("failed to initialize controller (err %d)", err);
190 return err;
191 }
192
Marek Matej6b57b3b2023-07-20 18:24:09 +0200193#ifndef CONFIG_SOC_SERIES_ESP32
Martin Jäger2a035f72022-10-06 13:46:54 +0200194 /*
195 * TWAI_CLOCK_DIVIDER_REG is incompatible with CAN_SJA1000_CDR for non-ESP32 MCUs
196 * - TWAI_CD has length of 8 bits instead of 3 bits
197 * - TWAI_CLOCK_OFF at BIT(8) instead of BIT(3)
198 * - TWAI_EXT_MODE bit missing (always "extended" = PeliCAN mode)
199 *
200 * Overwrite with 32-bit register variant configured via devicetree.
201 */
202 can_esp32_twai_write_reg32(dev, TWAI_CLOCK_DIVIDER_REG, twai_config->cdr32);
Marek Matej6b57b3b2023-07-20 18:24:09 +0200203#endif /* !CONFIG_SOC_SERIES_ESP32 */
Martin Jäger2a035f72022-10-06 13:46:54 +0200204
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200205 esp_intr_alloc(twai_config->irq_source, 0, can_esp32_twai_isr, (void *)dev, NULL);
206
207 return 0;
208}
209
210const struct can_driver_api can_esp32_twai_driver_api = {
211 .get_capabilities = can_sja1000_get_capabilities,
Henrik Brix Andersen180cdc12022-08-31 14:28:42 +0200212 .start = can_sja1000_start,
213 .stop = can_sja1000_stop,
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200214 .set_mode = can_sja1000_set_mode,
Marek Matej6b57b3b2023-07-20 18:24:09 +0200215#ifdef CONFIG_SOC_SERIES_ESP32
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200216 .set_timing = can_sja1000_set_timing,
Martin Jäger2a035f72022-10-06 13:46:54 +0200217#else
218 .set_timing = can_esp32_twai_set_timing,
Marek Matej6b57b3b2023-07-20 18:24:09 +0200219#endif /* CONFIG_SOC_SERIES_ESP32 */
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200220 .send = can_sja1000_send,
221 .add_rx_filter = can_sja1000_add_rx_filter,
222 .remove_rx_filter = can_sja1000_remove_rx_filter,
223 .get_state = can_sja1000_get_state,
224 .set_state_change_callback = can_sja1000_set_state_change_callback,
225 .get_core_clock = can_esp32_twai_get_core_clock,
226 .get_max_filters = can_sja1000_get_max_filters,
Henrik Brix Andersena57db0d2024-02-14 22:38:34 +0100227#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200228 .recover = can_sja1000_recover,
Henrik Brix Andersena57db0d2024-02-14 22:38:34 +0100229#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200230 .timing_min = CAN_SJA1000_TIMING_MIN_INITIALIZER,
Marek Matej6b57b3b2023-07-20 18:24:09 +0200231#ifdef CONFIG_SOC_SERIES_ESP32
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200232 .timing_max = CAN_SJA1000_TIMING_MAX_INITIALIZER,
Martin Jäger2a035f72022-10-06 13:46:54 +0200233#else
234 /* larger prescaler allowed for newer ESP32-series MCUs */
235 .timing_max = {
236 .sjw = 0x4,
237 .prop_seg = 0x0,
238 .phase_seg1 = 0x10,
239 .phase_seg2 = 0x8,
240 .prescaler = 0x2000,
241 }
Marek Matej6b57b3b2023-07-20 18:24:09 +0200242#endif /* CONFIG_SOC_SERIES_ESP32 */
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200243};
244
Marek Matej6b57b3b2023-07-20 18:24:09 +0200245#ifdef CONFIG_SOC_SERIES_ESP32
Martin Jäger2a035f72022-10-06 13:46:54 +0200246#define TWAI_CLKOUT_DIVIDER_MAX (14)
247#define TWAI_CDR32_INIT(inst)
248#else
249#define TWAI_CLKOUT_DIVIDER_MAX (490)
250#define TWAI_CDR32_INIT(inst) .cdr32 = CAN_ESP32_TWAI_DT_CDR_INST_GET(inst)
Marek Matej6b57b3b2023-07-20 18:24:09 +0200251#endif /* CONFIG_SOC_SERIES_ESP32 */
Martin Jäger2a035f72022-10-06 13:46:54 +0200252
253#define CAN_ESP32_TWAI_ASSERT_CLKOUT_DIVIDER(inst) \
254 BUILD_ASSERT(COND_CODE_0(DT_INST_NODE_HAS_PROP(inst, clkout_divider), (1), \
255 (DT_INST_PROP(inst, clkout_divider) == 1 || \
256 (DT_INST_PROP(inst, clkout_divider) % 2 == 0 && \
257 DT_INST_PROP(inst, clkout_divider) / 2 <= TWAI_CLKOUT_DIVIDER_MAX))), \
258 "TWAI clkout-divider from dts invalid")
259
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200260#define CAN_ESP32_TWAI_DT_CDR_INST_GET(inst) \
261 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, clkout_divider), \
Martin Jäger2a035f72022-10-06 13:46:54 +0200262 COND_CODE_1(DT_INST_PROP(inst, clkout_divider) == 1, (TWAI_CD_MASK), \
263 ((DT_INST_PROP(inst, clkout_divider)) / 2 - 1)), \
264 (TWAI_CLOCK_OFF))
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200265
266#define CAN_ESP32_TWAI_INIT(inst) \
267 PINCTRL_DT_INST_DEFINE(inst); \
268 \
269 static const struct can_esp32_twai_config can_esp32_twai_config_##inst = { \
270 .base = DT_INST_REG_ADDR(inst), \
271 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
272 .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(inst, offset), \
273 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
274 .irq_source = DT_INST_IRQN(inst), \
Martin Jäger2a035f72022-10-06 13:46:54 +0200275 TWAI_CDR32_INIT(inst) \
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200276 }; \
Martin Jäger2a035f72022-10-06 13:46:54 +0200277 CAN_ESP32_TWAI_ASSERT_CLKOUT_DIVIDER(inst); \
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200278 static const struct can_sja1000_config can_sja1000_config_##inst = \
279 CAN_SJA1000_DT_CONFIG_INST_GET(inst, &can_esp32_twai_config_##inst, \
Marek Matej938732c2023-06-23 11:43:03 +0200280 can_esp32_twai_read_reg, can_esp32_twai_write_reg, \
281 CAN_SJA1000_OCR_OCMODE_BIPHASE, \
282 COND_CODE_0(IS_ENABLED(CONFIG_SOC_SERIES_ESP32), (0), \
Henrik Brix Andersen621515c2024-02-26 22:38:26 +0100283 (CAN_ESP32_TWAI_DT_CDR_INST_GET(inst))), 25000); \
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200284 \
285 static struct can_sja1000_data can_sja1000_data_##inst = \
286 CAN_SJA1000_DATA_INITIALIZER(NULL); \
287 \
Henrik Brix Andersen49ab0b22023-09-20 17:40:07 +0200288 CAN_DEVICE_DT_INST_DEFINE(inst, can_esp32_twai_init, NULL, &can_sja1000_data_##inst, \
289 &can_sja1000_config_##inst, POST_KERNEL, \
290 CONFIG_CAN_INIT_PRIORITY, &can_esp32_twai_driver_api);
Henrik Brix Andersenaeb9fd62022-06-22 16:14:34 +0200291
292DT_INST_FOREACH_STATUS_OKAY(CAN_ESP32_TWAI_INIT)