blob: eace24fac700320c290c78308f61b6b5698cbd09 [file] [log] [blame]
Francisco Munoz278da902019-08-09 16:28:05 -07001/*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
Kumar Gala7a81cd92020-03-24 15:45:46 -05007#define DT_DRV_COMPAT microchip_xec_ps2
8
Francisco Munoz278da902019-08-09 16:28:05 -07009#include <errno.h>
10#include <device.h>
11#include <drivers/ps2.h>
12#include <soc.h>
13#include <logging/log.h>
14
15#define LOG_LEVEL CONFIG_PS2_LOG_LEVEL
16LOG_MODULE_REGISTER(ps2_mchp_xec);
17
18/* in 50us units */
19#define PS2_TIMEOUT 10000
20
21struct ps2_xec_config {
22 PS2_Type *base;
Kumar Galaa1b77fd2020-05-27 11:26:57 -050023 uint8_t girq_id;
24 uint8_t girq_bit;
25 uint8_t isr_nvic;
Francisco Munoz278da902019-08-09 16:28:05 -070026};
27
28struct ps2_xec_data {
29 ps2_callback_t callback_isr;
30 struct k_sem tx_lock;
31};
32
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +020033static int ps2_xec_configure(const struct device *dev,
34 ps2_callback_t callback_isr)
Francisco Munoz278da902019-08-09 16:28:05 -070035{
Tomasz Bursztykaaf6140c2020-05-28 20:44:16 +020036 const struct ps2_xec_config *config = dev->config;
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +020037 struct ps2_xec_data *data = dev->data;
Francisco Munoz278da902019-08-09 16:28:05 -070038 PS2_Type *base = config->base;
39
Kumar Galaa1b77fd2020-05-27 11:26:57 -050040 uint8_t __attribute__((unused)) dummy;
Francisco Munoz278da902019-08-09 16:28:05 -070041
42 if (!callback_isr) {
43 return -EINVAL;
44 }
45
46 data->callback_isr = callback_isr;
47
48 /* In case the self test for a PS2 device already finished and
49 * set the SOURCE bit to 1 we clear it before enabling the
50 * interrupts. Instances must be allocated before the BAT or
51 * the host may time out.
52 */
53 MCHP_GIRQ_SRC(config->girq_id) = BIT(config->girq_bit);
54 dummy = base->TRX_BUFF;
55 base->STATUS = MCHP_PS2_STATUS_RW1C_MASK;
56
57 /* Enable FSM and init instance in rx mode*/
58 base->CTRL = MCHP_PS2_CTRL_EN_POS;
59
60 /* We enable the interrupts in the EC aggregator so that the
61 * result can be forwarded to the ARM NVIC
62 */
63 MCHP_GIRQ_ENSET(config->girq_id) = BIT(config->girq_bit);
64
65 k_sem_give(&data->tx_lock);
66
67 return 0;
68}
69
70
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +020071static int ps2_xec_write(const struct device *dev, uint8_t value)
Francisco Munoz278da902019-08-09 16:28:05 -070072{
Tomasz Bursztykaaf6140c2020-05-28 20:44:16 +020073 const struct ps2_xec_config *config = dev->config;
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +020074 struct ps2_xec_data *data = dev->data;
Francisco Munoz278da902019-08-09 16:28:05 -070075 PS2_Type *base = config->base;
76 int i = 0;
77
Kumar Galaa1b77fd2020-05-27 11:26:57 -050078 uint8_t __attribute__((unused)) dummy;
Francisco Munoz278da902019-08-09 16:28:05 -070079
80 if (k_sem_take(&data->tx_lock, K_NO_WAIT)) {
81 return -EACCES;
82 }
83 /* Allow the PS2 controller to complete a RX transaction. This
84 * is because the channel may be actively receiving data.
85 * In addition, it is necessary to wait for a previous TX
86 * transaction to complete. The PS2 block has a single
87 * FSM.
88 */
89 while (((base->STATUS &
Francisco Munoz51e82852020-04-28 15:00:48 -070090 (MCHP_PS2_STATUS_RX_BUSY | MCHP_PS2_STATUS_TX_IDLE))
Francisco Munoz278da902019-08-09 16:28:05 -070091 != MCHP_PS2_STATUS_TX_IDLE) && (i < PS2_TIMEOUT)) {
92 k_busy_wait(50);
93 i++;
94 }
95
96 if (unlikely(i == PS2_TIMEOUT)) {
97 LOG_DBG("PS2 write timed out");
98 return -ETIMEDOUT;
99 }
100
101 /* Inhibit ps2 controller and clear status register */
102 base->CTRL = 0x00;
103
104 /* Read to clear data ready bit in the status register*/
105 dummy = base->TRX_BUFF;
Francisco Munoz51e82852020-04-28 15:00:48 -0700106 k_sleep(K_MSEC(1));
Francisco Munoz278da902019-08-09 16:28:05 -0700107 base->STATUS = MCHP_PS2_STATUS_RW1C_MASK;
Francisco Munoz51e82852020-04-28 15:00:48 -0700108
Francisco Munoz278da902019-08-09 16:28:05 -0700109 /* Switch the interface to TX mode and enable state machine */
110 base->CTRL = MCHP_PS2_CTRL_TR_TX | MCHP_PS2_CTRL_EN;
111
112 /* Write value to TX/RX register */
113 base->TRX_BUFF = value;
114
115 k_sem_give(&data->tx_lock);
116
117 return 0;
118}
119
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200120static int ps2_xec_inhibit_interface(const struct device *dev)
Francisco Munoz278da902019-08-09 16:28:05 -0700121{
Tomasz Bursztykaaf6140c2020-05-28 20:44:16 +0200122 const struct ps2_xec_config *config = dev->config;
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +0200123 struct ps2_xec_data *data = dev->data;
Francisco Munoz278da902019-08-09 16:28:05 -0700124 PS2_Type *base = config->base;
125
126 if (k_sem_take(&data->tx_lock, K_MSEC(10)) != 0) {
127 return -EACCES;
128 }
129
130 base->CTRL = 0x00;
131 MCHP_GIRQ_SRC(config->girq_id) = BIT(config->girq_bit);
132 NVIC_ClearPendingIRQ(config->isr_nvic);
133
134 k_sem_give(&data->tx_lock);
135
136 return 0;
137}
138
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200139static int ps2_xec_enable_interface(const struct device *dev)
Francisco Munoz278da902019-08-09 16:28:05 -0700140{
Tomasz Bursztykaaf6140c2020-05-28 20:44:16 +0200141 const struct ps2_xec_config *config = dev->config;
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +0200142 struct ps2_xec_data *data = dev->data;
Francisco Munoz278da902019-08-09 16:28:05 -0700143 PS2_Type *base = config->base;
144
145 MCHP_GIRQ_SRC(config->girq_id) = BIT(config->girq_bit);
146 base->CTRL = MCHP_PS2_CTRL_EN;
147
148 k_sem_give(&data->tx_lock);
149
150 return 0;
151}
Tomasz Bursztyka4dcfb552020-06-17 14:58:56 +0200152static void ps2_xec_isr(const struct device *dev)
Francisco Munoz278da902019-08-09 16:28:05 -0700153{
Tomasz Bursztykaaf6140c2020-05-28 20:44:16 +0200154 const struct ps2_xec_config *config = dev->config;
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +0200155 struct ps2_xec_data *data = dev->data;
Francisco Munoz278da902019-08-09 16:28:05 -0700156 PS2_Type *base = config->base;
Kumar Galaa1b77fd2020-05-27 11:26:57 -0500157 uint32_t status;
Francisco Munoz278da902019-08-09 16:28:05 -0700158
159 MCHP_GIRQ_SRC(config->girq_id) = BIT(config->girq_bit);
160
161 /* Read and clear status */
162 status = base->STATUS;
163
164 if (status & MCHP_PS2_STATUS_RXD_RDY) {
165 base->CTRL = 0x00;
166 if (data->callback_isr) {
167 data->callback_isr(dev, base->TRX_BUFF);
168 }
169 } else if (status &
170 (MCHP_PS2_STATUS_TX_TMOUT | MCHP_PS2_STATUS_TX_ST_TMOUT)) {
171 /* Clear sticky bits and go to read mode */
172 base->STATUS = MCHP_PS2_STATUS_RW1C_MASK;
Francisco Munoz51e82852020-04-28 15:00:48 -0700173 LOG_ERR("TX time out: %0x", status);
Francisco Munoz278da902019-08-09 16:28:05 -0700174 }
175
176 /* The control register reverts to RX automatically after
177 * transmiting the data
178 */
179 base->CTRL = MCHP_PS2_CTRL_EN;
180}
181
182static const struct ps2_driver_api ps2_xec_driver_api = {
183 .config = ps2_xec_configure,
184 .read = NULL,
185 .write = ps2_xec_write,
186 .disable_callback = ps2_xec_inhibit_interface,
187 .enable_callback = ps2_xec_enable_interface,
188};
189
190#ifdef CONFIG_PS2_XEC_0
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200191static int ps2_xec_init_0(const struct device *dev);
Francisco Munoz278da902019-08-09 16:28:05 -0700192
193static const struct ps2_xec_config ps2_xec_config_0 = {
Kumar Gala7a81cd92020-03-24 15:45:46 -0500194 .base = (PS2_Type *) DT_INST_REG_ADDR(0),
195 .girq_id = DT_INST_PROP(0, girq),
196 .girq_bit = DT_INST_PROP(0, girq_bit),
197 .isr_nvic = DT_INST_IRQN(0),
Francisco Munoz278da902019-08-09 16:28:05 -0700198};
199
200static struct ps2_xec_data ps2_xec_port_data_0;
201
Kumar Gala7a81cd92020-03-24 15:45:46 -0500202DEVICE_AND_API_INIT(ps2_xec_0, DT_INST_LABEL(0),
Francisco Munoz278da902019-08-09 16:28:05 -0700203 &ps2_xec_init_0,
204 &ps2_xec_port_data_0, &ps2_xec_config_0,
205 POST_KERNEL, CONFIG_PS2_INIT_PRIORITY,
206 &ps2_xec_driver_api);
207
208
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200209static int ps2_xec_init_0(const struct device *dev)
Francisco Munoz278da902019-08-09 16:28:05 -0700210{
211 ARG_UNUSED(dev);
212
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +0200213 struct ps2_xec_data *data = dev->data;
Francisco Munoz278da902019-08-09 16:28:05 -0700214
215 k_sem_init(&data->tx_lock, 0, 1);
216
Kumar Gala7a81cd92020-03-24 15:45:46 -0500217 IRQ_CONNECT(DT_INST_IRQN(0),
218 DT_INST_IRQ(0, priority),
Francisco Munoz278da902019-08-09 16:28:05 -0700219 ps2_xec_isr, DEVICE_GET(ps2_xec_0), 0);
220
Kumar Gala7a81cd92020-03-24 15:45:46 -0500221 irq_enable(DT_INST_IRQN(0));
Francisco Munoz278da902019-08-09 16:28:05 -0700222
223 return 0;
224}
225#endif /* CONFIG_PS2_XEC_0 */
226
227#ifdef CONFIG_PS2_XEC_1
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200228static int ps2_xec_init_1(const struct device *dev);
Francisco Munoz278da902019-08-09 16:28:05 -0700229
230static const struct ps2_xec_config ps2_xec_config_1 = {
Kumar Gala7a81cd92020-03-24 15:45:46 -0500231 .base = (PS2_Type *) DT_INST_REG_ADDR(1),
232 .girq_id = DT_INST_PROP(1, girq),
233 .girq_bit = DT_INST_PROP(1, girq_bit),
234 .isr_nvic = DT_INST_IRQN(1),
Francisco Munoz278da902019-08-09 16:28:05 -0700235
236};
237
238static struct ps2_xec_data ps2_xec_port_data_1;
239
Kumar Gala7a81cd92020-03-24 15:45:46 -0500240DEVICE_AND_API_INIT(ps2_xec_1, DT_INST_LABEL(1),
Francisco Munoz278da902019-08-09 16:28:05 -0700241 &ps2_xec_init_1,
242 &ps2_xec_port_data_1, &ps2_xec_config_1,
243 POST_KERNEL, CONFIG_PS2_INIT_PRIORITY,
244 &ps2_xec_driver_api);
245
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200246static int ps2_xec_init_1(const struct device *dev)
Francisco Munoz278da902019-08-09 16:28:05 -0700247{
248 ARG_UNUSED(dev);
249
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +0200250 struct ps2_xec_data *data = dev->data;
Francisco Munoz278da902019-08-09 16:28:05 -0700251
252 k_sem_init(&data->tx_lock, 0, 1);
253
Kumar Gala7a81cd92020-03-24 15:45:46 -0500254 IRQ_CONNECT(DT_INST_IRQN(1),
255 DT_INST_IRQ(1, priority),
Francisco Munoz278da902019-08-09 16:28:05 -0700256 ps2_xec_isr, DEVICE_GET(ps2_xec_1), 0);
257
Kumar Gala7a81cd92020-03-24 15:45:46 -0500258 irq_enable(DT_INST_IRQN(1));
Francisco Munoz278da902019-08-09 16:28:05 -0700259
260 return 0;
261}
262#endif /* CONFIG_PS2_XEC_1 */