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pigweed / third_party / github / zephyrproject-rtos / zephyr / 379c1dea388dc457a4cf656b3d957b5a2cd58ffa / . / dts / x86 / ia32.dtsi
blob: f44cc32204197c105fddd0b87ffff11327045882 [file] [log] [blame]
Tomasz Bursztyka9e1f1ac2018-03-05 13:37:46 +0100[diff] [blame]1/*
2 * Copyright (c) 2017 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
Savinay Dharmappaddf6a692017-09-07 23:37:36 +0530[diff] [blame]7#include "skeleton.dtsi"
Savinay Dharmappa54239d52017-11-08 21:30:37 +0530[diff] [blame]8#include <dt-bindings/interrupt-controller/intel-ioapic.h>
Savinay Dharmappab05ba6b2017-11-06 23:02:33 +0530[diff] [blame]9
Savinay Dharmappaddf6a692017-09-07 23:37:36 +0530[diff] [blame]10/ {
11 cpus {
12 #address-cells = <1>;
13 #size-cells = <0>;
14
15 cpu@0 {
16 device_type = "cpu";
Tomasz Bursztyka32638182021-02-11 13:16:01 +0100[diff] [blame]17 compatible = "intel,x86";
Tomasz Bursztyka16c4b652021-02-11 09:42:44 +0100[diff] [blame]18 d-cache-line-size = <64>;
Savinay Dharmappaddf6a692017-09-07 23:37:36 +0530[diff] [blame]19 reg = <0>;
20 };
21
22 };
23
Savinay Dharmappa54239d52017-11-08 21:30:37 +0530[diff] [blame]24 intc: ioapic@fec00000 {
25 compatible = "intel,ioapic";
Kumar Gala343e1602019-05-21 15:53:16 -0500[diff] [blame]26 reg = <0xfec00000 0x1000>;
Savinay Dharmappa54239d52017-11-08 21:30:37 +0530[diff] [blame]27 interrupt-controller;
Tomasz Bursztykae4aced52018-03-02 21:55:13 +0100[diff] [blame]28 #interrupt-cells = <3>;
Savinay Dharmappa54239d52017-11-08 21:30:37 +0530[diff] [blame]29 };
30
Kumar Gala17d5a472020-07-22 12:11:56 -0500[diff] [blame]31 dram0: memory@0 {
Savinay Dharmappaddf6a692017-09-07 23:37:36 +0530[diff] [blame]32 device_type = "memory";
Andrew Boieea10c982020-12-14 21:14:05 -0800[diff] [blame]33 reg = <DT_DRAM_BASE DT_DRAM_SIZE>;
Savinay Dharmappaddf6a692017-09-07 23:37:36 +0530[diff] [blame]34 };
35
Savinay Dharmappaddf6a692017-09-07 23:37:36 +0530[diff] [blame]36 soc {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "simple-bus";
40 ranges;
41
Kumar Galae4a96cc2018-09-17 16:32:03 -0500[diff] [blame]42 uart0: uart@3f8 {
Kumar Galae4014792017-10-10 12:15:28 -0500[diff] [blame]43 compatible = "ns16550";
Tomasz Bursztyka8bbb80e2018-03-05 14:37:29 +0100[diff] [blame]44 reg = <0x000003f8 0x100>;
Savinay Dharmappaddf6a692017-09-07 23:37:36 +0530[diff] [blame]45 label = "UART_0";
Tomasz Bursztyka61ef30d2018-03-05 14:38:50 +0100[diff] [blame]46 clock-frequency = <1843200>;
Zide Chenf32eeba2020-03-04 16:01:39 -0800[diff] [blame]47 interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
Savinay Dharmappa54239d52017-11-08 21:30:37 +0530[diff] [blame]48 interrupt-parent = <&intc>;
Savinay Dharmappaddf6a692017-09-07 23:37:36 +0530[diff] [blame]49
50 status = "disabled";
51 };
52
Kumar Galae4a96cc2018-09-17 16:32:03 -0500[diff] [blame]53 uart1: uart@2f8 {
Kumar Galae4014792017-10-10 12:15:28 -0500[diff] [blame]54 compatible = "ns16550";
Tomasz Bursztyka8bbb80e2018-03-05 14:37:29 +0100[diff] [blame]55 reg = <0x000002f8 0x100>;
Savinay Dharmappaddf6a692017-09-07 23:37:36 +0530[diff] [blame]56 label = "UART_1";
Tomasz Bursztyka61ef30d2018-03-05 14:38:50 +0100[diff] [blame]57 clock-frequency = <1843200>;
Zide Chenf32eeba2020-03-04 16:01:39 -0800[diff] [blame]58 interrupts = <3 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
Savinay Dharmappa54239d52017-11-08 21:30:37 +0530[diff] [blame]59 interrupt-parent = <&intc>;
Savinay Dharmappaddf6a692017-09-07 23:37:36 +0530[diff] [blame]60
61 status = "disabled";
62 };
Charles E. Youse30382092019-09-11 16:45:43 -0400[diff] [blame]63
64 hpet: hpet@fed00000 {
65 label = "HPET";
66 compatible = "intel,hpet";
67 reg = <0xfed00000 0x400>;
Zide Chenf32eeba2020-03-04 16:01:39 -0800[diff] [blame]68 interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
Charles E. Youse30382092019-09-11 16:45:43 -0400[diff] [blame]69 interrupt-parent = <&intc>;
70
71 status = "disabled";
72 };
Savinay Dharmappaddf6a692017-09-07 23:37:36 +0530[diff] [blame]73 };
74};