| Armando Visconti | 7b82e9f | 2018-06-14 09:27:46 +0200 | [diff] [blame^] | 1 | # Kconfig - STM32 I2S driver configuration options |
| 2 | # |
| 3 | # Copyright (c) 2018 STMicroelectronics |
| 4 | # |
| 5 | # SPDX-License-Identifier: Apache-2.0 |
| 6 | # |
| 7 | |
| 8 | menuconfig I2S_STM32 |
| 9 | bool "STM32 MCU I2S controller driver" |
| 10 | depends on I2S && SOC_SERIES_STM32F4X |
| 11 | select DMA |
| 12 | default n |
| 13 | help |
| 14 | Enable I2S support on the STM32 family of processors. |
| 15 | (Tested on the STM32F4 series) |
| 16 | |
| 17 | if I2S_STM32 |
| 18 | |
| 19 | config I2S_STM32_RX_BLOCK_COUNT |
| 20 | int "RX queue length" |
| 21 | default 4 |
| 22 | |
| 23 | config I2S_STM32_TX_BLOCK_COUNT |
| 24 | int "TX queue length" |
| 25 | default 4 |
| 26 | |
| 27 | config I2S_STM32_USE_PLLI2S_ENABLE |
| 28 | bool "Enable usage of PLL" |
| 29 | default n |
| 30 | help |
| 31 | Enable it if I2S clock should be provided by the PLLI2S. |
| 32 | If not enabled the clock will be provided by HSI/HSE. |
| 33 | |
| 34 | config I2S_STM32_PLLI2S_PLLM |
| 35 | int "Division factor for PLLI2S VCO input clock" |
| 36 | depends on I2S_STM32_USE_PLLI2S_ENABLE |
| 37 | default 8 |
| 38 | range 2 63 |
| 39 | help |
| 40 | Division factor for the audio PLL (PLLI2S) VCO input clock. |
| 41 | PLLM factor should be selected to ensure that the VCO |
| 42 | input frequency ranges from 1 to 2 MHz. It is recommended |
| 43 | to select a frequency of 2 MHz to limit PLL jitter. |
| 44 | Allowed values: 2-63 |
| 45 | |
| 46 | config I2S_STM32_PLLI2S_PLLN |
| 47 | int "Multiplier factor for PLLI2S VCO output clock" |
| 48 | depends on I2S_STM32_USE_PLLI2S_ENABLE |
| 49 | default 56 |
| 50 | range 50 432 |
| 51 | help |
| 52 | Multiply factor for the audio PLL (PLLI2S) VCO output clock. |
| 53 | PLLN factor should be selected to ensure that the VCO |
| 54 | output frequency ranges from 100 to 432 MHz. |
| 55 | Allowed values: 50-432 |
| 56 | |
| 57 | config I2S_STM32_PLLI2S_PLLR |
| 58 | int "Division factor for I2S clock" |
| 59 | depends on I2S_STM32_USE_PLLI2S_ENABLE |
| 60 | default 7 |
| 61 | range 2 7 |
| 62 | help |
| 63 | Division factor for the I2S clock. |
| 64 | PLLR factor should be selected to ensure that the I2S clock |
| 65 | frequency is less than or equal to 192MHz. |
| 66 | Allowed values: 2-7 |
| 67 | |
| 68 | config I2S_1 |
| 69 | bool "I2S port 1" |
| 70 | default n |
| 71 | help |
| 72 | Enable I2S controller port 1. |
| 73 | |
| 74 | config I2S_2 |
| 75 | bool "I2S port 2" |
| 76 | default n |
| 77 | help |
| 78 | Enable I2S controller port 2. |
| 79 | |
| 80 | config I2S_3 |
| 81 | bool "I2S port 3" |
| 82 | default n |
| 83 | help |
| 84 | Enable I2S controller port 3. |
| 85 | |
| 86 | config I2S_4 |
| 87 | bool "I2S port 4" |
| 88 | default n |
| 89 | help |
| 90 | Enable I2S controller port 4. |
| 91 | |
| 92 | config I2S_5 |
| 93 | bool "I2S port 5" |
| 94 | default n |
| 95 | help |
| 96 | Enable I2S controller port 5. |
| 97 | |
| 98 | endif # I2S_STM32 |
