Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | */ |
| 6 | |
| 7 | /** |
| 8 | * @file |
| 9 | * @brief Linker command/script file |
| 10 | * |
| 11 | * Linker script for the NXP i.MX8 platform |
| 12 | */ |
| 13 | |
| 14 | OUTPUT_ARCH(xtensa) |
| 15 | |
Gerard Marull-Paretas | d342e4c | 2022-05-09 13:20:58 +0200 | [diff] [blame] | 16 | #include <zephyr/devicetree.h> |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 17 | #include <xtensa/config/core-isa.h> |
Laurentiu Mihalcea | f29d6ed | 2023-09-22 10:23:06 +0300 | [diff] [blame] | 18 | #include <memory.h> |
Gerard Marull-Paretas | d342e4c | 2022-05-09 13:20:58 +0200 | [diff] [blame] | 19 | #include <zephyr/linker/sections.h> |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 20 | |
Gerard Marull-Paretas | d342e4c | 2022-05-09 13:20:58 +0200 | [diff] [blame] | 21 | #include <zephyr/linker/linker-defs.h> |
| 22 | #include <zephyr/linker/linker-tool.h> |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 23 | |
| 24 | PROVIDE(__memctl_default = 0x00000000); |
| 25 | PROVIDE(_MemErrorHandler = 0x00000000); |
| 26 | |
| 27 | #define RAMABLE_REGION sdram0 :sdram0_phdr |
| 28 | #define ROMABLE_REGION sdram0 :sdram0_phdr |
| 29 | |
| 30 | MEMORY |
| 31 | { |
| 32 | vector_reset_text : |
| 33 | org = XCHAL_RESET_VECTOR0_PADDR_IRAM, |
| 34 | len = MEM_RESET_TEXT_SIZE |
| 35 | vector_reset_lit : |
| 36 | org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE, |
| 37 | len = MEM_RESET_LIT_SIZE |
| 38 | vector_base_text : |
| 39 | org = XCHAL_VECBASE_RESET_PADDR_IRAM, |
| 40 | len = MEM_VECBASE_LIT_SIZE |
| 41 | vector_int2_lit : |
| 42 | org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, |
| 43 | len = MEM_VECT_LIT_SIZE |
| 44 | vector_int2_text : |
| 45 | org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM, |
| 46 | len = MEM_VECT_TEXT_SIZE |
| 47 | vector_int3_lit : |
| 48 | org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, |
| 49 | len = MEM_VECT_LIT_SIZE |
| 50 | vector_int3_text : |
| 51 | org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM, |
| 52 | len = MEM_VECT_TEXT_SIZE |
| 53 | vector_int4_lit : |
| 54 | org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, |
| 55 | len = MEM_VECT_LIT_SIZE |
| 56 | vector_int4_text : |
| 57 | org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM, |
| 58 | len = MEM_VECT_TEXT_SIZE |
| 59 | vector_int5_lit : |
| 60 | org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, |
| 61 | len = MEM_VECT_LIT_SIZE |
| 62 | vector_int5_text : |
| 63 | org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM, |
| 64 | len = MEM_VECT_TEXT_SIZE |
| 65 | vector_kernel_lit : |
| 66 | org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, |
| 67 | len = MEM_VECT_LIT_SIZE |
| 68 | vector_kernel_text : |
| 69 | org = XCHAL_KERNEL_VECTOR_PADDR_IRAM, |
| 70 | len = MEM_VECT_TEXT_SIZE |
| 71 | vector_user_lit : |
| 72 | org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, |
| 73 | len = MEM_VECT_LIT_SIZE |
| 74 | vector_user_text : |
| 75 | org = XCHAL_USER_VECTOR_PADDR_IRAM, |
| 76 | len = MEM_VECT_TEXT_SIZE |
| 77 | vector_double_lit : |
| 78 | org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, |
| 79 | len = MEM_VECT_LIT_SIZE |
| 80 | vector_double_text : |
| 81 | org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM, |
| 82 | len = MEM_VECT_TEXT_SIZE |
| 83 | iram_text_start : |
| 84 | org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE, |
| 85 | len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE) |
| 86 | sdram0 : |
| 87 | org = SDRAM0_BASE, |
| 88 | len = SDRAM0_SIZE |
| 89 | sdram1 : |
| 90 | org = SDRAM1_BASE + SOF_MAILBOX_SIZE, |
| 91 | len = SDRAM1_SIZE - SOF_MAILBOX_SIZE |
| 92 | #ifdef CONFIG_GEN_ISR_TABLES |
| 93 | IDT_LIST : |
| 94 | org = IDT_BASE, |
| 95 | len = IDT_SIZE |
| 96 | #endif |
| 97 | |
| 98 | static_uuid_entries_seg (!ari) : |
| 99 | org = UUID_ENTRY_ELF_BASE, |
| 100 | len = UUID_ENTRY_ELF_SIZE |
| 101 | static_log_entries_seg (!ari) : |
| 102 | org = LOG_ENTRY_ELF_BASE, |
| 103 | len = LOG_ENTRY_ELF_SIZE |
| 104 | fw_metadata_seg (!ari) : |
| 105 | org = EXT_MANIFEST_ELF_BASE, |
| 106 | len = EXT_MANIFEST_ELF_SIZE |
| 107 | } |
| 108 | |
| 109 | PHDRS |
| 110 | { |
| 111 | vector_reset_text_phdr PT_LOAD; |
| 112 | vector_reset_lit_phdr PT_LOAD; |
| 113 | vector_base_text_phdr PT_LOAD; |
| 114 | vector_base_lit_phdr PT_LOAD; |
| 115 | vector_int2_text_phdr PT_LOAD; |
| 116 | vector_int2_lit_phdr PT_LOAD; |
| 117 | vector_int3_text_phdr PT_LOAD; |
| 118 | vector_int3_lit_phdr PT_LOAD; |
| 119 | vector_int4_text_phdr PT_LOAD; |
| 120 | vector_int4_lit_phdr PT_LOAD; |
| 121 | vector_int5_text_phdr PT_LOAD; |
| 122 | vector_int5_lit_phdr PT_LOAD; |
| 123 | vector_kernel_text_phdr PT_LOAD; |
| 124 | vector_kernel_lit_phdr PT_LOAD; |
| 125 | vector_user_text_phdr PT_LOAD; |
| 126 | vector_user_lit_phdr PT_LOAD; |
| 127 | vector_double_text_phdr PT_LOAD; |
| 128 | vector_double_lit_phdr PT_LOAD; |
| 129 | iram_text_start_phdr PT_LOAD; |
| 130 | sdram0_phdr PT_LOAD; |
| 131 | sdram1_phdr PT_LOAD; |
| 132 | static_uuid_entries_phdr PT_NOTE; |
| 133 | static_log_entries_phdr PT_NOTE; |
| 134 | metadata_entries_phdr PT_NOTE; |
| 135 | } |
| 136 | |
| 137 | _rom_store_table = 0; |
| 138 | |
| 139 | PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR); |
| 140 | |
| 141 | ENTRY(CONFIG_KERNEL_ENTRY) |
| 142 | |
| 143 | /* Various memory-map dependent cache attribute settings: */ |
| 144 | _memmap_cacheattr_wb_base = 0x44024000; |
| 145 | _memmap_cacheattr_wt_base = 0x11021000; |
| 146 | _memmap_cacheattr_bp_base = 0x22022000; |
| 147 | _memmap_cacheattr_unused_mask = 0x00F00FFF; |
| 148 | _memmap_cacheattr_wb_trapnull = 0x4422422F; |
| 149 | _memmap_cacheattr_wba_trapnull = 0x4422422F; |
| 150 | _memmap_cacheattr_wbna_trapnull = 0x25222222; |
| 151 | _memmap_cacheattr_wt_trapnull = 0x1122122F; |
| 152 | _memmap_cacheattr_bp_trapnull = 0x2222222F; |
| 153 | _memmap_cacheattr_wb_strict = 0x44F24FFF; |
| 154 | _memmap_cacheattr_wt_strict = 0x11F21FFF; |
| 155 | _memmap_cacheattr_bp_strict = 0x22F22FFF; |
| 156 | _memmap_cacheattr_wb_allvalid = 0x44224222; |
| 157 | _memmap_cacheattr_wt_allvalid = 0x11221222; |
| 158 | _memmap_cacheattr_bp_allvalid = 0x22222222; |
| 159 | /* |
| 160 | * Every 512M in 4GB space has dedicate cache attribute. |
| 161 | * 1: write through |
| 162 | * 2: cache bypass |
| 163 | * 4: write back |
| 164 | * F: invalid access |
| 165 | */ |
| 166 | _memmap_cacheattr_imx8_wt_allvalid = 0x22212222; |
| 167 | PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_imx8_wt_allvalid); |
| 168 | |
| 169 | _EXT_MAN_ALIGN_ = 16; |
| 170 | EXTERN(ext_man_fw_ver) |
| 171 | |
| 172 | SECTIONS |
| 173 | { |
| 174 | |
Gerard Marull-Paretas | d342e4c | 2022-05-09 13:20:58 +0200 | [diff] [blame] | 175 | #include <zephyr/linker/rel-sections.ld> |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 176 | .ResetVector.text : ALIGN(4) |
| 177 | { |
| 178 | _ResetVector_text_start = ABSOLUTE(.); |
| 179 | KEEP (*(.ResetVector.text)) |
| 180 | _ResetVector_text_end = ABSOLUTE(.); |
| 181 | } >vector_reset_text :vector_reset_text_phdr |
| 182 | |
| 183 | .ResetVector.literal : ALIGN(4) |
| 184 | { |
| 185 | _ResetVector_literal_start = ABSOLUTE(.); |
| 186 | *(.ResetVector.literal) |
| 187 | _ResetVector_literal_end = ABSOLUTE(.); |
| 188 | } >vector_reset_lit :vector_reset_lit_phdr |
| 189 | |
| 190 | .WindowVectors.text : ALIGN(4) |
| 191 | { |
| 192 | _WindowVectors_text_start = ABSOLUTE(.); |
| 193 | KEEP (*(.WindowVectors.text)) |
| 194 | _WindowVectors_text_end = ABSOLUTE(.); |
| 195 | } >vector_base_text :vector_base_text_phdr |
| 196 | |
| 197 | .Level2InterruptVector.literal : ALIGN(4) |
| 198 | { |
| 199 | _Level2InterruptVector_literal_start = ABSOLUTE(.); |
| 200 | *(.Level2InterruptVector.literal) |
| 201 | _Level2InterruptVector_literal_end = ABSOLUTE(.); |
| 202 | } >vector_int2_lit :vector_int2_lit_phdr |
| 203 | |
| 204 | .Level2InterruptVector.text : ALIGN(4) |
| 205 | { |
| 206 | _Level2InterruptVector_text_start = ABSOLUTE(.); |
| 207 | KEEP (*(.Level2InterruptVector.text)) |
| 208 | _Level2InterruptVector_text_end = ABSOLUTE(.); |
| 209 | } >vector_int2_text :vector_int2_text_phdr |
| 210 | |
| 211 | .Level3InterruptVector.literal : ALIGN(4) |
| 212 | { |
| 213 | _Level3InterruptVector_literal_start = ABSOLUTE(.); |
| 214 | *(.Level3InterruptVector.literal) |
| 215 | _Level3InterruptVector_literal_end = ABSOLUTE(.); |
| 216 | } >vector_int3_lit :vector_int3_lit_phdr |
| 217 | |
| 218 | .Level3InterruptVector.text : ALIGN(4) |
| 219 | { |
| 220 | _Level3InterruptVector_text_start = ABSOLUTE(.); |
| 221 | KEEP (*(.Level3InterruptVector.text)) |
| 222 | _Level3InterruptVector_text_end = ABSOLUTE(.); |
| 223 | } >vector_int3_text :vector_int3_text_phdr |
| 224 | |
| 225 | .DebugExceptionVector.literal : ALIGN(4) |
| 226 | { |
| 227 | _DebugExceptionVector_literal_start = ABSOLUTE(.); |
| 228 | *(.DebugExceptionVector.literal) |
| 229 | _DebugExceptionVector_literal_end = ABSOLUTE(.); |
| 230 | } >vector_int4_lit :vector_int4_lit_phdr |
| 231 | |
| 232 | .DebugExceptionVector.text : ALIGN(4) |
| 233 | { |
| 234 | _DebugExceptionVector_text_start = ABSOLUTE(.); |
| 235 | KEEP (*(.DebugExceptionVector.text)) |
| 236 | _DebugExceptionVector_text_end = ABSOLUTE(.); |
| 237 | } >vector_int4_text :vector_int4_text_phdr |
| 238 | |
| 239 | .NMIExceptionVector.literal : ALIGN(4) |
| 240 | { |
| 241 | _NMIExceptionVector_literal_start = ABSOLUTE(.); |
| 242 | *(.NMIExceptionVector.literal) |
| 243 | _NMIExceptionVector_literal_end = ABSOLUTE(.); |
| 244 | } >vector_int5_lit :vector_int5_lit_phdr |
| 245 | |
| 246 | .NMIExceptionVector.text : ALIGN(4) |
| 247 | { |
| 248 | _NMIExceptionVector_text_start = ABSOLUTE(.); |
| 249 | KEEP (*(.NMIExceptionVector.text)) |
| 250 | _NMIExceptionVector_text_end = ABSOLUTE(.); |
| 251 | } >vector_int5_text :vector_int5_text_phdr |
| 252 | |
| 253 | .KernelExceptionVector.literal : ALIGN(4) |
| 254 | { |
| 255 | _KernelExceptionVector_literal_start = ABSOLUTE(.); |
| 256 | *(.KernelExceptionVector.literal) |
| 257 | _KernelExceptionVector_literal_end = ABSOLUTE(.); |
| 258 | } >vector_kernel_lit :vector_kernel_lit_phdr |
| 259 | |
| 260 | .KernelExceptionVector.text : ALIGN(4) |
| 261 | { |
| 262 | _KernelExceptionVector_text_start = ABSOLUTE(.); |
| 263 | KEEP (*(.KernelExceptionVector.text)) |
| 264 | _KernelExceptionVector_text_end = ABSOLUTE(.); |
| 265 | } >vector_kernel_text :vector_kernel_text_phdr |
| 266 | |
| 267 | .UserExceptionVector.literal : ALIGN(4) |
| 268 | { |
| 269 | _UserExceptionVector_literal_start = ABSOLUTE(.); |
| 270 | *(.UserExceptionVector.literal) |
| 271 | _UserExceptionVector_literal_end = ABSOLUTE(.); |
| 272 | } >vector_user_lit :vector_user_lit_phdr |
| 273 | |
| 274 | .UserExceptionVector.text : ALIGN(4) |
| 275 | { |
| 276 | _UserExceptionVector_text_start = ABSOLUTE(.); |
| 277 | KEEP (*(.UserExceptionVector.text)) |
| 278 | _UserExceptionVector_text_end = ABSOLUTE(.); |
| 279 | } >vector_user_text :vector_user_text_phdr |
| 280 | |
| 281 | .DoubleExceptionVector.literal : ALIGN(4) |
| 282 | { |
| 283 | _DoubleExceptionVector_literal_start = ABSOLUTE(.); |
| 284 | *(.DoubleExceptionVector.literal) |
| 285 | _DoubleExceptionVector_literal_end = ABSOLUTE(.); |
| 286 | } >vector_double_lit :vector_double_lit_phdr |
| 287 | |
| 288 | .DoubleExceptionVector.text : ALIGN(4) |
| 289 | { |
| 290 | _DoubleExceptionVector_text_start = ABSOLUTE(.); |
| 291 | KEEP (*(.DoubleExceptionVector.text)) |
| 292 | _DoubleExceptionVector_text_end = ABSOLUTE(.); |
| 293 | } >vector_double_text :vector_double_text_phdr |
| 294 | |
| 295 | .iram.text : ALIGN(4) |
| 296 | { |
| 297 | _stext = .; |
| 298 | _iram_text_start = ABSOLUTE(.); |
| 299 | *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) |
| 300 | _iram_text_end = ABSOLUTE(.); |
| 301 | } >iram_text_start :iram_text_start_phdr |
| 302 | |
| 303 | .rodata : ALIGN(4) |
| 304 | { |
Flavio Ceolin | e3aac24 | 2022-09-13 11:11:01 -0700 | [diff] [blame] | 305 | __rodata_region_start = ABSOLUTE(.); |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 306 | *(.rodata) |
| 307 | *(.rodata.*) |
| 308 | *(.gnu.linkonce.r.*) |
| 309 | *(.rodata1) |
| 310 | __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); |
| 311 | KEEP (*(.xt_except_table)) |
| 312 | KEEP (*(.gcc_except_table .gcc_except_table.*)) |
| 313 | *(.gnu.linkonce.e.*) |
| 314 | *(.gnu.version_r) |
| 315 | KEEP (*(.eh_frame)) |
| 316 | KEEP (*crtbegin.o(.ctors)) |
| 317 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) |
| 318 | KEEP (*(SORT(.ctors.*))) |
| 319 | KEEP (*(.ctors)) |
| 320 | KEEP (*crtbegin.o(.dtors)) |
| 321 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) |
| 322 | KEEP (*(SORT(.dtors.*))) |
| 323 | KEEP (*(.dtors)) |
| 324 | __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); |
| 325 | *(.xt_except_desc) |
| 326 | *(.gnu.linkonce.h.*) |
| 327 | __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); |
| 328 | *(.xt_except_desc_end) |
| 329 | *(.dynamic) |
| 330 | *(.gnu.version_d) |
| 331 | . = ALIGN(4); |
| 332 | _bss_table_start = ABSOLUTE(.); |
| 333 | LONG(_bss_start) |
| 334 | LONG(_bss_end) |
| 335 | _bss_table_end = ABSOLUTE(.); |
Flavio Ceolin | e3aac24 | 2022-09-13 11:11:01 -0700 | [diff] [blame] | 336 | __rodata_region_end = ABSOLUTE(.); |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 337 | } >sdram0 :sdram0_phdr |
| 338 | |
| 339 | .module_init : ALIGN(4) |
| 340 | { |
| 341 | _module_init_start = ABSOLUTE(.); |
Daniel Baluta | c3c026e | 2022-04-21 10:05:24 +0300 | [diff] [blame] | 342 | *(*.initcall) |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 343 | _module_init_end = ABSOLUTE(.); |
| 344 | } >sdram0 :sdram0_phdr |
| 345 | |
| 346 | .text : ALIGN(4) |
| 347 | { |
| 348 | _stext = .; |
Iuliana Prodan | 24f2d2e | 2023-11-11 01:09:46 +0200 | [diff] [blame] | 349 | __text_region_start = ABSOLUTE(.); |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 350 | KEEP (*(.ResetVector.text)) |
| 351 | *(.ResetVector.literal) |
| 352 | *(.entry.text) |
| 353 | *(.init.literal) |
| 354 | KEEP(*(.init)) |
| 355 | *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) |
| 356 | *(.fini.literal) |
| 357 | KEEP(*(.fini)) |
| 358 | *(.gnu.version) |
Iuliana Prodan | 24f2d2e | 2023-11-11 01:09:46 +0200 | [diff] [blame] | 359 | __text_region_end = ABSOLUTE(.); |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 360 | _etext = .; |
| 361 | } >sdram0 :sdram0_phdr |
| 362 | |
Gerard Marull-Paretas | d342e4c | 2022-05-09 13:20:58 +0200 | [diff] [blame] | 363 | #include <zephyr/linker/common-rom.ld> |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 364 | |
| 365 | .fw_ready : ALIGN(4) |
| 366 | { |
| 367 | KEEP(*(".fw_ready")); |
| 368 | KEEP (*(.fw_ready_metadata)) |
| 369 | } >sdram0 :sdram0_phdr |
| 370 | |
| 371 | .noinit : ALIGN(4) |
| 372 | { |
| 373 | *(.noinit) |
| 374 | *(.noinit.*) |
| 375 | } >sdram0 :sdram0_phdr |
| 376 | |
| 377 | .data : ALIGN(4) |
| 378 | { |
Ederson de Souza | d7f4613 | 2022-10-19 09:16:30 -0700 | [diff] [blame] | 379 | __data_start = ABSOLUTE(.); |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 380 | *(.data) |
| 381 | *(.data.*) |
| 382 | *(.gnu.linkonce.d.*) |
| 383 | KEEP(*(.gnu.linkonce.d.*personality*)) |
| 384 | *(.data1) |
| 385 | *(.sdata) |
| 386 | *(.sdata.*) |
| 387 | *(.gnu.linkonce.s.*) |
| 388 | *(.sdata2) |
| 389 | *(.sdata2.*) |
| 390 | *(.gnu.linkonce.s2.*) |
| 391 | KEEP(*(.jcr)) |
Marc Herbert | 5d4e08b | 2021-12-17 04:28:34 +0000 | [diff] [blame] | 392 | _trace_ctx_start = ABSOLUTE(.); |
| 393 | *(.trace_ctx) |
| 394 | _trace_ctx_end = ABSOLUTE(.); |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 395 | . = ALIGN(4); |
| 396 | *(.gna_model) |
Ederson de Souza | d7f4613 | 2022-10-19 09:16:30 -0700 | [diff] [blame] | 397 | __data_end = ABSOLUTE(.); |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 398 | . = ALIGN(4096); |
| 399 | } >sdram0 :sdram0_phdr |
| 400 | |
| 401 | .lit4 : ALIGN(4) |
| 402 | { |
| 403 | _lit4_start = ABSOLUTE(.); |
| 404 | *(*.lit4) |
| 405 | *(.lit4.*) |
| 406 | *(.gnu.linkonce.lit4.*) |
| 407 | _lit4_end = ABSOLUTE(.); |
| 408 | } >sdram0 :sdram0_phdr |
| 409 | |
Gerard Marull-Paretas | d342e4c | 2022-05-09 13:20:58 +0200 | [diff] [blame] | 410 | #include <zephyr/linker/common-ram.ld> |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 411 | |
| 412 | .bss (NOLOAD) : ALIGN(8) |
| 413 | { |
| 414 | . = ALIGN (8); |
| 415 | _bss_start = ABSOLUTE(.); |
| 416 | *(.dynsbss) |
| 417 | *(.sbss) |
| 418 | *(.sbss.*) |
| 419 | *(.gnu.linkonce.sb.*) |
| 420 | *(.scommon) |
| 421 | *(.sbss2) |
| 422 | *(.sbss2.*) |
| 423 | *(.gnu.linkonce.sb2.*) |
| 424 | *(.dynbss) |
| 425 | *(.bss) |
| 426 | *(.bss.*) |
| 427 | *(.gnu.linkonce.b.*) |
| 428 | *(COMMON) |
| 429 | . = ALIGN (8); |
| 430 | _bss_end = ABSOLUTE(.); |
| 431 | } >sdram0 :sdram0_phdr |
| 432 | |
| 433 | .heap_mem (NOLOAD) : ALIGN(8) |
| 434 | { |
| 435 | . = ALIGN (8); |
| 436 | _heap_mem_start = ABSOLUTE(.); |
| 437 | *(*.heap_mem) |
| 438 | _heap_mem_end = ABSOLUTE(.); |
| 439 | } >sdram1 :sdram1_phdr |
| 440 | |
| 441 | /* stack */ |
| 442 | _end = ALIGN (8); |
| 443 | PROVIDE(end = ALIGN (8)); |
| 444 | |
| 445 | __stack = SDRAM1_BASE + SDRAM1_SIZE; |
| 446 | .comment 0 : { *(.comment) } |
| 447 | .debug 0 : { *(.debug) } |
| 448 | .line 0 : { *(.line) } |
| 449 | .debug_srcinfo 0 : { *(.debug_srcinfo) } |
| 450 | .debug_sfnames 0 : { *(.debug_sfnames) } |
| 451 | .debug_aranges 0 : { *(.debug_aranges) } |
| 452 | .debug_pubnames 0 : { *(.debug_pubnames) } |
| 453 | .debug_info 0 : { *(.debug_info) } |
| 454 | .debug_abbrev 0 : { *(.debug_abbrev) } |
| 455 | .debug_line 0 : { *(.debug_line) } |
| 456 | .debug_frame 0 : { *(.debug_frame) } |
| 457 | .debug_str 0 : { *(.debug_str) } |
| 458 | .debug_loc 0 : { *(.debug_loc) } |
| 459 | .debug_macinfo 0 : { *(.debug_macinfo) } |
| 460 | .debug_weaknames 0 : { *(.debug_weaknames) } |
| 461 | .debug_funcnames 0 : { *(.debug_funcnames) } |
| 462 | .debug_typenames 0 : { *(.debug_typenames) } |
| 463 | .debug_varnames 0 : { *(.debug_varnames) } |
| 464 | .debug_ranges 0 : { *(.debug_ranges) } |
| 465 | .xtensa.info 0 : { *(.xtensa.info) } |
| 466 | .xt.insn 0 : |
| 467 | { |
| 468 | KEEP (*(.xt.insn)) |
| 469 | KEEP (*(.gnu.linkonce.x.*)) |
| 470 | } |
| 471 | .xt.prop 0 : |
| 472 | { |
| 473 | KEEP (*(.xt.prop)) |
| 474 | KEEP (*(.xt.prop.*)) |
| 475 | KEEP (*(.gnu.linkonce.prop.*)) |
| 476 | } |
| 477 | .xt.lit 0 : |
| 478 | { |
| 479 | KEEP (*(.xt.lit)) |
| 480 | KEEP (*(.xt.lit.*)) |
| 481 | KEEP (*(.gnu.linkonce.p.*)) |
| 482 | } |
| 483 | .xt.profile_range 0 : |
| 484 | { |
| 485 | KEEP (*(.xt.profile_range)) |
| 486 | KEEP (*(.gnu.linkonce.profile_range.*)) |
| 487 | } |
| 488 | .xt.profile_ranges 0 : |
| 489 | { |
| 490 | KEEP (*(.xt.profile_ranges)) |
| 491 | KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) |
| 492 | } |
| 493 | .xt.profile_files 0 : |
| 494 | { |
| 495 | KEEP (*(.xt.profile_files)) |
| 496 | KEEP (*(.gnu.linkonce.xt.profile_files.*)) |
| 497 | } |
| 498 | #ifdef CONFIG_GEN_ISR_TABLES |
Gerard Marull-Paretas | d342e4c | 2022-05-09 13:20:58 +0200 | [diff] [blame] | 499 | #include <zephyr/linker/intlist.ld> |
Iuliana Prodan | 9dcd562 | 2021-05-18 23:35:51 +0300 | [diff] [blame] | 500 | #endif |
| 501 | |
| 502 | .static_uuid_entries (COPY) : ALIGN(1024) |
| 503 | { |
| 504 | *(*.static_uuids) |
| 505 | } > static_uuid_entries_seg :static_uuid_entries_phdr |
| 506 | |
| 507 | .static_log_entries (COPY) : ALIGN(1024) |
| 508 | { |
| 509 | *(*.static_log*) |
| 510 | } > static_log_entries_seg :static_log_entries_phdr |
| 511 | |
| 512 | .fw_metadata (COPY) : ALIGN(1024) |
| 513 | { |
| 514 | KEEP (*(.fw_metadata)) |
| 515 | . = ALIGN(_EXT_MAN_ALIGN_); |
| 516 | } >fw_metadata_seg :metadata_entries_phdr |
| 517 | } |