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Vinayak Chettimadaa100ada2016-11-22 17:03:32 +01001/*
Wojciech Bober923560a2017-02-13 16:31:53 +01002 * Copyright (c) 2016-2017 Nordic Semiconductor ASA
Andy Ross03f007e2018-10-15 09:04:21 -07003 * Copyright (c) 2018 Intel Corporation
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +01004 *
David B. Kinderac74d8b2017-01-18 17:01:01 -08005 * SPDX-License-Identifier: Apache-2.0
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +01006 */
7
8#include <soc.h>
9#include <clock_control.h>
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +010010#include <drivers/clock_control/nrf5_clock_control.h>
Andy Ross03f007e2018-10-15 09:04:21 -070011#include <system_timer.h>
Ramesh Thomas89ffd442017-02-05 19:37:19 -080012#include <sys_clock.h>
Andy Ross03f007e2018-10-15 09:04:21 -070013#include <nrf_rtc.h>
14#include <spinlock.h>
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +010015
Andy Ross03f007e2018-10-15 09:04:21 -070016#define RTC NRF_RTC1
Andy Rossab488272018-09-20 13:56:45 -070017
Andy Ross03f007e2018-10-15 09:04:21 -070018#define COUNTER_MAX 0x00ffffff
19#define CYC_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
20 / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
21#define MAX_TICKS ((COUNTER_MAX - CYC_PER_TICK) / CYC_PER_TICK)
Wojciech Bober923560a2017-02-13 16:31:53 +010022
Andy Ross03f007e2018-10-15 09:04:21 -070023#define MIN_DELAY 32
Alberto Escolar Piedras785faea2018-06-15 15:17:49 +020024
Andy Ross03f007e2018-10-15 09:04:21 -070025static struct k_spinlock lock;
Youvedeep Singha4063f52017-05-08 11:29:37 +053026
Andy Ross03f007e2018-10-15 09:04:21 -070027static u32_t last_count;
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +010028
Andy Ross03f007e2018-10-15 09:04:21 -070029static u32_t counter_sub(u32_t a, u32_t b)
Carles Cufica0951d2016-12-13 11:55:22 +010030{
Andy Ross03f007e2018-10-15 09:04:21 -070031 return (a - b) & COUNTER_MAX;
Wojciech Bober923560a2017-02-13 16:31:53 +010032}
33
Andy Ross03f007e2018-10-15 09:04:21 -070034static void set_comparator(u32_t cyc)
Ramakrishna Pallala5f443092018-06-25 11:32:54 +053035{
Andy Ross03f007e2018-10-15 09:04:21 -070036 nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
Ramakrishna Pallala5f443092018-06-25 11:32:54 +053037}
38
Andy Ross03f007e2018-10-15 09:04:21 -070039static u32_t counter(void)
Youvedeep Singha4063f52017-05-08 11:29:37 +053040{
Andy Ross03f007e2018-10-15 09:04:21 -070041 return nrf_rtc_counter_get(RTC);
Youvedeep Singha4063f52017-05-08 11:29:37 +053042}
43
Andy Ross03f007e2018-10-15 09:04:21 -070044/* Note: this function has public linkage, and MUST have this
45 * particular name. The platform architecture itself doesn't care,
46 * but there is a test (tests/kernel/arm_irq_vector_table) that needs
47 * to find it to it can set it in a custom vector table. Should
48 * probably better abstract that at some point (e.g. query and reset
49 * it by pointer at runtime, maybe?) so we don't have this leaky
50 * symbol.
Wojciech Bober923560a2017-02-13 16:31:53 +010051 */
Ioannis Glaropoulos8d2b22c2018-04-04 17:45:46 +020052void rtc1_nrf5_isr(void *arg)
Wojciech Bober923560a2017-02-13 16:31:53 +010053{
Youvedeep Singha4063f52017-05-08 11:29:37 +053054 ARG_UNUSED(arg);
Andy Ross03f007e2018-10-15 09:04:21 -070055 RTC->EVENTS_COMPARE[0] = 0;
Youvedeep Singha4063f52017-05-08 11:29:37 +053056
Andy Ross03f007e2018-10-15 09:04:21 -070057 k_spinlock_key_t key = k_spin_lock(&lock);
58 u32_t t = counter();
59 u32_t dticks = counter_sub(t, last_count) / CYC_PER_TICK;
Youvedeep Singh91063a32017-08-31 20:22:18 +053060
Andy Ross03f007e2018-10-15 09:04:21 -070061 last_count += dticks * CYC_PER_TICK;
62
63 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
64 u32_t next = last_count + CYC_PER_TICK;
65
Peter A. Bigotd2f50782018-11-29 12:56:38 -060066 if (counter_sub(next, t) < MIN_DELAY) {
Andy Ross03f007e2018-10-15 09:04:21 -070067 next += CYC_PER_TICK;
Ramakrishna Pallala5f443092018-06-25 11:32:54 +053068 }
Andy Ross03f007e2018-10-15 09:04:21 -070069 set_comparator(next);
Ramakrishna Pallala5f443092018-06-25 11:32:54 +053070 }
Ramakrishna Pallala5f443092018-06-25 11:32:54 +053071
Andy Ross03f007e2018-10-15 09:04:21 -070072 k_spin_unlock(&lock, key);
73 z_clock_announce(dticks);
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +010074}
75
Andy Ross1a1a9532018-09-21 09:33:36 -070076int z_clock_driver_init(struct device *device)
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +010077{
78 struct device *clock;
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +010079
80 ARG_UNUSED(device);
81
82 clock = device_get_binding(CONFIG_CLOCK_CONTROL_NRF5_K32SRC_DRV_NAME);
83 if (!clock) {
84 return -1;
85 }
86
87 clock_control_on(clock, (void *)CLOCK_CONTROL_NRF5_K32SRC);
88
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +010089 /* TODO: replace with counter driver to access RTC */
Andy Ross03f007e2018-10-15 09:04:21 -070090 nrf_rtc_prescaler_set(RTC, 0);
91 nrf_rtc_cc_set(RTC, 0, CYC_PER_TICK);
92 nrf_rtc_event_enable(RTC, RTC_EVTENSET_COMPARE0_Msk);
93 nrf_rtc_int_enable(RTC, RTC_INTENSET_COMPARE0_Msk);
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +010094
Ricardo Salveti51036ca2017-02-28 11:41:18 -030095 /* Clear the event flag and possible pending interrupt */
Andy Ross03f007e2018-10-15 09:04:21 -070096 nrf_rtc_event_clear(RTC, NRF_RTC_EVENT_COMPARE_0);
Ricardo Salveti51036ca2017-02-28 11:41:18 -030097 NVIC_ClearPendingIRQ(NRF5_IRQ_RTC1_IRQn);
98
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +010099 IRQ_CONNECT(NRF5_IRQ_RTC1_IRQn, 1, rtc1_nrf5_isr, 0, 0);
100 irq_enable(NRF5_IRQ_RTC1_IRQn);
101
Andy Ross03f007e2018-10-15 09:04:21 -0700102 nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
103 nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);
104
105 if (!IS_ENABLED(TICKLESS_KERNEL)) {
106 set_comparator(counter() + CYC_PER_TICK);
107 }
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +0100108
Anas Nashif247a4502016-11-27 22:35:52 -0500109 return 0;
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +0100110}
111
Andy Ross03f007e2018-10-15 09:04:21 -0700112void z_clock_set_timeout(s32_t ticks, bool idle)
113{
114 ARG_UNUSED(idle);
115
116#ifdef CONFIG_TICKLESS_KERNEL
117 ticks = (ticks == K_FOREVER) ? MAX_TICKS : ticks;
118 ticks = max(min(ticks - 1, (s32_t)MAX_TICKS), 0);
119
120 k_spinlock_key_t key = k_spin_lock(&lock);
121 u32_t cyc, t = counter();
122
123 /* Round up to next tick boundary */
124 cyc = ticks * CYC_PER_TICK + counter_sub(t, last_count);
125 cyc += (CYC_PER_TICK - 1);
126 cyc = (cyc / CYC_PER_TICK) * CYC_PER_TICK;
127 cyc += last_count;
128
Peter A. Bigotd2f50782018-11-29 12:56:38 -0600129 if (counter_sub(cyc, t) < MIN_DELAY) {
Andy Ross03f007e2018-10-15 09:04:21 -0700130 cyc += CYC_PER_TICK;
131 }
132
133 set_comparator(cyc);
134 k_spin_unlock(&lock, key);
135#endif
136}
137
138u32_t z_clock_elapsed(void)
139{
140 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
141 return 0;
142 }
143
144 k_spinlock_key_t key = k_spin_lock(&lock);
145 u32_t ret = counter_sub(counter(), last_count) / CYC_PER_TICK;
146
147 k_spin_unlock(&lock, key);
148 return ret;
149}
150
Kumar Galacc334c72017-04-21 10:55:34 -0500151u32_t _timer_cycle_get_32(void)
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +0100152{
Andy Ross03f007e2018-10-15 09:04:21 -0700153 k_spinlock_key_t key = k_spin_lock(&lock);
154 u32_t ret = counter_sub(counter(), last_count) + last_count;
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +0100155
Andy Ross03f007e2018-10-15 09:04:21 -0700156 k_spin_unlock(&lock, key);
157 return ret;
Vinayak Chettimadaa100ada2016-11-22 17:03:32 +0100158}