cyliang tw | 5879810 | 2023-03-03 17:27:55 +0800 | [diff] [blame] | 1 | # Copyright (c) Nuvoton Technology Corp. All rights reserved. |
| 2 | # SPDX-License-Identifier: Apache-2.0 |
| 3 | |
| 4 | description: | |
| 5 | Pin controller is responsible for controlling pin function |
| 6 | selection and pin properties. For example, for example you can |
| 7 | use this node to set UART0 RX as pin PB12 to fulfill SYS_GPB_MFP3_PB12MFP_UART0_RXD. |
| 8 | |
| 9 | The node has the 'pinctrl' node label set in your SoC's devicetree, |
| 10 | so you can modify it like this: |
| 11 | |
| 12 | &pinctrl { |
| 13 | /* your modifications go here */ |
| 14 | }; |
| 15 | |
| 16 | All device pin configurations should be placed in child nodes of the |
| 17 | 'pinctrl' node, as shown in this example: |
| 18 | |
| 19 | &pinctrl { |
| 20 | /* configuration for the uart0 "default" state */ |
| 21 | uart0_default: uart0_default { |
| 22 | /* configure PB13 as UART0 TX and PB12 as UART0 RX */ |
cyliang tw | 51d57f6 | 2023-06-27 16:06:02 +0800 | [diff] [blame] | 23 | group0 { |
| 24 | pinmux = <PB12MFP_UART0_RXD>, <PB13MFP_UART0_TXD>; |
| 25 | }; |
cyliang tw | 5879810 | 2023-03-03 17:27:55 +0800 | [diff] [blame] | 26 | }; |
| 27 | }; |
| 28 | |
| 29 | |
| 30 | To link pin configurations with a device, use a pinctrl-N property for some |
| 31 | number N, like this example you could place in your board's DTS file: |
| 32 | |
| 33 | #include "board-pinctrl.dtsi" |
| 34 | |
| 35 | &uart0 { |
| 36 | pinctrl-0 = <&uart0_default>; |
| 37 | pinctrl-names = "default"; |
| 38 | }; |
| 39 | |
| 40 | compatible: "nuvoton,numaker-pinctrl" |
| 41 | |
cyliang tw | 51d57f6 | 2023-06-27 16:06:02 +0800 | [diff] [blame] | 42 | include: base.yaml |
| 43 | |
| 44 | properties: |
| 45 | reg: |
| 46 | required: true |
cyliang tw | 5879810 | 2023-03-03 17:27:55 +0800 | [diff] [blame] | 47 | |
| 48 | child-binding: |
cyliang tw | 51d57f6 | 2023-06-27 16:06:02 +0800 | [diff] [blame] | 49 | description: NuMaker pin controller pin group |
| 50 | child-binding: |
| 51 | description: | |
| 52 | Each child node defines the configuration for a particular state. |
| 53 | include: |
| 54 | - name: pincfg-node.yaml |
| 55 | property-allowlist: |
| 56 | - drive-open-drain |
| 57 | - input-schmitt-enable |
| 58 | properties: |
| 59 | pinmux: |
| 60 | required: true |
| 61 | type: array |
| 62 | description: | |
| 63 | An array of pins sharing the same group properties. The pins should |
| 64 | be defined using pre-defined macros or, alternatively, using NVT_PINMUX |
| 65 | macros depending on the pinmux model used by the SoC series. |
| 66 | drive-strength: |
| 67 | type: string |
| 68 | default: "low" |
| 69 | enum: |
| 70 | - "low" |
| 71 | - "fast" |
| 72 | description: | |
| 73 | Set the driving strength of a pin. Hardware default configuration is low and |
| 74 | it's enough to drive most components, like as LED, CAN transceiver and so on. |
| 75 | slew-rate: |
| 76 | type: string |
| 77 | default: "low" |
| 78 | enum: |
| 79 | - "low" |
| 80 | - "high" |
| 81 | - "fast" |
| 82 | description: | |
| 83 | Set the speed of a pin. This setting effectively limits the |
| 84 | slew rate of the output signal. Hardware default configuration is low. |
| 85 | Fast slew rate could support fast speed pins, like as SPI CLK up to 50MHz. |
cyliang tw | de58070 | 2024-05-08 09:35:08 +0800 | [diff] [blame^] | 86 | digital-path-disable: |
| 87 | type: boolean |
| 88 | description: disable digital path on a pin. |