Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016 Linaro Limited. |
| 3 | * Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: Apache-2.0 |
| 6 | */ |
| 7 | |
| 8 | /** |
| 9 | * @brief Common part of DMA drivers for stm32. |
| 10 | * @note Functions named with stm32_dma_* are SoCs related functions |
| 11 | * implemented in dma_stm32_v*.c |
| 12 | */ |
| 13 | |
Francois Ramu | 3553d4f | 2020-01-27 10:52:56 +0100 | [diff] [blame] | 14 | #include "dma_stm32.h" |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 15 | |
Gerard Marull-Paretas | fb60aab | 2022-05-06 10:25:46 +0200 | [diff] [blame] | 16 | #include <zephyr/init.h> |
| 17 | #include <zephyr/drivers/clock_control.h> |
| 18 | #include <zephyr/drivers/dma/dma_stm32.h> |
Erwin Rol | 3866b39 | 2020-08-28 15:04:00 +0200 | [diff] [blame] | 19 | |
Gerard Marull-Paretas | fb60aab | 2022-05-06 10:25:46 +0200 | [diff] [blame] | 20 | #include <zephyr/logging/log.h> |
Francois Ramu | 3553d4f | 2020-01-27 10:52:56 +0100 | [diff] [blame] | 21 | LOG_MODULE_REGISTER(dma_stm32, CONFIG_DMA_LOG_LEVEL); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 22 | |
Erwan Gouriou | a214f41 | 2021-01-07 20:37:04 +0100 | [diff] [blame] | 23 | #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v1) |
| 24 | #define DT_DRV_COMPAT st_stm32_dma_v1 |
| 25 | #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v2) |
| 26 | #define DT_DRV_COMPAT st_stm32_dma_v2 |
Francois Ramu | dcefbd6 | 2021-04-28 14:37:47 +0200 | [diff] [blame] | 27 | #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v2bis) |
| 28 | #define DT_DRV_COMPAT st_stm32_dma_v2bis |
Erwan Gouriou | a214f41 | 2021-01-07 20:37:04 +0100 | [diff] [blame] | 29 | #endif |
| 30 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 31 | #if DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) |
| 32 | #if DT_INST_IRQ_HAS_IDX(0, 7) |
| 33 | #define DMA_STM32_0_STREAM_COUNT 8 |
| 34 | #elif DT_INST_IRQ_HAS_IDX(0, 6) |
| 35 | #define DMA_STM32_0_STREAM_COUNT 7 |
| 36 | #elif DT_INST_IRQ_HAS_IDX(0, 5) |
| 37 | #define DMA_STM32_0_STREAM_COUNT 6 |
| 38 | #else |
| 39 | #define DMA_STM32_0_STREAM_COUNT 5 |
| 40 | #endif |
| 41 | #endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */ |
| 42 | |
| 43 | #if DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay) |
| 44 | #if DT_INST_IRQ_HAS_IDX(1, 7) |
| 45 | #define DMA_STM32_1_STREAM_COUNT 8 |
| 46 | #elif DT_INST_IRQ_HAS_IDX(1, 6) |
| 47 | #define DMA_STM32_1_STREAM_COUNT 7 |
| 48 | #elif DT_INST_IRQ_HAS_IDX(1, 5) |
| 49 | #define DMA_STM32_1_STREAM_COUNT 6 |
| 50 | #else |
| 51 | #define DMA_STM32_1_STREAM_COUNT 5 |
| 52 | #endif |
| 53 | #endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay) */ |
| 54 | |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 55 | static uint32_t table_m_size[] = { |
Francois Ramu | 1b0503d | 2020-04-01 16:36:51 +0200 | [diff] [blame] | 56 | LL_DMA_MDATAALIGN_BYTE, |
| 57 | LL_DMA_MDATAALIGN_HALFWORD, |
| 58 | LL_DMA_MDATAALIGN_WORD, |
| 59 | }; |
| 60 | |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 61 | static uint32_t table_p_size[] = { |
Francois Ramu | 1b0503d | 2020-04-01 16:36:51 +0200 | [diff] [blame] | 62 | LL_DMA_PDATAALIGN_BYTE, |
| 63 | LL_DMA_PDATAALIGN_HALFWORD, |
| 64 | LL_DMA_PDATAALIGN_WORD, |
| 65 | }; |
| 66 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 67 | static void dma_stm32_dump_stream_irq(const struct device *dev, uint32_t id) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 68 | { |
Tomasz Bursztyka | af6140c | 2020-05-28 20:44:16 +0200 | [diff] [blame] | 69 | const struct dma_stm32_config *config = dev->config; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 70 | DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); |
| 71 | |
| 72 | stm32_dma_dump_stream_irq(dma, id); |
| 73 | } |
| 74 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 75 | static void dma_stm32_clear_stream_irq(const struct device *dev, uint32_t id) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 76 | { |
Tomasz Bursztyka | af6140c | 2020-05-28 20:44:16 +0200 | [diff] [blame] | 77 | const struct dma_stm32_config *config = dev->config; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 78 | DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); |
| 79 | |
Erwin Rol | 3866b39 | 2020-08-28 15:04:00 +0200 | [diff] [blame] | 80 | dma_stm32_clear_tc(dma, id); |
| 81 | dma_stm32_clear_ht(dma, id); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 82 | stm32_dma_clear_stream_irq(dma, id); |
| 83 | } |
| 84 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 85 | static void dma_stm32_irq_handler(const struct device *dev, uint32_t id) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 86 | { |
Tomasz Bursztyka | af6140c | 2020-05-28 20:44:16 +0200 | [diff] [blame] | 87 | const struct dma_stm32_config *config = dev->config; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 88 | DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); |
| 89 | struct dma_stm32_stream *stream; |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 90 | uint32_t callback_arg; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 91 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 92 | __ASSERT_NO_MSG(id < config->max_streams); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 93 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 94 | stream = &config->streams[id]; |
Francois Ramu | 41df1c9 | 2020-04-23 11:38:06 +0200 | [diff] [blame] | 95 | |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 96 | #ifdef CONFIG_DMAMUX_STM32 |
| 97 | callback_arg = stream->mux_channel; |
| 98 | #else |
Francois Ramu | 005968a | 2022-04-29 15:19:53 +0200 | [diff] [blame] | 99 | callback_arg = id + STM32_DMA_STREAM_OFFSET; |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 100 | #endif /* CONFIG_DMAMUX_STM32 */ |
Francois Ramu | 41df1c9 | 2020-04-23 11:38:06 +0200 | [diff] [blame] | 101 | if (!IS_ENABLED(CONFIG_DMAMUX_STM32)) { |
| 102 | stream->busy = false; |
| 103 | } |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 104 | |
Francois Ramu | 005968a | 2022-04-29 15:19:53 +0200 | [diff] [blame] | 105 | /* the dma stream id is in range from STM32_DMA_STREAM_OFFSET..<dma-requests> */ |
Erwan Gouriou | 96c92ed | 2021-02-03 16:57:10 +0100 | [diff] [blame] | 106 | if (stm32_dma_is_ht_irq_active(dma, id)) { |
Erwan Gouriou | d43200e | 2020-12-18 10:49:23 +0100 | [diff] [blame] | 107 | /* Let HAL DMA handle flags on its own */ |
| 108 | if (!stream->hal_override) { |
| 109 | dma_stm32_clear_ht(dma, id); |
| 110 | } |
| 111 | stream->dma_callback(dev, stream->user_data, callback_arg, 0); |
Erwan Gouriou | 96c92ed | 2021-02-03 16:57:10 +0100 | [diff] [blame] | 112 | } else if (stm32_dma_is_tc_irq_active(dma, id)) { |
Francois Ramu | 41df1c9 | 2020-04-23 11:38:06 +0200 | [diff] [blame] | 113 | #ifdef CONFIG_DMAMUX_STM32 |
| 114 | stream->busy = false; |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 115 | #endif |
Erwan Gouriou | d43200e | 2020-12-18 10:49:23 +0100 | [diff] [blame] | 116 | /* Let HAL DMA handle flags on its own */ |
| 117 | if (!stream->hal_override) { |
| 118 | dma_stm32_clear_tc(dma, id); |
| 119 | } |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 120 | stream->dma_callback(dev, stream->user_data, callback_arg, 0); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 121 | } else if (stm32_dma_is_unexpected_irq_happened(dma, id)) { |
| 122 | LOG_ERR("Unexpected irq happened."); |
Tomasz Bursztyka | 1580768 | 2020-07-29 09:02:03 +0200 | [diff] [blame] | 123 | stream->dma_callback(dev, stream->user_data, |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 124 | callback_arg, -EIO); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 125 | } else { |
| 126 | LOG_ERR("Transfer Error."); |
| 127 | dma_stm32_dump_stream_irq(dev, id); |
| 128 | dma_stm32_clear_stream_irq(dev, id); |
Tomasz Bursztyka | 1580768 | 2020-07-29 09:02:03 +0200 | [diff] [blame] | 129 | stream->dma_callback(dev, stream->user_data, |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 130 | callback_arg, -EIO); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 131 | } |
| 132 | } |
| 133 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 134 | #ifdef CONFIG_DMA_STM32_SHARED_IRQS |
| 135 | |
Thomas Stranger | 5a475d7 | 2021-03-17 16:05:42 +0100 | [diff] [blame] | 136 | #define HANDLE_IRQS(index) \ |
| 137 | static const struct device *dev_##index = DEVICE_DT_INST_GET(index); \ |
| 138 | const struct dma_stm32_config *cfg_##index = dev_##index->config; \ |
| 139 | DMA_TypeDef *dma_##index = (DMA_TypeDef *)(cfg_##index->base); \ |
| 140 | \ |
| 141 | for (id = 0; id < cfg_##index->max_streams; ++id) { \ |
| 142 | if (stm32_dma_is_irq_active(dma_##index, id)) { \ |
| 143 | dma_stm32_irq_handler(dev_##index, id); \ |
| 144 | } \ |
| 145 | } |
| 146 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 147 | static void dma_stm32_shared_irq_handler(const struct device *dev) |
| 148 | { |
Thomas Stranger | 5a475d7 | 2021-03-17 16:05:42 +0100 | [diff] [blame] | 149 | ARG_UNUSED(dev); |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 150 | uint32_t id = 0; |
| 151 | |
Thomas Stranger | 5a475d7 | 2021-03-17 16:05:42 +0100 | [diff] [blame] | 152 | DT_INST_FOREACH_STATUS_OKAY(HANDLE_IRQS) |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | #endif /* CONFIG_DMA_STM32_SHARED_IRQS */ |
| 156 | |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 157 | static int dma_stm32_get_priority(uint8_t priority, uint32_t *ll_priority) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 158 | { |
| 159 | switch (priority) { |
| 160 | case 0x0: |
| 161 | *ll_priority = LL_DMA_PRIORITY_LOW; |
| 162 | break; |
| 163 | case 0x1: |
| 164 | *ll_priority = LL_DMA_PRIORITY_MEDIUM; |
| 165 | break; |
| 166 | case 0x2: |
| 167 | *ll_priority = LL_DMA_PRIORITY_HIGH; |
| 168 | break; |
| 169 | case 0x3: |
| 170 | *ll_priority = LL_DMA_PRIORITY_VERYHIGH; |
| 171 | break; |
| 172 | default: |
| 173 | LOG_ERR("Priority error. %d", priority); |
| 174 | return -EINVAL; |
| 175 | } |
| 176 | |
| 177 | return 0; |
| 178 | } |
| 179 | |
| 180 | static int dma_stm32_get_direction(enum dma_channel_direction direction, |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 181 | uint32_t *ll_direction) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 182 | { |
| 183 | switch (direction) { |
| 184 | case MEMORY_TO_MEMORY: |
| 185 | *ll_direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY; |
| 186 | break; |
| 187 | case MEMORY_TO_PERIPHERAL: |
| 188 | *ll_direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH; |
| 189 | break; |
| 190 | case PERIPHERAL_TO_MEMORY: |
| 191 | *ll_direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; |
| 192 | break; |
| 193 | default: |
| 194 | LOG_ERR("Direction error. %d", direction); |
| 195 | return -EINVAL; |
| 196 | } |
| 197 | |
| 198 | return 0; |
| 199 | } |
| 200 | |
| 201 | static int dma_stm32_get_memory_increment(enum dma_addr_adj increment, |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 202 | uint32_t *ll_increment) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 203 | { |
| 204 | switch (increment) { |
| 205 | case DMA_ADDR_ADJ_INCREMENT: |
| 206 | *ll_increment = LL_DMA_MEMORY_INCREMENT; |
| 207 | break; |
| 208 | case DMA_ADDR_ADJ_NO_CHANGE: |
| 209 | *ll_increment = LL_DMA_MEMORY_NOINCREMENT; |
| 210 | break; |
| 211 | case DMA_ADDR_ADJ_DECREMENT: |
| 212 | return -ENOTSUP; |
| 213 | default: |
| 214 | LOG_ERR("Memory increment error. %d", increment); |
| 215 | return -EINVAL; |
| 216 | } |
| 217 | |
| 218 | return 0; |
| 219 | } |
| 220 | |
| 221 | static int dma_stm32_get_periph_increment(enum dma_addr_adj increment, |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 222 | uint32_t *ll_increment) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 223 | { |
| 224 | switch (increment) { |
| 225 | case DMA_ADDR_ADJ_INCREMENT: |
| 226 | *ll_increment = LL_DMA_PERIPH_INCREMENT; |
| 227 | break; |
| 228 | case DMA_ADDR_ADJ_NO_CHANGE: |
| 229 | *ll_increment = LL_DMA_PERIPH_NOINCREMENT; |
| 230 | break; |
| 231 | case DMA_ADDR_ADJ_DECREMENT: |
| 232 | return -ENOTSUP; |
| 233 | default: |
| 234 | LOG_ERR("Periph increment error. %d", increment); |
| 235 | return -EINVAL; |
| 236 | } |
| 237 | |
| 238 | return 0; |
| 239 | } |
| 240 | |
Erwin Rol | 7b8b219 | 2020-08-28 14:04:19 +0200 | [diff] [blame] | 241 | static int dma_stm32_disable_stream(DMA_TypeDef *dma, uint32_t id) |
| 242 | { |
| 243 | int count = 0; |
| 244 | |
| 245 | for (;;) { |
| 246 | if (stm32_dma_disable_stream(dma, id) == 0) { |
| 247 | return 0; |
| 248 | } |
| 249 | /* After trying for 5 seconds, give up */ |
| 250 | if (count++ > (5 * 1000)) { |
| 251 | return -EBUSY; |
| 252 | } |
| 253 | k_sleep(K_MSEC(1)); |
| 254 | } |
| 255 | |
| 256 | return 0; |
| 257 | } |
| 258 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 259 | DMA_STM32_EXPORT_API int dma_stm32_configure(const struct device *dev, |
| 260 | uint32_t id, |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 261 | struct dma_config *config) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 262 | { |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 263 | const struct dma_stm32_config *dev_config = dev->config; |
| 264 | struct dma_stm32_stream *stream = |
Francois Ramu | 005968a | 2022-04-29 15:19:53 +0200 | [diff] [blame] | 265 | &dev_config->streams[id - STM32_DMA_STREAM_OFFSET]; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 266 | DMA_TypeDef *dma = (DMA_TypeDef *)dev_config->base; |
Abel Radenac | e8fa6b3 | 2021-03-29 18:14:29 +0200 | [diff] [blame] | 267 | LL_DMA_InitTypeDef DMA_InitStruct; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 268 | int ret; |
| 269 | |
Abel Radenac | e8fa6b3 | 2021-03-29 18:14:29 +0200 | [diff] [blame] | 270 | LL_DMA_StructInit(&DMA_InitStruct); |
| 271 | |
Erwan Gouriou | de4ba27 | 2020-04-13 21:38:58 +0200 | [diff] [blame] | 272 | /* give channel from index 0 */ |
Francois Ramu | 005968a | 2022-04-29 15:19:53 +0200 | [diff] [blame] | 273 | id = id - STM32_DMA_STREAM_OFFSET; |
Erwan Gouriou | de4ba27 | 2020-04-13 21:38:58 +0200 | [diff] [blame] | 274 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 275 | if (id >= dev_config->max_streams) { |
Erwan Gouriou | de4ba27 | 2020-04-13 21:38:58 +0200 | [diff] [blame] | 276 | LOG_ERR("cannot configure the dma stream %d.", id); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 277 | return -EINVAL; |
| 278 | } |
| 279 | |
| 280 | if (stream->busy) { |
Erwan Gouriou | de4ba27 | 2020-04-13 21:38:58 +0200 | [diff] [blame] | 281 | LOG_ERR("dma stream %d is busy.", id); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 282 | return -EBUSY; |
| 283 | } |
| 284 | |
Erwin Rol | 7b8b219 | 2020-08-28 14:04:19 +0200 | [diff] [blame] | 285 | if (dma_stm32_disable_stream(dma, id) != 0) { |
| 286 | LOG_ERR("could not disable dma stream %d.", id); |
| 287 | return -EBUSY; |
| 288 | } |
| 289 | |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 290 | dma_stm32_clear_stream_irq(dev, id); |
| 291 | |
Francois Ramu | 41efe86 | 2022-04-28 14:45:15 +0200 | [diff] [blame] | 292 | /* Check potential DMA override (if id parameters and stream are valid) */ |
| 293 | if (config->linked_channel == STM32_DMA_HAL_OVERRIDE) { |
| 294 | /* DMA channel is overridden by HAL DMA |
| 295 | * Retain that the channel is busy and proceed to the minimal |
| 296 | * configuration to properly route the IRQ |
| 297 | */ |
| 298 | stream->busy = true; |
| 299 | stream->hal_override = true; |
| 300 | stream->dma_callback = config->dma_callback; |
| 301 | stream->user_data = config->user_data; |
| 302 | return 0; |
| 303 | } |
| 304 | |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 305 | if (config->head_block->block_size > DMA_STM32_MAX_DATA_ITEMS) { |
| 306 | LOG_ERR("Data size too big: %d\n", |
| 307 | config->head_block->block_size); |
| 308 | return -EINVAL; |
| 309 | } |
| 310 | |
Francois Ramu | 82799d2 | 2020-01-24 12:04:01 +0100 | [diff] [blame] | 311 | #ifdef CONFIG_DMA_STM32_V1 |
Abe Kohandel | 8c7f63c | 2020-04-07 23:37:05 -0700 | [diff] [blame] | 312 | if ((config->channel_direction == MEMORY_TO_MEMORY) && |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 313 | (!dev_config->support_m2m)) { |
| 314 | LOG_ERR("Memcopy not supported for device %s", |
Tomasz Bursztyka | 97326c0 | 2020-03-09 12:49:07 +0100 | [diff] [blame] | 315 | dev->name); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 316 | return -ENOTSUP; |
| 317 | } |
Francois Ramu | 82799d2 | 2020-01-24 12:04:01 +0100 | [diff] [blame] | 318 | #endif /* CONFIG_DMA_STM32_V1 */ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 319 | |
Francois Ramu | e7f222a | 2020-11-18 11:10:52 +0100 | [diff] [blame] | 320 | /* support only the same data width for source and dest */ |
| 321 | if ((config->dest_data_size != config->source_data_size)) { |
| 322 | LOG_ERR("source and dest data size differ."); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 323 | return -EINVAL; |
| 324 | } |
| 325 | |
Francois Ramu | e7f222a | 2020-11-18 11:10:52 +0100 | [diff] [blame] | 326 | if (config->source_data_size != 4U && |
| 327 | config->source_data_size != 2U && |
| 328 | config->source_data_size != 1U) { |
| 329 | LOG_ERR("source and dest unit size error, %d", |
| 330 | config->source_data_size); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 331 | return -EINVAL; |
| 332 | } |
| 333 | |
| 334 | /* |
| 335 | * STM32's circular mode will auto reset both source address |
| 336 | * counter and destination address counter. |
| 337 | */ |
| 338 | if (config->head_block->source_reload_en != |
| 339 | config->head_block->dest_reload_en) { |
| 340 | LOG_ERR("source_reload_en and dest_reload_en must " |
| 341 | "be the same."); |
| 342 | return -EINVAL; |
| 343 | } |
| 344 | |
| 345 | stream->busy = true; |
| 346 | stream->dma_callback = config->dma_callback; |
| 347 | stream->direction = config->channel_direction; |
Tomasz Bursztyka | 1580768 | 2020-07-29 09:02:03 +0200 | [diff] [blame] | 348 | stream->user_data = config->user_data; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 349 | stream->src_size = config->source_data_size; |
| 350 | stream->dst_size = config->dest_data_size; |
| 351 | |
Francois Ramu | a9f277a | 2020-03-12 15:43:46 +0100 | [diff] [blame] | 352 | /* check dest or source memory address, warn if 0 */ |
| 353 | if ((config->head_block->source_address == 0)) { |
| 354 | LOG_WRN("source_buffer address is null."); |
| 355 | } |
| 356 | |
| 357 | if ((config->head_block->dest_address == 0)) { |
| 358 | LOG_WRN("dest_buffer address is null."); |
| 359 | } |
| 360 | |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 361 | if (stream->direction == MEMORY_TO_PERIPHERAL) { |
| 362 | DMA_InitStruct.MemoryOrM2MDstAddress = |
| 363 | config->head_block->source_address; |
| 364 | DMA_InitStruct.PeriphOrM2MSrcAddress = |
| 365 | config->head_block->dest_address; |
| 366 | } else { |
| 367 | DMA_InitStruct.PeriphOrM2MSrcAddress = |
| 368 | config->head_block->source_address; |
| 369 | DMA_InitStruct.MemoryOrM2MDstAddress = |
| 370 | config->head_block->dest_address; |
| 371 | } |
| 372 | |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 373 | uint16_t memory_addr_adj = 0, periph_addr_adj = 0; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 374 | |
| 375 | ret = dma_stm32_get_priority(config->channel_priority, |
| 376 | &DMA_InitStruct.Priority); |
| 377 | if (ret < 0) { |
| 378 | return ret; |
| 379 | } |
| 380 | |
| 381 | ret = dma_stm32_get_direction(config->channel_direction, |
| 382 | &DMA_InitStruct.Direction); |
| 383 | if (ret < 0) { |
| 384 | return ret; |
| 385 | } |
| 386 | |
| 387 | switch (config->channel_direction) { |
| 388 | case MEMORY_TO_MEMORY: |
| 389 | case PERIPHERAL_TO_MEMORY: |
| 390 | memory_addr_adj = config->head_block->dest_addr_adj; |
| 391 | periph_addr_adj = config->head_block->source_addr_adj; |
| 392 | break; |
| 393 | case MEMORY_TO_PERIPHERAL: |
| 394 | memory_addr_adj = config->head_block->source_addr_adj; |
| 395 | periph_addr_adj = config->head_block->dest_addr_adj; |
| 396 | break; |
| 397 | /* Direction has been asserted in dma_stm32_get_direction. */ |
Francois Ramu | e135bba | 2020-03-31 14:55:49 +0200 | [diff] [blame] | 398 | default: |
| 399 | LOG_ERR("Channel direction error (%d).", |
| 400 | config->channel_direction); |
| 401 | return -EINVAL; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 402 | } |
| 403 | |
| 404 | ret = dma_stm32_get_memory_increment(memory_addr_adj, |
| 405 | &DMA_InitStruct.MemoryOrM2MDstIncMode); |
| 406 | if (ret < 0) { |
| 407 | return ret; |
| 408 | } |
| 409 | ret = dma_stm32_get_periph_increment(periph_addr_adj, |
| 410 | &DMA_InitStruct.PeriphOrM2MSrcIncMode); |
| 411 | if (ret < 0) { |
| 412 | return ret; |
| 413 | } |
| 414 | |
| 415 | if (config->head_block->source_reload_en) { |
| 416 | DMA_InitStruct.Mode = LL_DMA_MODE_CIRCULAR; |
| 417 | } else { |
| 418 | DMA_InitStruct.Mode = LL_DMA_MODE_NORMAL; |
| 419 | } |
| 420 | |
Francois Ramu | 325edf2 | 2021-07-19 12:22:19 +0200 | [diff] [blame] | 421 | stream->source_periph = (stream->direction == PERIPHERAL_TO_MEMORY); |
Francois Ramu | e7f222a | 2020-11-18 11:10:52 +0100 | [diff] [blame] | 422 | |
| 423 | /* set the data width, when source_data_size equals dest_data_size */ |
| 424 | int index = find_lsb_set(config->source_data_size) - 1; |
| 425 | DMA_InitStruct.PeriphOrM2MSrcDataSize = table_p_size[index]; |
| 426 | index = find_lsb_set(config->dest_data_size) - 1; |
| 427 | DMA_InitStruct.MemoryOrM2MDstDataSize = table_m_size[index]; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 428 | |
| 429 | #if defined(CONFIG_DMA_STM32_V1) |
| 430 | DMA_InitStruct.MemBurst = stm32_dma_get_mburst(config, |
| 431 | stream->source_periph); |
| 432 | DMA_InitStruct.PeriphBurst = stm32_dma_get_pburst(config, |
| 433 | stream->source_periph); |
| 434 | |
Shlomi Vaknin | 95143fc | 2021-03-30 18:22:30 +0300 | [diff] [blame] | 435 | #if !defined(CONFIG_SOC_SERIES_STM32H7X) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 436 | if (config->channel_direction != MEMORY_TO_MEMORY) { |
| 437 | if (config->dma_slot >= 8) { |
| 438 | LOG_ERR("dma slot error."); |
| 439 | return -EINVAL; |
| 440 | } |
| 441 | } else { |
| 442 | if (config->dma_slot >= 8) { |
| 443 | LOG_ERR("dma slot is too big, using 0 as default."); |
| 444 | config->dma_slot = 0; |
| 445 | } |
| 446 | } |
Shlomi Vaknin | 95143fc | 2021-03-30 18:22:30 +0300 | [diff] [blame] | 447 | |
Erwin Rol | b05dc44 | 2020-08-22 14:28:52 +0200 | [diff] [blame] | 448 | DMA_InitStruct.Channel = dma_stm32_slot_to_channel(config->dma_slot); |
Shlomi Vaknin | 95143fc | 2021-03-30 18:22:30 +0300 | [diff] [blame] | 449 | #endif |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 450 | |
Song Qiang | 65c1d76 | 2019-12-04 21:01:40 +0800 | [diff] [blame] | 451 | DMA_InitStruct.FIFOThreshold = stm32_dma_get_fifo_threshold( |
| 452 | config->head_block->fifo_mode_control); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 453 | |
| 454 | if (stm32_dma_check_fifo_mburst(&DMA_InitStruct)) { |
| 455 | DMA_InitStruct.FIFOMode = LL_DMA_FIFOMODE_ENABLE; |
| 456 | } else { |
| 457 | DMA_InitStruct.FIFOMode = LL_DMA_FIFOMODE_DISABLE; |
| 458 | } |
| 459 | #endif |
| 460 | if (stream->source_periph) { |
| 461 | DMA_InitStruct.NbData = config->head_block->block_size / |
| 462 | config->source_data_size; |
| 463 | } else { |
| 464 | DMA_InitStruct.NbData = config->head_block->block_size / |
| 465 | config->dest_data_size; |
| 466 | } |
Francois Ramu | 41df1c9 | 2020-04-23 11:38:06 +0200 | [diff] [blame] | 467 | |
Francois Ramu | 6312b73 | 2021-06-21 10:55:29 +0200 | [diff] [blame] | 468 | #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v2) || DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dmamux) |
Francois Ramu | 7ed83de | 2020-03-10 12:52:34 +0100 | [diff] [blame] | 469 | /* |
Francois Ramu | 41df1c9 | 2020-04-23 11:38:06 +0200 | [diff] [blame] | 470 | * the with dma V2 and dma mux, |
Francois Ramu | 7ed83de | 2020-03-10 12:52:34 +0100 | [diff] [blame] | 471 | * the request ID is stored in the dma_slot |
| 472 | */ |
| 473 | DMA_InitStruct.PeriphRequest = config->dma_slot; |
| 474 | #endif |
Erwin Rol | b05dc44 | 2020-08-22 14:28:52 +0200 | [diff] [blame] | 475 | LL_DMA_Init(dma, dma_stm32_id_to_stream(id), &DMA_InitStruct); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 476 | |
Erwin Rol | b05dc44 | 2020-08-22 14:28:52 +0200 | [diff] [blame] | 477 | LL_DMA_EnableIT_TC(dma, dma_stm32_id_to_stream(id)); |
Shlomi Vaknin | e9efa8a | 2021-03-29 19:23:13 +0300 | [diff] [blame] | 478 | |
| 479 | /* Enable Half-Transfer irq if circular mode is enabled */ |
| 480 | if (config->head_block->source_reload_en) { |
| 481 | LL_DMA_EnableIT_HT(dma, dma_stm32_id_to_stream(id)); |
| 482 | } |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 483 | |
| 484 | #if defined(CONFIG_DMA_STM32_V1) |
| 485 | if (DMA_InitStruct.FIFOMode == LL_DMA_FIFOMODE_ENABLE) { |
Erwin Rol | b05dc44 | 2020-08-22 14:28:52 +0200 | [diff] [blame] | 486 | LL_DMA_EnableFifoMode(dma, dma_stm32_id_to_stream(id)); |
| 487 | LL_DMA_EnableIT_FE(dma, dma_stm32_id_to_stream(id)); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 488 | } else { |
Erwin Rol | b05dc44 | 2020-08-22 14:28:52 +0200 | [diff] [blame] | 489 | LL_DMA_DisableFifoMode(dma, dma_stm32_id_to_stream(id)); |
| 490 | LL_DMA_DisableIT_FE(dma, dma_stm32_id_to_stream(id)); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 491 | } |
| 492 | #endif |
| 493 | return ret; |
| 494 | } |
| 495 | |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 496 | DMA_STM32_EXPORT_API int dma_stm32_reload(const struct device *dev, uint32_t id, |
| 497 | uint32_t src, uint32_t dst, |
| 498 | size_t size) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 499 | { |
Tomasz Bursztyka | af6140c | 2020-05-28 20:44:16 +0200 | [diff] [blame] | 500 | const struct dma_stm32_config *config = dev->config; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 501 | DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); |
Erwin Rol | 2da881a | 2020-08-28 13:15:48 +0200 | [diff] [blame] | 502 | struct dma_stm32_stream *stream; |
Erwan Gouriou | de4ba27 | 2020-04-13 21:38:58 +0200 | [diff] [blame] | 503 | |
| 504 | /* give channel from index 0 */ |
Francois Ramu | 005968a | 2022-04-29 15:19:53 +0200 | [diff] [blame] | 505 | id = id - STM32_DMA_STREAM_OFFSET; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 506 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 507 | if (id >= config->max_streams) { |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 508 | return -EINVAL; |
| 509 | } |
| 510 | |
Erwin Rol | 2da881a | 2020-08-28 13:15:48 +0200 | [diff] [blame] | 511 | stream = &config->streams[id]; |
Francois Ramu | bea0a95 | 2020-04-23 10:53:30 +0200 | [diff] [blame] | 512 | |
Erwin Rol | 7b8b219 | 2020-08-28 14:04:19 +0200 | [diff] [blame] | 513 | if (dma_stm32_disable_stream(dma, id) != 0) { |
| 514 | return -EBUSY; |
| 515 | } |
| 516 | |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 517 | switch (stream->direction) { |
| 518 | case MEMORY_TO_PERIPHERAL: |
Erwin Rol | b05dc44 | 2020-08-22 14:28:52 +0200 | [diff] [blame] | 519 | LL_DMA_SetMemoryAddress(dma, dma_stm32_id_to_stream(id), src); |
| 520 | LL_DMA_SetPeriphAddress(dma, dma_stm32_id_to_stream(id), dst); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 521 | break; |
| 522 | case MEMORY_TO_MEMORY: |
| 523 | case PERIPHERAL_TO_MEMORY: |
Erwin Rol | b05dc44 | 2020-08-22 14:28:52 +0200 | [diff] [blame] | 524 | LL_DMA_SetPeriphAddress(dma, dma_stm32_id_to_stream(id), src); |
| 525 | LL_DMA_SetMemoryAddress(dma, dma_stm32_id_to_stream(id), dst); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 526 | break; |
| 527 | default: |
| 528 | return -EINVAL; |
| 529 | } |
| 530 | |
| 531 | if (stream->source_periph) { |
Erwin Rol | b05dc44 | 2020-08-22 14:28:52 +0200 | [diff] [blame] | 532 | LL_DMA_SetDataLength(dma, dma_stm32_id_to_stream(id), |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 533 | size / stream->src_size); |
| 534 | } else { |
Erwin Rol | b05dc44 | 2020-08-22 14:28:52 +0200 | [diff] [blame] | 535 | LL_DMA_SetDataLength(dma, dma_stm32_id_to_stream(id), |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 536 | size / stream->dst_size); |
| 537 | } |
Francois Ramu | bea0a95 | 2020-04-23 10:53:30 +0200 | [diff] [blame] | 538 | |
| 539 | stm32_dma_enable_stream(dma, id); |
| 540 | |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 541 | return 0; |
| 542 | } |
| 543 | |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 544 | DMA_STM32_EXPORT_API int dma_stm32_start(const struct device *dev, uint32_t id) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 545 | { |
Tomasz Bursztyka | af6140c | 2020-05-28 20:44:16 +0200 | [diff] [blame] | 546 | const struct dma_stm32_config *config = dev->config; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 547 | DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 548 | |
Erwan Gouriou | de4ba27 | 2020-04-13 21:38:58 +0200 | [diff] [blame] | 549 | /* give channel from index 0 */ |
Francois Ramu | 005968a | 2022-04-29 15:19:53 +0200 | [diff] [blame] | 550 | id = id - STM32_DMA_STREAM_OFFSET; |
Erwan Gouriou | de4ba27 | 2020-04-13 21:38:58 +0200 | [diff] [blame] | 551 | |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 552 | /* Only M2P or M2M mode can be started manually. */ |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 553 | if (id >= config->max_streams) { |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 554 | return -EINVAL; |
| 555 | } |
| 556 | |
| 557 | dma_stm32_clear_stream_irq(dev, id); |
| 558 | |
| 559 | stm32_dma_enable_stream(dma, id); |
| 560 | |
| 561 | return 0; |
| 562 | } |
| 563 | |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 564 | DMA_STM32_EXPORT_API int dma_stm32_stop(const struct device *dev, uint32_t id) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 565 | { |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 566 | const struct dma_stm32_config *config = dev->config; |
Francois Ramu | 005968a | 2022-04-29 15:19:53 +0200 | [diff] [blame] | 567 | struct dma_stm32_stream *stream = &config->streams[id - STM32_DMA_STREAM_OFFSET]; |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 568 | DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); |
| 569 | |
Erwan Gouriou | de4ba27 | 2020-04-13 21:38:58 +0200 | [diff] [blame] | 570 | /* give channel from index 0 */ |
Francois Ramu | 005968a | 2022-04-29 15:19:53 +0200 | [diff] [blame] | 571 | id = id - STM32_DMA_STREAM_OFFSET; |
Erwan Gouriou | de4ba27 | 2020-04-13 21:38:58 +0200 | [diff] [blame] | 572 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 573 | if (id >= config->max_streams) { |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 574 | return -EINVAL; |
| 575 | } |
| 576 | |
Shlomi Vaknin | 95143fc | 2021-03-30 18:22:30 +0300 | [diff] [blame] | 577 | #if !defined(CONFIG_DMAMUX_STM32) || defined(CONFIG_SOC_SERIES_STM32H7X) |
Erwin Rol | b05dc44 | 2020-08-22 14:28:52 +0200 | [diff] [blame] | 578 | LL_DMA_DisableIT_TC(dma, dma_stm32_id_to_stream(id)); |
Francois Ramu | 41df1c9 | 2020-04-23 11:38:06 +0200 | [diff] [blame] | 579 | #endif /* CONFIG_DMAMUX_STM32 */ |
| 580 | |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 581 | #if defined(CONFIG_DMA_STM32_V1) |
| 582 | stm32_dma_disable_fifo_irq(dma, id); |
| 583 | #endif |
| 584 | dma_stm32_disable_stream(dma, id); |
| 585 | dma_stm32_clear_stream_irq(dev, id); |
| 586 | |
| 587 | /* Finally, flag stream as free */ |
| 588 | stream->busy = false; |
| 589 | |
| 590 | return 0; |
| 591 | } |
| 592 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 593 | static int dma_stm32_init(const struct device *dev) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 594 | { |
Tomasz Bursztyka | af6140c | 2020-05-28 20:44:16 +0200 | [diff] [blame] | 595 | const struct dma_stm32_config *config = dev->config; |
Kumar Gala | b275fec | 2021-02-11 11:49:24 -0600 | [diff] [blame] | 596 | const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 597 | |
| 598 | if (clock_control_on(clk, |
| 599 | (clock_control_subsys_t *) &config->pclken) != 0) { |
| 600 | LOG_ERR("clock op failed\n"); |
| 601 | return -EIO; |
| 602 | } |
| 603 | |
| 604 | config->config_irq(dev); |
| 605 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 606 | for (uint32_t i = 0; i < config->max_streams; i++) { |
| 607 | config->streams[i].busy = false; |
Francois Ramu | 41df1c9 | 2020-04-23 11:38:06 +0200 | [diff] [blame] | 608 | #ifdef CONFIG_DMAMUX_STM32 |
| 609 | /* each further stream->mux_channel is fixed here */ |
Francois Ramu | 7208632 | 2020-10-15 08:50:23 +0200 | [diff] [blame] | 610 | config->streams[i].mux_channel = i + config->offset; |
Francois Ramu | 41df1c9 | 2020-04-23 11:38:06 +0200 | [diff] [blame] | 611 | #endif /* CONFIG_DMAMUX_STM32 */ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 612 | } |
| 613 | |
Francois Ramu | e90c47f | 2021-08-04 16:58:04 +0200 | [diff] [blame] | 614 | ((struct dma_stm32_data *)dev->data)->dma_ctx.magic = 0; |
| 615 | ((struct dma_stm32_data *)dev->data)->dma_ctx.dma_channels = 0; |
| 616 | ((struct dma_stm32_data *)dev->data)->dma_ctx.atomic = 0; |
| 617 | |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 618 | return 0; |
| 619 | } |
| 620 | |
Shlomi Vaknin | cad9685 | 2020-12-16 16:44:53 +0200 | [diff] [blame] | 621 | DMA_STM32_EXPORT_API int dma_stm32_get_status(const struct device *dev, |
| 622 | uint32_t id, struct dma_status *stat) |
Jun Li | 486dab0 | 2020-05-20 09:33:29 -0700 | [diff] [blame] | 623 | { |
Tomasz Bursztyka | af6140c | 2020-05-28 20:44:16 +0200 | [diff] [blame] | 624 | const struct dma_stm32_config *config = dev->config; |
Jun Li | 486dab0 | 2020-05-20 09:33:29 -0700 | [diff] [blame] | 625 | DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); |
Jun Li | 486dab0 | 2020-05-20 09:33:29 -0700 | [diff] [blame] | 626 | struct dma_stm32_stream *stream; |
| 627 | |
| 628 | /* give channel from index 0 */ |
Francois Ramu | 005968a | 2022-04-29 15:19:53 +0200 | [diff] [blame] | 629 | id = id - STM32_DMA_STREAM_OFFSET; |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 630 | if (id >= config->max_streams) { |
Jun Li | 486dab0 | 2020-05-20 09:33:29 -0700 | [diff] [blame] | 631 | return -EINVAL; |
| 632 | } |
| 633 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 634 | stream = &config->streams[id]; |
Erwin Rol | b05dc44 | 2020-08-22 14:28:52 +0200 | [diff] [blame] | 635 | stat->pending_length = LL_DMA_GetDataLength(dma, dma_stm32_id_to_stream(id)); |
Jun Li | 486dab0 | 2020-05-20 09:33:29 -0700 | [diff] [blame] | 636 | stat->dir = stream->direction; |
| 637 | stat->busy = stream->busy; |
| 638 | |
| 639 | return 0; |
| 640 | } |
| 641 | |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 642 | static const struct dma_driver_api dma_funcs = { |
| 643 | .reload = dma_stm32_reload, |
| 644 | .config = dma_stm32_configure, |
| 645 | .start = dma_stm32_start, |
| 646 | .stop = dma_stm32_stop, |
Jun Li | 486dab0 | 2020-05-20 09:33:29 -0700 | [diff] [blame] | 647 | .get_status = dma_stm32_get_status, |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 648 | }; |
| 649 | |
Francois Ramu | 7208632 | 2020-10-15 08:50:23 +0200 | [diff] [blame] | 650 | #ifdef CONFIG_DMAMUX_STM32 |
| 651 | #define DMA_STM32_OFFSET_INIT(index) \ |
| 652 | .offset = DT_INST_PROP(index, dma_offset), |
| 653 | #else |
| 654 | #define DMA_STM32_OFFSET_INIT(index) |
| 655 | #endif /* CONFIG_DMAMUX_STM32 */ |
| 656 | |
Erwan Gouriou | a214f41 | 2021-01-07 20:37:04 +0100 | [diff] [blame] | 657 | #ifdef CONFIG_DMA_STM32_V1 |
| 658 | #define DMA_STM32_MEM2MEM_INIT(index) \ |
| 659 | .support_m2m = DT_INST_PROP(index, st_mem2mem), |
| 660 | #else |
| 661 | #define DMA_STM32_MEM2MEM_INIT(index) |
| 662 | #endif /* CONFIG_DMA_STM32_V1 */ \ |
| 663 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 664 | #define DMA_STM32_INIT_DEV(index) \ |
| 665 | static struct dma_stm32_stream \ |
| 666 | dma_stm32_streams_##index[DMA_STM32_##index##_STREAM_COUNT]; \ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 667 | \ |
| 668 | const struct dma_stm32_config dma_stm32_config_##index = { \ |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 669 | .pclken = { .bus = DT_INST_CLOCKS_CELL(index, bus), \ |
| 670 | .enr = DT_INST_CLOCKS_CELL(index, bits) }, \ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 671 | .config_irq = dma_stm32_config_irq_##index, \ |
Erwin Rol | c8ae070 | 2020-08-23 09:20:17 +0200 | [diff] [blame] | 672 | .base = DT_INST_REG_ADDR(index), \ |
Erwan Gouriou | a214f41 | 2021-01-07 20:37:04 +0100 | [diff] [blame] | 673 | DMA_STM32_MEM2MEM_INIT(index) \ |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 674 | .max_streams = DMA_STM32_##index##_STREAM_COUNT, \ |
| 675 | .streams = dma_stm32_streams_##index, \ |
Francois Ramu | 7208632 | 2020-10-15 08:50:23 +0200 | [diff] [blame] | 676 | DMA_STM32_OFFSET_INIT(index) \ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 677 | }; \ |
| 678 | \ |
| 679 | static struct dma_stm32_data dma_stm32_data_##index = { \ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 680 | }; \ |
| 681 | \ |
Kumar Gala | c558235 | 2020-12-17 11:53:29 -0600 | [diff] [blame] | 682 | DEVICE_DT_INST_DEFINE(index, \ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 683 | &dma_stm32_init, \ |
Gerard Marull-Paretas | 861eac3 | 2021-04-28 10:35:17 +0200 | [diff] [blame] | 684 | NULL, \ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 685 | &dma_stm32_data_##index, &dma_stm32_config_##index, \ |
Maureen Helm | b539699 | 2021-10-28 13:49:26 -0500 | [diff] [blame] | 686 | PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 687 | &dma_funcs) |
| 688 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 689 | #ifdef CONFIG_DMA_STM32_SHARED_IRQS |
| 690 | |
| 691 | #define DMA_STM32_DEFINE_IRQ_HANDLER(dma, chan) /* nothing */ |
| 692 | |
| 693 | #define DMA_STM32_IRQ_CONNECT(dma, chan) \ |
| 694 | do { \ |
| 695 | IRQ_CONNECT(DT_INST_IRQ_BY_IDX(dma, chan, irq), \ |
| 696 | DT_INST_IRQ_BY_IDX(dma, chan, priority), \ |
| 697 | dma_stm32_shared_irq_handler, \ |
Kumar Gala | c558235 | 2020-12-17 11:53:29 -0600 | [diff] [blame] | 698 | DEVICE_DT_INST_GET(dma), 0); \ |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 699 | irq_enable(DT_INST_IRQ_BY_IDX(dma, chan, irq)); \ |
| 700 | } while (0) |
| 701 | |
| 702 | |
| 703 | #else /* CONFIG_DMA_STM32_SHARED_IRQS */ |
| 704 | |
| 705 | #define DMA_STM32_DEFINE_IRQ_HANDLER(dma, chan) \ |
| 706 | static void dma_stm32_irq_##dma##_##chan(const struct device *dev) \ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 707 | { \ |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 708 | dma_stm32_irq_handler(dev, chan); \ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 709 | } |
| 710 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 711 | |
| 712 | #define DMA_STM32_IRQ_CONNECT(dma, chan) \ |
| 713 | do { \ |
| 714 | IRQ_CONNECT(DT_INST_IRQ_BY_IDX(dma, chan, irq), \ |
Tomasz Bursztyka | 5c9dd0d | 2020-08-03 13:34:08 +0200 | [diff] [blame] | 715 | DT_INST_IRQ_BY_IDX(dma, chan, priority), \ |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 716 | dma_stm32_irq_##dma##_##chan, \ |
Kumar Gala | c558235 | 2020-12-17 11:53:29 -0600 | [diff] [blame] | 717 | DEVICE_DT_INST_GET(dma), 0); \ |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 718 | irq_enable(DT_INST_IRQ_BY_IDX(dma, chan, irq)); \ |
| 719 | } while (0) |
| 720 | |
| 721 | #endif /* CONFIG_DMA_STM32_SHARED_IRQS */ |
| 722 | |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 723 | |
Martí Bolívar | 6e8775f | 2020-05-11 11:56:08 -0700 | [diff] [blame] | 724 | #if DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 725 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 726 | DMA_STM32_DEFINE_IRQ_HANDLER(0, 0); |
| 727 | DMA_STM32_DEFINE_IRQ_HANDLER(0, 1); |
| 728 | DMA_STM32_DEFINE_IRQ_HANDLER(0, 2); |
| 729 | DMA_STM32_DEFINE_IRQ_HANDLER(0, 3); |
| 730 | DMA_STM32_DEFINE_IRQ_HANDLER(0, 4); |
Kumar Gala | 989484b | 2020-03-24 14:28:48 -0500 | [diff] [blame] | 731 | #if DT_INST_IRQ_HAS_IDX(0, 5) |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 732 | DMA_STM32_DEFINE_IRQ_HANDLER(0, 5); |
Kumar Gala | 989484b | 2020-03-24 14:28:48 -0500 | [diff] [blame] | 733 | #if DT_INST_IRQ_HAS_IDX(0, 6) |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 734 | DMA_STM32_DEFINE_IRQ_HANDLER(0, 6); |
Kumar Gala | 989484b | 2020-03-24 14:28:48 -0500 | [diff] [blame] | 735 | #if DT_INST_IRQ_HAS_IDX(0, 7) |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 736 | DMA_STM32_DEFINE_IRQ_HANDLER(0, 7); |
Kumar Gala | 989484b | 2020-03-24 14:28:48 -0500 | [diff] [blame] | 737 | #endif /* DT_INST_IRQ_HAS_IDX(0, 5) */ |
| 738 | #endif /* DT_INST_IRQ_HAS_IDX(0, 6) */ |
| 739 | #endif /* DT_INST_IRQ_HAS_IDX(0, 7) */ |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 740 | |
| 741 | static void dma_stm32_config_irq_0(const struct device *dev) |
| 742 | { |
| 743 | ARG_UNUSED(dev); |
| 744 | |
| 745 | DMA_STM32_IRQ_CONNECT(0, 0); |
| 746 | DMA_STM32_IRQ_CONNECT(0, 1); |
| 747 | #ifndef CONFIG_DMA_STM32_SHARED_IRQS |
| 748 | DMA_STM32_IRQ_CONNECT(0, 2); |
| 749 | #endif /* CONFIG_DMA_STM32_SHARED_IRQS */ |
| 750 | DMA_STM32_IRQ_CONNECT(0, 3); |
| 751 | #ifndef CONFIG_DMA_STM32_SHARED_IRQS |
| 752 | DMA_STM32_IRQ_CONNECT(0, 4); |
| 753 | #if DT_INST_IRQ_HAS_IDX(0, 5) |
| 754 | DMA_STM32_IRQ_CONNECT(0, 5); |
| 755 | #if DT_INST_IRQ_HAS_IDX(0, 6) |
| 756 | DMA_STM32_IRQ_CONNECT(0, 6); |
| 757 | #if DT_INST_IRQ_HAS_IDX(0, 7) |
| 758 | DMA_STM32_IRQ_CONNECT(0, 7); |
| 759 | #endif /* DT_INST_IRQ_HAS_IDX(0, 5) */ |
| 760 | #endif /* DT_INST_IRQ_HAS_IDX(0, 6) */ |
| 761 | #endif /* DT_INST_IRQ_HAS_IDX(0, 7) */ |
| 762 | #endif /* CONFIG_DMA_STM32_SHARED_IRQS */ |
Francois Ramu | 53dec09 | 2020-01-24 15:04:06 +0100 | [diff] [blame] | 763 | /* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 764 | } |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 765 | |
| 766 | DMA_STM32_INIT_DEV(0); |
| 767 | |
Martí Bolívar | 6e8775f | 2020-05-11 11:56:08 -0700 | [diff] [blame] | 768 | #endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */ |
Francois Ramu | 53dec09 | 2020-01-24 15:04:06 +0100 | [diff] [blame] | 769 | |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 770 | |
Martí Bolívar | 6e8775f | 2020-05-11 11:56:08 -0700 | [diff] [blame] | 771 | #if DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay) |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 772 | |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 773 | DMA_STM32_DEFINE_IRQ_HANDLER(1, 0); |
| 774 | DMA_STM32_DEFINE_IRQ_HANDLER(1, 1); |
| 775 | DMA_STM32_DEFINE_IRQ_HANDLER(1, 2); |
| 776 | DMA_STM32_DEFINE_IRQ_HANDLER(1, 3); |
Josh Hansen | ae4f68c | 2021-10-14 09:46:33 -0400 | [diff] [blame] | 777 | #if DT_INST_IRQ_HAS_IDX(1, 4) |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 778 | DMA_STM32_DEFINE_IRQ_HANDLER(1, 4); |
Kumar Gala | 989484b | 2020-03-24 14:28:48 -0500 | [diff] [blame] | 779 | #if DT_INST_IRQ_HAS_IDX(1, 5) |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 780 | DMA_STM32_DEFINE_IRQ_HANDLER(1, 5); |
Kumar Gala | 989484b | 2020-03-24 14:28:48 -0500 | [diff] [blame] | 781 | #if DT_INST_IRQ_HAS_IDX(1, 6) |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 782 | DMA_STM32_DEFINE_IRQ_HANDLER(1, 6); |
Kumar Gala | 989484b | 2020-03-24 14:28:48 -0500 | [diff] [blame] | 783 | #if DT_INST_IRQ_HAS_IDX(1, 7) |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 784 | DMA_STM32_DEFINE_IRQ_HANDLER(1, 7); |
Josh Hansen | ae4f68c | 2021-10-14 09:46:33 -0400 | [diff] [blame] | 785 | #endif /* DT_INST_IRQ_HAS_IDX(1, 4) */ |
Kumar Gala | 989484b | 2020-03-24 14:28:48 -0500 | [diff] [blame] | 786 | #endif /* DT_INST_IRQ_HAS_IDX(1, 5) */ |
| 787 | #endif /* DT_INST_IRQ_HAS_IDX(1, 6) */ |
| 788 | #endif /* DT_INST_IRQ_HAS_IDX(1, 7) */ |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 789 | |
| 790 | static void dma_stm32_config_irq_1(const struct device *dev) |
| 791 | { |
| 792 | ARG_UNUSED(dev); |
| 793 | |
Thomas Stranger | 5a475d7 | 2021-03-17 16:05:42 +0100 | [diff] [blame] | 794 | #ifndef CONFIG_DMA_STM32_SHARED_IRQS |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 795 | DMA_STM32_IRQ_CONNECT(1, 0); |
| 796 | DMA_STM32_IRQ_CONNECT(1, 1); |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 797 | DMA_STM32_IRQ_CONNECT(1, 2); |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 798 | DMA_STM32_IRQ_CONNECT(1, 3); |
Josh Hansen | ae4f68c | 2021-10-14 09:46:33 -0400 | [diff] [blame] | 799 | #if DT_INST_IRQ_HAS_IDX(1, 4) |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 800 | DMA_STM32_IRQ_CONNECT(1, 4); |
| 801 | #if DT_INST_IRQ_HAS_IDX(1, 5) |
| 802 | DMA_STM32_IRQ_CONNECT(1, 5); |
| 803 | #if DT_INST_IRQ_HAS_IDX(1, 6) |
| 804 | DMA_STM32_IRQ_CONNECT(1, 6); |
| 805 | #if DT_INST_IRQ_HAS_IDX(1, 7) |
| 806 | DMA_STM32_IRQ_CONNECT(1, 7); |
Josh Hansen | ae4f68c | 2021-10-14 09:46:33 -0400 | [diff] [blame] | 807 | #endif /* DT_INST_IRQ_HAS_IDX(1, 4) */ |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 808 | #endif /* DT_INST_IRQ_HAS_IDX(1, 5) */ |
| 809 | #endif /* DT_INST_IRQ_HAS_IDX(1, 6) */ |
| 810 | #endif /* DT_INST_IRQ_HAS_IDX(1, 7) */ |
| 811 | #endif /* CONFIG_DMA_STM32_SHARED_IRQS */ |
Thomas Stranger | 5a475d7 | 2021-03-17 16:05:42 +0100 | [diff] [blame] | 812 | /* |
| 813 | * Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. |
| 814 | * STM32F0 and STM32G0: if dma2 exits, the channel interrupts overlap with dma1 |
| 815 | */ |
Song Qiang | 749d2d2 | 2019-10-24 19:06:19 +0800 | [diff] [blame] | 816 | } |
Erwin Rol | 67f68e6 | 2020-08-21 23:50:00 +0200 | [diff] [blame] | 817 | |
| 818 | DMA_STM32_INIT_DEV(1); |
| 819 | |
Martí Bolívar | 6e8775f | 2020-05-11 11:56:08 -0700 | [diff] [blame] | 820 | #endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay) */ |