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Savinay Dharmappa87e54932018-11-12 21:06:24 +05301/*
2 * Copyright (c) 2018 Savoir-Faire Linux.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef __SPI_NOR_H__
8#define __SPI_NOR_H__
9
Gerard Marull-Paretasfb60aab2022-05-06 10:25:46 +020010#include <zephyr/sys/util.h>
Savinay Dharmappa87e54932018-11-12 21:06:24 +053011
12#define SPI_NOR_MAX_ID_LEN 3
13
Savinay Dharmappa87e54932018-11-12 21:06:24 +053014/* Status register bits */
15#define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */
16#define SPI_NOR_WEL_BIT BIT(1) /* Write enable latch */
Lukasz Majewskic1b60e72021-12-01 15:31:00 +010017#define SPI_NOR_QE_BIT BIT(6) /* Enable quad mode */
Savinay Dharmappa87e54932018-11-12 21:06:24 +053018
Lukasz Majewski029f49f2021-11-30 17:18:27 +010019/* Control register bits */
20#define SPI_NOR_4BYTE_BIT BIT(5) /* 4B addressing */
21
Savinay Dharmappa87e54932018-11-12 21:06:24 +053022/* Flash opcodes */
23#define SPI_NOR_CMD_WRSR 0x01 /* Write status register */
24#define SPI_NOR_CMD_RDSR 0x05 /* Read status register */
Zack Cornelius790e2bd2022-01-21 09:59:44 -060025#define SPI_NOR_CMD_WRSR2 0x31 /* Write status register 2 */
26#define SPI_NOR_CMD_RDSR2 0x35 /* Read status register 2 */
Savinay Dharmappa87e54932018-11-12 21:06:24 +053027#define SPI_NOR_CMD_READ 0x03 /* Read data */
Lukasz Majewski5599f1b2022-01-04 22:49:43 +010028#define SPI_NOR_CMD_DREAD 0x3B /* Read data (1-1-2) */
29#define SPI_NOR_CMD_QREAD 0x6B /* Read data (1-1-4) */
30#define SPI_NOR_CMD_4READ 0xEB /* Read data (1-4-4) */
Savinay Dharmappa87e54932018-11-12 21:06:24 +053031#define SPI_NOR_CMD_WREN 0x06 /* Write enable */
32#define SPI_NOR_CMD_WRDI 0x04 /* Write disable */
33#define SPI_NOR_CMD_PP 0x02 /* Page program */
Lukasz Majewski5599f1b2022-01-04 22:49:43 +010034#define SPI_NOR_CMD_4PP 0x38 /* Page program (1-4-4) */
Lukasz Majewski029f49f2021-11-30 17:18:27 +010035#define SPI_NOR_CMD_RDCR 0x15 /* Read control register */
Savinay Dharmappa87e54932018-11-12 21:06:24 +053036#define SPI_NOR_CMD_SE 0x20 /* Sector erase */
37#define SPI_NOR_CMD_BE_32K 0x52 /* Block erase 32KB */
38#define SPI_NOR_CMD_BE 0xD8 /* Block erase */
39#define SPI_NOR_CMD_CE 0xC7 /* Chip erase */
40#define SPI_NOR_CMD_RDID 0x9F /* Read JEDEC ID */
Peter A. Bigote4c37292019-10-27 09:21:38 -050041#define SPI_NOR_CMD_ULBPR 0x98 /* Global Block Protection Unlock */
Peter Bigotc26cdb72021-03-03 13:30:12 -060042#define SPI_NOR_CMD_4BA 0xB7 /* Enter 4-Byte Address Mode */
Peter A. Bigot98a344f2019-10-27 12:57:09 -050043#define SPI_NOR_CMD_DPD 0xB9 /* Deep Power Down */
44#define SPI_NOR_CMD_RDPD 0xAB /* Release from Deep Power Down */
Savinay Dharmappa87e54932018-11-12 21:06:24 +053045
Peter A. Bigot2a590d32019-07-20 14:09:10 -050046/* Page, sector, and block size are standard, not configurable. */
47#define SPI_NOR_PAGE_SIZE 0x0100U
48#define SPI_NOR_SECTOR_SIZE 0x1000U
49#define SPI_NOR_BLOCK_SIZE 0x10000U
50
Peter A. Bigot810920f2020-05-30 17:44:08 -050051/* Test whether offset is aligned to a given number of bits. */
52#define SPI_NOR_IS_ALIGNED(_ofs, _bits) (((_ofs) & BIT_MASK(_bits)) == 0)
53#define SPI_NOR_IS_SECTOR_ALIGNED(_ofs) SPI_NOR_IS_ALIGNED(_ofs, 12)
Peter A. Bigot2a590d32019-07-20 14:09:10 -050054
Savinay Dharmappa87e54932018-11-12 21:06:24 +053055#endif /*__SPI_NOR_H__*/