FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_g.c

/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
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*all copies or substantial portions of the Software.
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*(a) running on a Xilinx device, or
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* 
* Description: Driver configuration
*
*******************************************************************/

#include "xparameters.h"
#include "xzdma.h"

/*
* The configuration table for devices
*/

XZDma_Config XZDma_ConfigTable[XPAR_XZDMA_NUM_INSTANCES] =
{
	{
		XPAR_PSU_ADMA_0_DEVICE_ID,
		XPAR_PSU_ADMA_0_BASEADDR,
		XPAR_PSU_ADMA_0_DMA_MODE,
		XPAR_PSU_ADMA_0_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_1_DEVICE_ID,
		XPAR_PSU_ADMA_1_BASEADDR,
		XPAR_PSU_ADMA_1_DMA_MODE,
		XPAR_PSU_ADMA_1_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_2_DEVICE_ID,
		XPAR_PSU_ADMA_2_BASEADDR,
		XPAR_PSU_ADMA_2_DMA_MODE,
		XPAR_PSU_ADMA_2_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_3_DEVICE_ID,
		XPAR_PSU_ADMA_3_BASEADDR,
		XPAR_PSU_ADMA_3_DMA_MODE,
		XPAR_PSU_ADMA_3_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_4_DEVICE_ID,
		XPAR_PSU_ADMA_4_BASEADDR,
		XPAR_PSU_ADMA_4_DMA_MODE,
		XPAR_PSU_ADMA_4_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_5_DEVICE_ID,
		XPAR_PSU_ADMA_5_BASEADDR,
		XPAR_PSU_ADMA_5_DMA_MODE,
		XPAR_PSU_ADMA_5_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_6_DEVICE_ID,
		XPAR_PSU_ADMA_6_BASEADDR,
		XPAR_PSU_ADMA_6_DMA_MODE,
		XPAR_PSU_ADMA_6_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_7_DEVICE_ID,
		XPAR_PSU_ADMA_7_BASEADDR,
		XPAR_PSU_ADMA_7_DMA_MODE,
		XPAR_PSU_ADMA_7_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_0_DEVICE_ID,
		XPAR_PSU_GDMA_0_BASEADDR,
		XPAR_PSU_GDMA_0_DMA_MODE,
		XPAR_PSU_GDMA_0_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_1_DEVICE_ID,
		XPAR_PSU_GDMA_1_BASEADDR,
		XPAR_PSU_GDMA_1_DMA_MODE,
		XPAR_PSU_GDMA_1_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_2_DEVICE_ID,
		XPAR_PSU_GDMA_2_BASEADDR,
		XPAR_PSU_GDMA_2_DMA_MODE,
		XPAR_PSU_GDMA_2_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_3_DEVICE_ID,
		XPAR_PSU_GDMA_3_BASEADDR,
		XPAR_PSU_GDMA_3_DMA_MODE,
		XPAR_PSU_GDMA_3_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_4_DEVICE_ID,
		XPAR_PSU_GDMA_4_BASEADDR,
		XPAR_PSU_GDMA_4_DMA_MODE,
		XPAR_PSU_GDMA_4_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_5_DEVICE_ID,
		XPAR_PSU_GDMA_5_BASEADDR,
		XPAR_PSU_GDMA_5_DMA_MODE,
		XPAR_PSU_GDMA_5_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_6_DEVICE_ID,
		XPAR_PSU_GDMA_6_BASEADDR,
		XPAR_PSU_GDMA_6_DMA_MODE,
		XPAR_PSU_GDMA_6_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_7_DEVICE_ID,
		XPAR_PSU_GDMA_7_BASEADDR,
		XPAR_PSU_GDMA_7_DMA_MODE,
		XPAR_PSU_GDMA_7_IS_CACHE_COHERENT
	}
};