Release v2.3.3
diff --git a/Include/stm32l100xb.h b/Include/stm32l100xb.h
index 9b5af5d..c582b36 100644
--- a/Include/stm32l100xb.h
+++ b/Include/stm32l100xb.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -863,7 +862,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -2751,7 +2750,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT1
@@ -3658,7 +3657,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4465,7 +4464,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4515,7 +4514,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
@@ -5006,7 +5005,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
/******************* Bit definition for SPI_CR1 register ********************/
@@ -6078,12 +6077,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -7666,4 +7674,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l100xba.h b/Include/stm32l100xba.h
index 8f80f90..e055a31 100644
--- a/Include/stm32l100xba.h
+++ b/Include/stm32l100xba.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -863,7 +862,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -2754,7 +2753,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT2
@@ -3664,7 +3663,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -3833,7 +3832,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4492,7 +4491,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4542,7 +4541,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5154,7 +5153,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
/******************* Bit definition for SPI_CR1 register ********************/
@@ -6226,12 +6225,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -7814,4 +7822,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l100xc.h b/Include/stm32l100xc.h
index f0cd00b..739353e 100644
--- a/Include/stm32l100xc.h
+++ b/Include/stm32l100xc.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -908,7 +907,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -2850,7 +2849,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT3
@@ -3766,7 +3765,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -3935,7 +3934,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4612,7 +4611,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4662,7 +4661,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5274,7 +5273,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -6811,12 +6810,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -8412,4 +8420,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l151xb.h b/Include/stm32l151xb.h
index 161dbdd..c11d636 100644
--- a/Include/stm32l151xb.h
+++ b/Include/stm32l151xb.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -864,7 +863,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -2752,7 +2751,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT1
@@ -4350,7 +4349,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4400,7 +4399,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
@@ -4966,7 +4965,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
/******************* Bit definition for SPI_CR1 register ********************/
@@ -6030,12 +6029,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -7615,4 +7623,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l151xba.h b/Include/stm32l151xba.h
index 69ea9c2..c18a4c2 100644
--- a/Include/stm32l151xba.h
+++ b/Include/stm32l151xba.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -864,7 +863,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -2755,7 +2754,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT2
@@ -3721,7 +3720,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4380,7 +4379,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4430,7 +4429,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5042,7 +5041,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
/******************* Bit definition for SPI_CR1 register ********************/
@@ -6106,12 +6105,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -7691,4 +7699,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l151xc.h b/Include/stm32l151xc.h
index 9e04ae2..b5d6cd2 100644
--- a/Include/stm32l151xc.h
+++ b/Include/stm32l151xc.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -945,7 +944,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -1033,6 +1032,27 @@
#define ADC_SMPR1_SMP26_1 (0x2UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP26_2 (0x4UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */
+#define ADC_SMPR1_SMP27_Pos (21U)
+#define ADC_SMPR1_SMP27_Msk (0x7UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP27 ADC_SMPR1_SMP27_Msk /*!< ADC channel 27 sampling time selection */
+#define ADC_SMPR1_SMP27_0 (0x1UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP27_1 (0x2UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP27_2 (0x4UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP28_Pos (24U)
+#define ADC_SMPR1_SMP28_Msk (0x7UL << ADC_SMPR1_SMP28_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP28 ADC_SMPR1_SMP28_Msk /*!< ADC channel 28 sampling time selection */
+#define ADC_SMPR1_SMP28_0 (0x1UL << ADC_SMPR1_SMP28_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP28_1 (0x2UL << ADC_SMPR1_SMP28_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP28_2 (0x4UL << ADC_SMPR1_SMP28_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP29_Pos (27U)
+#define ADC_SMPR1_SMP29_Msk (0x7UL << ADC_SMPR1_SMP29_Pos) /*!< 0x38000000 */
+#define ADC_SMPR1_SMP29 ADC_SMPR1_SMP29_Msk /*!< ADC channel 29 sampling time selection */
+#define ADC_SMPR1_SMP29_0 (0x1UL << ADC_SMPR1_SMP29_Pos) /*!< 0x08000000 */
+#define ADC_SMPR1_SMP29_1 (0x2UL << ADC_SMPR1_SMP29_Pos) /*!< 0x10000000 */
+#define ADC_SMPR1_SMP29_2 (0x4UL << ADC_SMPR1_SMP29_Pos) /*!< 0x20000000 */
+
/****************** Bit definition for ADC_SMPR2 register *******************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
@@ -2995,7 +3015,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT3
@@ -3967,7 +3987,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4653,7 +4673,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4703,7 +4723,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5450,7 +5470,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -6979,12 +6999,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -8612,4 +8641,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l151xca.h b/Include/stm32l151xca.h
index b3427af..7c4fc64 100644
--- a/Include/stm32l151xca.h
+++ b/Include/stm32l151xca.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -949,7 +948,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3038,7 +3037,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT3
@@ -4004,7 +4003,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4708,7 +4707,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4758,7 +4757,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5505,7 +5504,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7064,12 +7063,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -8699,4 +8707,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l151xd.h b/Include/stm32l151xd.h
index f09b8e2..7445c72 100644
--- a/Include/stm32l151xd.h
+++ b/Include/stm32l151xd.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1023,7 +1022,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3154,7 +3153,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT4
@@ -4311,7 +4310,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -5051,7 +5050,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -5101,7 +5100,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -6205,7 +6204,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7764,12 +7763,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -9413,4 +9421,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l151xdx.h b/Include/stm32l151xdx.h
index 5583b59..de65138 100644
--- a/Include/stm32l151xdx.h
+++ b/Include/stm32l151xdx.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -966,7 +965,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3055,7 +3054,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT6
@@ -4051,7 +4050,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4773,7 +4772,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4823,7 +4822,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5570,7 +5569,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7129,12 +7128,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -8774,4 +8782,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l151xe.h b/Include/stm32l151xe.h
index 6985398..a597567 100644
--- a/Include/stm32l151xe.h
+++ b/Include/stm32l151xe.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -966,7 +965,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3055,7 +3054,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT5
@@ -4051,7 +4050,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4773,7 +4772,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4823,7 +4822,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5570,7 +5569,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7129,12 +7128,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -8774,4 +8782,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l152xb.h b/Include/stm32l152xb.h
index a4cf861..345f3a9 100644
--- a/Include/stm32l152xb.h
+++ b/Include/stm32l152xb.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -881,7 +880,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -2769,7 +2768,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT1
@@ -3676,7 +3675,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4492,7 +4491,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4542,7 +4541,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
@@ -5108,7 +5107,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
/******************* Bit definition for SPI_CR1 register ********************/
@@ -6180,12 +6179,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -7769,4 +7777,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l152xba.h b/Include/stm32l152xba.h
index 12f15e1..82372aa 100644
--- a/Include/stm32l152xba.h
+++ b/Include/stm32l152xba.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -866,7 +865,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -2757,7 +2756,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT2
@@ -3670,7 +3669,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -3839,7 +3838,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4507,7 +4506,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4557,7 +4556,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5169,7 +5168,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
/******************* Bit definition for SPI_CR1 register ********************/
@@ -6241,12 +6240,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -7830,4 +7838,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l152xc.h b/Include/stm32l152xc.h
index b659ccc..17b989a 100644
--- a/Include/stm32l152xc.h
+++ b/Include/stm32l152xc.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -962,7 +961,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3012,7 +3011,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT3
@@ -3931,7 +3930,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4100,7 +4099,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4795,7 +4794,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4845,7 +4844,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5592,7 +5591,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7129,12 +7128,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -8766,4 +8774,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l152xca.h b/Include/stm32l152xca.h
index 701532d..78897d4 100644
--- a/Include/stm32l152xca.h
+++ b/Include/stm32l152xca.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -966,7 +965,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3055,7 +3054,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT3
@@ -3968,7 +3967,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4137,7 +4136,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4850,7 +4849,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4900,7 +4899,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5647,7 +5646,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7214,12 +7213,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -8853,4 +8861,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l152xd.h b/Include/stm32l152xd.h
index bb0ad24..487cc53 100644
--- a/Include/stm32l152xd.h
+++ b/Include/stm32l152xd.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1040,7 +1039,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3171,7 +3170,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT4
@@ -4275,7 +4274,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4444,7 +4443,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -5193,7 +5192,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -5243,7 +5242,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -6347,7 +6346,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7914,12 +7913,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -9567,4 +9575,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l152xdx.h b/Include/stm32l152xdx.h
index 1eaf3af..af9d615 100644
--- a/Include/stm32l152xdx.h
+++ b/Include/stm32l152xdx.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -983,7 +982,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3072,7 +3071,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT6
@@ -4015,7 +4014,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4184,7 +4183,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4915,7 +4914,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4965,7 +4964,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5712,7 +5711,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7279,12 +7278,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -8928,4 +8936,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l152xe.h b/Include/stm32l152xe.h
index 9589a79..f6b3345 100644
--- a/Include/stm32l152xe.h
+++ b/Include/stm32l152xe.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -983,7 +982,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3072,7 +3071,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT5
@@ -4015,7 +4014,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4184,7 +4183,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4915,7 +4914,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4965,7 +4964,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5712,7 +5711,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7279,12 +7278,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -8928,4 +8936,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l162xc.h b/Include/stm32l162xc.h
index 7ae05e8..dc550bb 100644
--- a/Include/stm32l162xc.h
+++ b/Include/stm32l162xc.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -985,7 +984,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3142,7 +3141,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT3
@@ -4061,7 +4060,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4230,7 +4229,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4934,7 +4933,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4984,7 +4983,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5731,7 +5730,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7268,12 +7267,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -8908,4 +8916,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l162xca.h b/Include/stm32l162xca.h
index 3944173..7994a7d 100644
--- a/Include/stm32l162xca.h
+++ b/Include/stm32l162xca.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -989,7 +988,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3185,7 +3184,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT3
@@ -4098,7 +4097,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4267,7 +4266,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -4989,7 +4988,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -5039,7 +5038,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5786,7 +5785,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7353,12 +7352,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -8995,4 +9003,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l162xd.h b/Include/stm32l162xd.h
index f86f329..9194d37 100644
--- a/Include/stm32l162xd.h
+++ b/Include/stm32l162xd.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1063,7 +1062,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3301,7 +3300,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT4
@@ -4405,7 +4404,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4574,7 +4573,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -5332,7 +5331,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -5382,7 +5381,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -6486,7 +6485,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -8053,12 +8052,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -9709,4 +9717,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l162xdx.h b/Include/stm32l162xdx.h
index eda15e0..4123fd3 100644
--- a/Include/stm32l162xdx.h
+++ b/Include/stm32l162xdx.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1006,7 +1005,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3202,7 +3201,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT6
@@ -4145,7 +4144,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4314,7 +4313,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -5054,7 +5053,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -5104,7 +5103,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5851,7 +5850,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7418,12 +7417,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -9070,4 +9078,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l162xe.h b/Include/stm32l162xe.h
index 689cfce..43c793c 100644
--- a/Include/stm32l162xe.h
+++ b/Include/stm32l162xe.h
@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1006,7 +1005,7 @@
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -3202,7 +3201,7 @@
/* */
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
*/
#define FLASH_CUT5
@@ -4145,7 +4144,7 @@
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
-#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4314,7 +4313,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
@@ -5054,7 +5053,7 @@
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
-/*!< RTC congiguration */
+/*!< RTC configuration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -5104,7 +5103,7 @@
/* */
/******************************************************************************/
/*
-* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
+* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5851,7 +5850,7 @@
/******************************************************************************/
/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
*/
#define SPI_I2S_SUPPORT
@@ -7418,12 +7417,21 @@
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION_Pos (0U)
-#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos (4U)
-#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
+
+/* Legacy aliases */
+#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
+#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
+
+#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
+#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
@@ -9070,4 +9078,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l1xx.h b/Include/stm32l1xx.h
index b4f7889..e4d1888 100644
--- a/Include/stm32l1xx.h
+++ b/Include/stm32l1xx.h
@@ -8,21 +8,20 @@
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32L1xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
- * code will be based on direct access to peripherals registers
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -100,11 +99,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.3.2
+ * @brief CMSIS Device version number
*/
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
+#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
@@ -298,4 +297,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/system_stm32l1xx.h b/Include/system_stm32l1xx.h
index 6fa05ff..a5d1733 100644
--- a/Include/system_stm32l1xx.h
+++ b/Include/system_stm32l1xx.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -105,4 +104,4 @@
/**
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/License.md b/License.md
index e0d829b..261eeb9 100644
--- a/License.md
+++ b/License.md
@@ -1,80 +1,198 @@
-Apache License
- Version 2.0, January 2004
- http://www.apache.org/licenses/
+ Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
-TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
-1. Definitions.
+ 1. Definitions.
-"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document.
+ "License" shall mean the terms and conditions for use, reproduction,
+ and distribution as defined by Sections 1 through 9 of this document.
-"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License.
+ "Licensor" shall mean the copyright owner or entity authorized by
+ the copyright owner that is granting the License.
-"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity.
+ "Legal Entity" shall mean the union of the acting entity and all
+ other entities that control, are controlled by, or are under common
+ control with that entity. For the purposes of this definition,
+ "control" means (i) the power, direct or indirect, to cause the
+ direction or management of such entity, whether by contract or
+ otherwise, or (ii) ownership of fifty percent (50%) or more of the
+ outstanding shares, or (iii) beneficial ownership of such entity.
-"You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License.
+ "You" (or "Your") shall mean an individual or Legal Entity
+ exercising permissions granted by this License.
-"Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files.
+ "Source" form shall mean the preferred form for making modifications,
+ including but not limited to software source code, documentation
+ source, and configuration files.
-"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types.
+ "Object" form shall mean any form resulting from mechanical
+ transformation or translation of a Source form, including but
+ not limited to compiled object code, generated documentation,
+ and conversions to other media types.
-"Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below).
+ "Work" shall mean the work of authorship, whether in Source or
+ Object form, made available under the License, as indicated by a
+ copyright notice that is included in or attached to the work
+ (an example is provided in the Appendix below).
-"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof.
+ "Derivative Works" shall mean any work, whether in Source or Object
+ form, that is based on (or derived from) the Work and for which the
+ editorial revisions, annotations, elaborations, or other modifications
+ represent, as a whole, an original work of authorship. For the purposes
+ of this License, Derivative Works shall not include works that remain
+ separable from, or merely link (or bind by name) to the interfaces of,
+ the Work and Derivative Works thereof.
-"Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution."
+ "Contribution" shall mean any work of authorship, including
+ the original version of the Work and any modifications or additions
+ to that Work or Derivative Works thereof, that is intentionally
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+ means any form of electronic, verbal, or written communication sent
+ to the Licensor or its representatives, including but not limited to
+ communication on electronic mailing lists, source code control systems,
+ and issue tracking systems that are managed by, or on behalf of, the
+ Licensor for the purpose of discussing and improving the Work, but
+ excluding communication that is conspicuously marked or otherwise
+ designated in writing by the copyright owner as "Not a Contribution."
-"Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work.
+ "Contributor" shall mean Licensor and any individual or Legal Entity
+ on behalf of whom a Contribution has been received by Licensor and
+ subsequently incorporated within the Work.
-2. Grant of Copyright License.
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+ worldwide, non-exclusive, no-charge, royalty-free, irrevocable
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+ Work and such Derivative Works in Source or Object form.
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+ 3. Grant of Patent License. Subject to the terms and conditions of
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diff --git a/Release_Notes.html b/Release_Notes.html
index 97c7930..e7c33c8 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -11,24 +11,21 @@
span.underline{text-decoration: underline;}
div.column{display: inline-block; vertical-align: top; width: 50%;}
</style>
- <link rel="stylesheet" href="_htmresc/mini-st.css" />
+ <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
<!--[if lt IE 9]>
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
<![endif]-->
+ <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
</head>
<body>
<div class="row">
<div class="col-sm-12 col-lg-4">
-<div class="card fluid">
-<div class="sectione dark">
<center>
<h1 id="release-notes-for-stm32l1xx-cmsis"><small>Release Notes for</small> <mark>STM32L1xx CMSIS</mark></h1>
-<p>Copyright © 2009-2018 ARM Limited - STMicroelectronics<br />
+<p>Copyright © 2016 STMicroelectronics<br />
</p>
-<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
-</div>
-</div>
<h1 id="purpose">Purpose</h1>
<p>This driver provides the CMSIS device for the stm32l1xx products. This covers:</p>
<ul>
@@ -48,12 +45,27 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section13" checked aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V2.3.2 / 21-May-2021</label>
+<input type="checkbox" id="collapse-section14" checked aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V2.3.3 / 07-April-2023</label>
<div>
<h2 id="main-changes">Main Changes</h2>
-<h3 id="maintenance-release">Maintenance release</h3>
+<h3 id="patch-release">Patch release</h3>
<h2 id="contents">Contents</h2>
<ul>
+<li>All source files: update disclaimer to add reference to the new license agreement.</li>
+<li>Update define value of HSI_VALUE to 16 Mhz to be aligned with reference manual.</li>
+<li>Align USART_BRR_DIV_Fraction and USART_BRR_DIV_Mantissa bits definitions with the reference manual.</li>
+<li>Add definitions for channel 27, 28 and 29 in the ADC sample time register1 in stm32l151xc.h file.</li>
+<li>Update the GCC startup file to be aligned to IAR/Keil IDE.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V2.3.2 / 21-May-2021</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3 id="maintenance-release">Maintenance release</h3>
+<h2 id="contents-1">Contents</h2>
+<ul>
<li>Improve GCC startup files robustness.</li>
<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li>
<li>Add atomic register access macros.</li>
@@ -67,9 +79,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V2.3.1 / 24-June-2020</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<h3 id="maintenance-release-1">Maintenance release</h3>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
<ul>
<li>All header files
<ul>
@@ -94,9 +106,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V2.3.0 / 05-April-2019</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<h3 id="maintenance-release-2">Maintenance release</h3>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-3">Contents</h2>
<ul>
<li>stm32l0xx.h
<ul>
@@ -106,7 +118,7 @@
<ul>
<li>Update header of startup files to remove build error with ARM compiler.</li>
</ul></li>
-<li>Updated Update CMSIS Devices compliancy with MISRA C 2012 rules
+<li>Updated Update CMSIS Devices compliance with MISRA C 2012 rules
<ul>
<li>Rule-10.6: Use ‘UL’ postfix for _Msk definitions and memory/peripheral base addresses</li>
</ul></li>
@@ -123,9 +135,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V2.2.3 / 12-January-2018</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
-<h3 id="patch-release">Patch release</h3>
-<h2 id="contents-3">Contents</h2>
+<h2 id="main-changes-4">Main Changes</h2>
+<h3 id="patch-release-1">Patch release</h3>
+<h2 id="contents-4">Contents</h2>
<ul>
<li>Corrected devices supporting RI_HYSCR3, RI_HYSCR4, RI_ASMRx, RI_CMRx, RI_CICRx registers in CMSIS files.</li>
</ul>
@@ -134,9 +146,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V2.2.2 / 25-August-2017</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<h3 id="maintenance-release-3">Maintenance release</h3>
-<h2 id="contents-4">Contents</h2>
+<h2 id="contents-5">Contents</h2>
<ul>
<li>Removed DATE and VERSION fields from header files.</li>
</ul>
@@ -145,11 +157,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V2.2.1 / 21-April-2017</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<h3 id="maintenance-release-4">Maintenance release</h3>
-<h2 id="contents-5">Contents</h2>
+<h2 id="contents-6">Contents</h2>
<ul>
-<li>Update CMSIS Devices compliancy with MISRA C 2004 rules:
+<li>Update CMSIS Devices compliance with MISRA C 2004 rules:
<ul>
<li>MISRA C 2004 rule 10.6 (‘U’ suffix applied to all constants of ‘unsigned’ type)</li>
<li>Update system_stm32l1xx.h/.c files.</li>
@@ -163,9 +175,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V2.2.0 / 01-July-2016</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<h3 id="maintenance-release-5">Maintenance release</h3>
-<h2 id="contents-6">Contents</h2>
+<h2 id="contents-7">Contents</h2>
<ul>
<li>Add macros _Pos and _Msk for each constants.
<ul>
@@ -193,9 +205,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V2.1.3 / 04-March-2016</label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<h3 id="maintenance-release-6">Maintenance release</h3>
-<h2 id="contents-7">Contents</h2>
+<h2 id="contents-8">Contents</h2>
<ul>
<li>Add HardFault_IRQn.</li>
<li>Add BKP5R to BKP19R for RTC_TypeDef for stm32l151xba.</li>
@@ -232,14 +244,14 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V2.1.2 / 09-October-2015</label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<h3 id="maintenance-release-7">Maintenance release</h3>
-<h2 id="contents-8">Contents</h2>
+<h2 id="contents-9">Contents</h2>
<ul>
<li>Removing the __IO attribute for PLLMulTable and AHBPrescTable. This was leading to issue during C++ initialisation.</li>
<li>IDR field of CRC_TypeDef changed from uint32_t to uint8_t to comply with register structure.</li>
<li>Added TIM10 and TIM11 to IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE).</li>
-<li>Renaming USB_CNTR_LP_MODE to USB_CNTR_LPMODE for naming consistancy with other bits.</li>
+<li>Renaming USB_CNTR_LP_MODE to USB_CNTR_LPMODE for naming consistency with other bits.</li>
<li>Renaming USB_ISTR_PMAOVRM to USB_ISTR_PMAOVR to use the name of the bit in this register.</li>
</ul>
</div>
@@ -247,11 +259,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V2.1.1 / 31-March-2015</label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<h3 id="maintenance-release-8">Maintenance release</h3>
-<h2 id="contents-9">Contents</h2>
+<h2 id="contents-10">Contents</h2>
<ul>
-<li>Ensure compliancy w/ C++</li>
+<li>Ensure compliance w/ C++</li>
<li>Minor update on Timer assert.</li>
<li>Adding IS_AES_ALL_INSTANCE macro for product with AES.</li>
</ul>
@@ -260,9 +272,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V2.1.0 / 06-February-2015</label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<h3 id="maintenance-release-9">Maintenance release</h3>
-<h2 id="contents-10">Contents</h2>
+<h2 id="contents-11">Contents</h2>
<ul>
<li>Add CMSIS files for new STM32L1 e<strong>X</strong>tended Devices : <strong>STM32L151xDX, STM32L152xDX and STM32L162xDX</strong></li>
</ul>
@@ -271,9 +283,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V2.0.0 / 05-September-2014</label>
<div>
-<h2 id="main-changes-11">Main Changes</h2>
+<h2 id="main-changes-12">Main Changes</h2>
<h3 id="maintenance-release-10">Maintenance release</h3>
-<h2 id="contents-11">Contents</h2>
+<h2 id="contents-12">Contents</h2>
<ul>
<li>Update based on STM32Cube specification</li>
</ul>
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-<meta content="MCD Application Team" name="author"></head>
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-<td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../Release_Notes.html">Back to Release page</a></span></td>
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-<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for<o:p></o:p> STM32L1xx CMSIS<br>
-</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
-© 2017 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update history</span></h2><span style="font-family: "Times New Roman";"><span style="font-weight: bold;"></span></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 0cm; font-size: 13.5pt; font-family: "Times New Roman"; font-weight: bold; color: rgb(0, 0, 0); font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.3.0 / 26-October-2018</span></h3><b style="color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; font-size: medium; font-family: "Times New Roman"; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes</span></u></b><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></p><ul style="margin-bottom: 0cm; color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; list-style-type: square;"><li><span style="text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; font-family: Verdana; font-style: normal; font-weight: normal; font-size: 13px; line-height: normal; font-stretch: normal; white-space: normal; color: rgb(0, 0, 0); word-spacing: 0px; display: inline ! important;">Updated header of startup files for GCC toolchain after removal of Atollic TrueSTUDIO toolchain support.</span></li><li><span style="text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; font-family: Verdana; font-style: normal; font-weight: normal; font-size: 13px; line-height: normal; font-stretch: normal; white-space: normal; color: rgb(0, 0, 0); word-spacing: 0px; display: inline ! important;">Corrected definitions for USB_COUNT3_TX_0 and USB_COUNT3_TX_1 registers.</span></li><li><span style="text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; font-family: Verdana; font-style: normal; font-weight: normal; font-size: 13px; line-height: normal; font-stretch: normal; white-space: normal; color: rgb(0, 0, 0); word-spacing: 0px; display: inline ! important;">Updated macros definition for TIM instances.<br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 0cm; font-size: 13.5pt; font-family: "Times New Roman"; font-weight: bold; color: rgb(0, 0, 0); font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.3 / 12-January-2018</span></h3><b style="color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; font-size: medium; font-family: "Times New Roman"; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes</span></u></b><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></p><ul style="margin-bottom: 0cm; color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; list-style-type: square;"><li><span style="text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; font-family: Verdana; font-style: normal; font-weight: normal; font-size: 13px; line-height: normal; font-stretch: normal; white-space: normal; float: none; color: rgb(0, 0, 0); word-spacing: 0px; display: inline ! important;">Corrected devices supporting RI_HYSCR3, RI_HYSCR4, RI_ASMRx, RI_CMRx, RI_CICRx registers in CMSIS files.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 0cm; font-size: 13.5pt; font-family: "Times New Roman"; font-weight: bold; color: rgb(0, 0, 0); font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.2 / 25-August-2017</span></h3><b style="color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; font-size: medium; font-family: "Times New Roman"; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes</span></u></b><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></p><ul style="margin-bottom: 0cm; color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; list-style-type: square;"><li><span style="text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; font-family: Verdana; font-style: normal; font-weight: normal; font-size: 13px; line-height: normal; font-stretch: normal; white-space: normal; float: none; color: rgb(0, 0, 0); word-spacing: 0px; display: inline ! important;">Removed DATE and VERSION fields from header files</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.1
-/ 21-April-2017</span></h3>
-<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-</p>
-<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">General updates:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated CMSIS Device compliancy with MISRA C 2004 rules:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.6 </span><span style="font-size: 10pt; font-family: Verdana;">('U' suffix applied to all constants of 'unsigned' type)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">U</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">pdated system_stm32l1xx.h/.c files.<br></span></li></ul></ul><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Aligned Bit definitions for SCB_CFSR register to be compliant with CMSIS Core V4.x and V5.x.</span></li><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Renamed RTC_CR_BCK bits in RTC_CR register to RTC_CR_BKP, to be aligned with others series.</span></li><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Renamed GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit definitions (from GPIO_AFRL/AFRH registers) to GPIO_AFRL_AFSELx.<br><br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.0
-/ 01-July-2016 <o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-</p>
-<ul style="list-style-type: square;">
-<li>Add macros _Pos and _Msk for each constants.</li>
-<ul>
-<li>For instance:</li>
-<ul>
-<li style="font-family: Courier New;">#define
-ADC_LTR_LT
- ((uint32_t)0x00000FFFU)</li>
-</ul>
-<li>Is now provided as:</li>
-<ul>
-<li style="font-family: Courier New;">#define
-ADC_LTR_LT_Pos (0U) </li>
-<li style="font-family: Courier New;">#define
-ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos)</li>
-<li><span style="font-family: Courier New;">#define
-ADC_LTR_LT ADC_LTR_LT_Msk</span></li>
-</ul>
-</ul>
-</ul>
-<ul style="list-style-type: square;">
-<li>IS_I2S_ALL_INSTANCE is now SPI2 and SPI3
-instead of SPI1 and SPI2.</li>
-<li>Update the TIM_ARR_ARR and TIM_CNT_CNT as they
-support the 32 bit counter feature.</li>
-<li>Add macro IS_TIM_ETR_INSTANCE.</li>
-<li>Add RI_ASCR2_GR6_x with x = 1,2,3,4 if
-applicable.</li>
-<li>Add macro IS_SMBUS_ALL_INSTANCE.</li>
-<li>Set default value for SystemCoreClock to
-2097000 instead of 32000000.</li>
-<li>Correct the presence of TIM9 for some devices
-inside various TIMER macros.</li>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.3
-/ 04-March-2016 <o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-</p>
-<ul style="list-style-type: square;">
-<li>Add HardFault_IRQn.</li>
-<li>Add BKP5R to BKP19R for RTC_TypeDef for
-stm32l151xba.</li>
-<li>Align bits naming on all stm32 families (ex:
-WWDG_CFR_WDGTB0 -> WWDG_CFR_WDGTB_0).</li>
-<li>Rename RCC_CFGR_MCO_DIVx to RCC_CFGR_MCOPRE_DIVx</li>
-<li>Align Bits naming on all stm32 families (ex:
-EXTI_IMR_MR0 --> EXTI_IMR_IM0)</li>
-<li>Update .icf file to correct empty linker ROM
-Start/End menu, under IAR, for stm32l151xdx, stm32l152xdx and
-stm32l162xdx.</li>
-<li>Rename RCC_CFGR_MCO_x to RCC_CFGR_MCOSEL_x to
-be aligned with Reference Manual.</li>
-<li>Update CMSIS drivers to apply MISRA C 2004 rule
-10.6. (Use U postfix)</li>
-<li>Add defines FLASHSIZE_BASE and UID_BASE</li>
-<li>ADC common instance standardization (new define
-ADC1_COMMON)</li>
-<li>Remove bit GPIO_BRR_BR_x from Cat1 to Cat2
-devices</li>
-<li>Literals "ADC_SMPR1_SMP27, ADC_SMPR1_SMP28,
-ADC_SMPR1_SMP29" are available on Cat4, Cat5 only.</li>
-<li>Add DMA_CNDTR_NDT, DMA_CPAR_PA and
-DMA_CMAR_MA definitions present on other stm32 families.</li>
-<li>Add defines to trig feature inside source code
-based on CMSIS content:</li>
-<ul>
-<li>RTC_TAMPER1_SUPPORT</li>
-<li>RTC_TAMPER2_SUPPORT</li>
-<li>RTC_TAMPER3_SUPPORT</li>
-<li>RTC_BACKUP_SUPPORT</li>
-<li>RTC_WAKEUP_SUPPORT</li>
-<li>RTC_SMOOTHCALIB_SUPPORT</li>
-<li>RTC_SUBSECOND_SUPPORT. </li>
-</ul>
-<ul>
-<li>PWR_PVD_SUPPORT</li>
-</ul>
-<li>Set CMSIS variables PLLMulTable, AHBPrescTable
-and APBPrescTable as external in system_stm32l1xx.h.</li>
-<li>Bit 23 of all EXTI registers (IMR, EMR, ...) is
-not supported on Cat 1 & 2.</li>
-<li>Correct a wrong values for RI_ASCR1_CH_27 to
-RI_ASCR1_CH_30</li>
-<li>Add defines for LCD capacitance</li>
-<li>Suppress SPI1 from I2S_ALL_INSTANCE</li>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.2
-/ 09-October-2015 <o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-</p>
-<ul style="list-style-type: square;">
-<li>Removing the __IO attribute for PLLMulTable and
-AHBPrescTable. This was leading to issue during C++ initialisation.</li>
-<li>IDR field of CRC_TypeDef changed from uint32_t
-to uint8_t to comply with register structure.</li>
-<li><span style="font-size: 10pt; font-family: Verdana;">Added TIM10
-and TIM11 to IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE).</span></li>
-<li><span style="font-size: 10pt; font-family: Verdana;">Renaming
-USB_CNTR_LP_MODE to USB_CNTR_LPMODE for naming consistancy with other
-bits.</span></li>
-<li><span style="font-size: 10pt; font-family: Verdana;">Renaming
-USB_ISTR_PMAOVRM to USB_ISTR_PMAOVR to use the name of the bit in this
-register.<br>
-</span></li>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.1
-/ 31-March-2015 <o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-</p>
-<ul style="list-style-type: square;">
-<li><span style="font-size: 10pt; font-family: Verdana;">Ensure
-compliancy w/ C++</span></li>
-<li><span style="font-size: 10pt; font-family: Verdana;">Minor update
-on Timer assert.</span></li>
-<li><span style="font-size: 10pt; font-family: Verdana;">Adding
-IS_AES_ALL_INSTANCE macro for product with AES.</span></li>
-</ul>
-<span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.0
-/ 16-January-2015 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
-CMSIS files for new STM32L1 e<span style="font-weight: bold;">X</span>tended
-Devices : <span style="font-weight: bold;">STM32L151xDX</span>,
-<span style="font-weight: bold;">STM32L152xDX</span>
-& <span style="font-weight: bold;">STM32L162xDX</span></span></li></ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0
-/ 05-September-2014 <o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<ul style="list-style-type: square;">
-<li><span style="font-size: 10pt; font-family: Verdana;">Update
-based on STM32Cube specification<br>
-</span></li>
-<li style="font-weight: bold;"><span style="font-size: 10pt; font-family: Verdana;">This version
-has to be used only with </span><span style="font-size: 10pt; font-family: Verdana;">STM32CubeF4</span><span style="font-size: 10pt; font-family: Verdana;"> based
-development</span></li>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.1
-/ 06-March-2014<o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span><span style="font-size: 10pt; font-family: Verdana;">: update RAM
-functions attribute definition for GNU compiler</span></li>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0
-/ 31-January-2014<o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support
-for <span style="font-weight: bold; font-style: italic;">STM32L1xx
-XL-density</span> devices </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">"Ultra Low Power XL-density
-devices: STM32L151x<span style="font-weight: bold;">E</span>xx,
-STM32L152x<span style="font-weight: bold;">E</span>xx
-and STM32L162x<span style="font-weight: bold;">E</span>xx"</span></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new
-startup file <span style="font-style: italic;">startup_stm32l1xx_xl.s</span>
-for all toolchains</span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span></li>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new macro
-<span style="font-style: italic;">STM32L1XX_XL</span>
-for XL-density devices<span style="font-style: italic;"></span></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">IRQn</span> enumeration
-for <span style="font-style: italic;">STM32L1XX_XL</span></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">GPIO BRR
-register is declared only for STM32L1XX_HD and STM32L1XX_XL devices</span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All devices </span><span style="font-size: 10pt; font-family: Verdana;">definition </span><span style="font-size: 10pt; font-family: Verdana;">(i.e.
-STM32L1XX_xx) are commented out, user need to define the right
-STM32L1xx device in the toolchain compiler preprocessor</span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Extend <span style="font-style: italic;">HSE_STARTUP_TIMEOUT</span>
-and <span style="font-style: italic;">HSI_STARTUP_TIMEOUT</span>
-values to 0x5000</span></li>
-</ul>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1
-/ 19-June-2013<o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span></li>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">RI_TypeDef</span>
-structure by adding registers <span style="font-style: italic;">RI_ASMRx</span>,
-<span style="font-style: italic;">RI_CMRx</span>
-and <span style="font-style: italic;">RI_CICRx</span>
-(x=1..5)</span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add bits
-definition for </span><span style="font-size: 10pt; font-family: Verdana;">registers <span style="font-style: italic;">RI_ASMRx</span>, <span style="font-style: italic;">RI_CMRx</span> and <span style="font-style: italic;">RI_CICRx</span> (x=1..5)</span></li>
-</ul>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0
-/ 22-February-2013<o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span></li>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">List of
-supported devices: add reference to <span style="font-weight: bold; font-style: italic;">STM32L100xx
-Ultra Low Power Value Line devices</span></span></li>
-</ul>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add <span style="font-style: italic;">SPRMOD</span> bit
-definition in <span style="font-style: italic;">FLASH_OBR</span>
-register</span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add <span style="font-style: italic;">RDERR</span> bit
-definition in <span style="font-style: italic;">FLASH_SR</span>
-register</span></li>
-</ul>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">FLASH_OBR_nRST_BFB2</span>
-to <span style="font-style: italic;">FLASH_OBR_BFB2</span></span></li>
-</ul>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Delete <span style="font-style: italic;">FLASH_OBR_USER</span>
-define (useless)<br>
-</span></li>
-</ul>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1
-/ 05-March-2012<o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source
-files: license disclaimer text update and add link to the
-License file on ST Internet.</span></li>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 191px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0
-/ 24-January-2012<o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Alpha version
-for <span style="font-weight: bold; font-style: italic;">STM32L1xx
-High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density
-Plus</span> devices.</span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support
-for </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32L1xx
-High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density
-Plus</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices:</span></li>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new
-product define: "#define STM32L1XX_MDP"</span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new
-product define: "#define STM32L1XX_HD"</span></li>
-</ul>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the
-library version to V1.1.0<br>
-</span></li>
-</ul>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new IRQ
-to support STM32L1XX_HD and </span><span style="font-size: 10pt; font-family: Verdana;">STM32L1XX_MDP
-</span><span style="font-size: 10pt; font-family: Verdana;">vector table</span></li>
-</ul>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new and
-update some Typedef to support new peripherals (AES, SDIO, OPAMP, FSMC,
-I2S)</span></li>
-</ul>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new
-peripherals address mapping</span></li>
-</ul>
-<ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update bits
-definition</span></li>
-</ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new
-startup file "<span style="font-weight: bold; font-style: italic;">startup_stm32l1xx_mdp.s</span>"
-for all toolchains</span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new
-startup file "<span style="font-weight: bold; font-style: italic;">startup_stm32l1xx_hd.s</span>"
-for all toolchains</span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the
-RTC "<span style="font-weight: bold; font-style: italic;">CAL</span>"
-register name to "<span style="font-weight: bold; font-style: italic;">CALR</span>"</span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update
-registers bits definitions.</span><span style="color: black;"><o:p>
-</o:p></span><br>
-</li>
-</ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
-/ 31-December-2010<o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Created</span></li>
-</ul>
-<span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><br>
-<span style="font-size: 10pt; font-family: Verdana;"></span>
-<ul style="margin-top: 0cm;" type="square">
-</ul>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:</span><br>
- </font>
- <ol><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
-in binary form must reproduce the above copyright notice, this list of
-conditions and the following disclaimer in </span><span style="font-family: "Verdana","sans-serif";">the documentation and/or other materials provided with the distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither
-the name of STMicroelectronics nor the names of its contributors may be
-used to endorse or promote products derived from this software without
-specific prior written permission.</span></font><span style="font-family: "Verdana","sans-serif";"></span><br></li></ol><font size="-1">
- <span style="font-family: "Verdana","sans-serif";"></span><br>
- <span style="font-family: "Verdana","sans-serif";">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
-
- </div>
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%"></span></div>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers
-visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="color: black;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p> </o:p></p>
-</div>
-</body></html>
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l100xb.s b/Source/Templates/arm/startup_stm32l100xb.s
index 2e8e3bd..e5f2c4f 100644
--- a/Source/Templates/arm/startup_stm32l100xb.s
+++ b/Source/Templates/arm/startup_stm32l100xb.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -311,4 +312,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l100xba.s b/Source/Templates/arm/startup_stm32l100xba.s
index 534cc98..f0db1cb 100644
--- a/Source/Templates/arm/startup_stm32l100xba.s
+++ b/Source/Templates/arm/startup_stm32l100xba.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -311,4 +312,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l100xc.s b/Source/Templates/arm/startup_stm32l100xc.s
index 202148b..9cf18f3 100644
--- a/Source/Templates/arm/startup_stm32l100xc.s
+++ b/Source/Templates/arm/startup_stm32l100xc.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -337,4 +338,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l151xb.s b/Source/Templates/arm/startup_stm32l151xb.s
index 38dec85..49967b0 100644
--- a/Source/Templates/arm/startup_stm32l151xb.s
+++ b/Source/Templates/arm/startup_stm32l151xb.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -309,4 +310,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l151xba.s b/Source/Templates/arm/startup_stm32l151xba.s
index 4d33c5c..ba4bdff 100644
--- a/Source/Templates/arm/startup_stm32l151xba.s
+++ b/Source/Templates/arm/startup_stm32l151xba.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -309,4 +310,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l151xc.s b/Source/Templates/arm/startup_stm32l151xc.s
index b8baae4..faae5eb 100644
--- a/Source/Templates/arm/startup_stm32l151xc.s
+++ b/Source/Templates/arm/startup_stm32l151xc.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -337,4 +338,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l151xca.s b/Source/Templates/arm/startup_stm32l151xca.s
index b65fef4..38005bc 100644
--- a/Source/Templates/arm/startup_stm32l151xca.s
+++ b/Source/Templates/arm/startup_stm32l151xca.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -337,4 +338,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l151xd.s b/Source/Templates/arm/startup_stm32l151xd.s
index e5fdc6f..3f6effa 100644
--- a/Source/Templates/arm/startup_stm32l151xd.s
+++ b/Source/Templates/arm/startup_stm32l151xd.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -343,4 +344,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l151xdx.s b/Source/Templates/arm/startup_stm32l151xdx.s
index f463bef..ea171be 100644
--- a/Source/Templates/arm/startup_stm32l151xdx.s
+++ b/Source/Templates/arm/startup_stm32l151xdx.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -341,4 +342,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l151xe.s b/Source/Templates/arm/startup_stm32l151xe.s
index 382be8c..a66ee82 100644
--- a/Source/Templates/arm/startup_stm32l151xe.s
+++ b/Source/Templates/arm/startup_stm32l151xe.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -341,4 +342,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l152xb.s b/Source/Templates/arm/startup_stm32l152xb.s
index 46d1f41..904d52f 100644
--- a/Source/Templates/arm/startup_stm32l152xb.s
+++ b/Source/Templates/arm/startup_stm32l152xb.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -311,4 +312,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l152xba.s b/Source/Templates/arm/startup_stm32l152xba.s
index 09b9286..273ead4 100644
--- a/Source/Templates/arm/startup_stm32l152xba.s
+++ b/Source/Templates/arm/startup_stm32l152xba.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -311,4 +312,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l152xc.s b/Source/Templates/arm/startup_stm32l152xc.s
index 22570aa..aceb2e9 100644
--- a/Source/Templates/arm/startup_stm32l152xc.s
+++ b/Source/Templates/arm/startup_stm32l152xc.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -338,4 +339,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l152xca.s b/Source/Templates/arm/startup_stm32l152xca.s
index f6fa497..2773113 100644
--- a/Source/Templates/arm/startup_stm32l152xca.s
+++ b/Source/Templates/arm/startup_stm32l152xca.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -339,4 +340,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l152xd.s b/Source/Templates/arm/startup_stm32l152xd.s
index 57e537a..0de3227 100644
--- a/Source/Templates/arm/startup_stm32l152xd.s
+++ b/Source/Templates/arm/startup_stm32l152xd.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -345,4 +346,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l152xdx.s b/Source/Templates/arm/startup_stm32l152xdx.s
index 5927660..807c64d 100644
--- a/Source/Templates/arm/startup_stm32l152xdx.s
+++ b/Source/Templates/arm/startup_stm32l152xdx.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -343,4 +344,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l152xe.s b/Source/Templates/arm/startup_stm32l152xe.s
index 8748e8b..5906963 100644
--- a/Source/Templates/arm/startup_stm32l152xe.s
+++ b/Source/Templates/arm/startup_stm32l152xe.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file -comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -343,4 +344,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l162xc.s b/Source/Templates/arm/startup_stm32l162xc.s
index dd5b5d2..bb7696e 100644
--- a/Source/Templates/arm/startup_stm32l162xc.s
+++ b/Source/Templates/arm/startup_stm32l162xc.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -341,4 +342,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l162xca.s b/Source/Templates/arm/startup_stm32l162xca.s
index 1001812..f38960d 100644
--- a/Source/Templates/arm/startup_stm32l162xca.s
+++ b/Source/Templates/arm/startup_stm32l162xca.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -341,4 +342,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l162xd.s b/Source/Templates/arm/startup_stm32l162xd.s
index cf5c277..83ccfd4 100644
--- a/Source/Templates/arm/startup_stm32l162xd.s
+++ b/Source/Templates/arm/startup_stm32l162xd.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -347,4 +348,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l162xdx.s b/Source/Templates/arm/startup_stm32l162xdx.s
index 4d5e128..6e3614a 100644
--- a/Source/Templates/arm/startup_stm32l162xdx.s
+++ b/Source/Templates/arm/startup_stm32l162xdx.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -345,4 +346,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l162xe.s b/Source/Templates/arm/startup_stm32l162xe.s
index 7f17445..a23ada2 100644
--- a/Source/Templates/arm/startup_stm32l162xe.s
+++ b/Source/Templates/arm/startup_stm32l162xe.s
@@ -12,16 +12,17 @@
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
+;******************************************************************************
+;* @attention
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
-;*******************************************************************************
+;******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
@@ -345,4 +346,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/gcc/startup_stm32l100xb.s b/Source/Templates/gcc/startup_stm32l100xb.s
index 3e93a42..0a857e9 100644
--- a/Source/Templates/gcc/startup_stm32l100xb.s
+++ b/Source/Templates/gcc/startup_stm32l100xb.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -378,5 +379,5 @@
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l100xba.s b/Source/Templates/gcc/startup_stm32l100xba.s
index bba696e..af5fa5f 100644
--- a/Source/Templates/gcc/startup_stm32l100xba.s
+++ b/Source/Templates/gcc/startup_stm32l100xba.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -378,5 +379,5 @@
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l100xc.s b/Source/Templates/gcc/startup_stm32l100xc.s
index 82fdaaf..20f6c04 100644
--- a/Source/Templates/gcc/startup_stm32l100xc.s
+++ b/Source/Templates/gcc/startup_stm32l100xc.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,9 @@
.type Reset_Handler, %function
Reset_Handler:
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +94,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -399,5 +399,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l151xb.s b/Source/Templates/gcc/startup_stm32l151xb.s
index e6671c4..2fe1a6a 100644
--- a/Source/Templates/gcc/startup_stm32l151xb.s
+++ b/Source/Templates/gcc/startup_stm32l151xb.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -375,5 +376,5 @@
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l151xba.s b/Source/Templates/gcc/startup_stm32l151xba.s
index 2610867..35b6bd4 100644
--- a/Source/Templates/gcc/startup_stm32l151xba.s
+++ b/Source/Templates/gcc/startup_stm32l151xba.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -375,5 +376,5 @@
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l151xc.s b/Source/Templates/gcc/startup_stm32l151xc.s
index 3f14248..5bd0811 100644
--- a/Source/Templates/gcc/startup_stm32l151xc.s
+++ b/Source/Templates/gcc/startup_stm32l151xc.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -399,5 +400,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l151xca.s b/Source/Templates/gcc/startup_stm32l151xca.s
index 81da7a7..1095b20 100644
--- a/Source/Templates/gcc/startup_stm32l151xca.s
+++ b/Source/Templates/gcc/startup_stm32l151xca.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -399,5 +400,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l151xd.s b/Source/Templates/gcc/startup_stm32l151xd.s
index fb105c7..1eaa194 100644
--- a/Source/Templates/gcc/startup_stm32l151xd.s
+++ b/Source/Templates/gcc/startup_stm32l151xd.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,9 @@
.type Reset_Handler, %function
Reset_Handler:
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +94,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -408,5 +408,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l151xdx.s b/Source/Templates/gcc/startup_stm32l151xdx.s
index 58c9ddf..eb24614 100644
--- a/Source/Templates/gcc/startup_stm32l151xdx.s
+++ b/Source/Templates/gcc/startup_stm32l151xdx.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -405,5 +406,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l151xe.s b/Source/Templates/gcc/startup_stm32l151xe.s
index cb7ca7f..1db6ef8 100644
--- a/Source/Templates/gcc/startup_stm32l151xe.s
+++ b/Source/Templates/gcc/startup_stm32l151xe.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,9 @@
.type Reset_Handler, %function
Reset_Handler:
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +94,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -405,5 +405,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l152xb.s b/Source/Templates/gcc/startup_stm32l152xb.s
index 75d70aa..343a42c 100644
--- a/Source/Templates/gcc/startup_stm32l152xb.s
+++ b/Source/Templates/gcc/startup_stm32l152xb.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -378,5 +379,5 @@
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l152xba.s b/Source/Templates/gcc/startup_stm32l152xba.s
index e9636b5..f35ef03 100644
--- a/Source/Templates/gcc/startup_stm32l152xba.s
+++ b/Source/Templates/gcc/startup_stm32l152xba.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -378,5 +379,5 @@
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l152xc.s b/Source/Templates/gcc/startup_stm32l152xc.s
index 9ff967a..29abf1a 100644
--- a/Source/Templates/gcc/startup_stm32l152xc.s
+++ b/Source/Templates/gcc/startup_stm32l152xc.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -402,5 +403,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l152xca.s b/Source/Templates/gcc/startup_stm32l152xca.s
index 49f8c29..000b95f 100644
--- a/Source/Templates/gcc/startup_stm32l152xca.s
+++ b/Source/Templates/gcc/startup_stm32l152xca.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -402,5 +403,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l152xd.s b/Source/Templates/gcc/startup_stm32l152xd.s
index 5ec40ed..e26b898 100644
--- a/Source/Templates/gcc/startup_stm32l152xd.s
+++ b/Source/Templates/gcc/startup_stm32l152xd.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -411,5 +412,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l152xdx.s b/Source/Templates/gcc/startup_stm32l152xdx.s
index ab001d6..8b229bb 100644
--- a/Source/Templates/gcc/startup_stm32l152xdx.s
+++ b/Source/Templates/gcc/startup_stm32l152xdx.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -408,5 +409,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l152xe.s b/Source/Templates/gcc/startup_stm32l152xe.s
index 6b9b75a..d3dd841 100644
--- a/Source/Templates/gcc/startup_stm32l152xe.s
+++ b/Source/Templates/gcc/startup_stm32l152xe.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -408,5 +409,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l162xc.s b/Source/Templates/gcc/startup_stm32l162xc.s
index aabd5d3..e2e9bd0 100644
--- a/Source/Templates/gcc/startup_stm32l162xc.s
+++ b/Source/Templates/gcc/startup_stm32l162xc.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -405,5 +406,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l162xca.s b/Source/Templates/gcc/startup_stm32l162xca.s
index 8013eab..78a5cc3 100644
--- a/Source/Templates/gcc/startup_stm32l162xca.s
+++ b/Source/Templates/gcc/startup_stm32l162xca.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -405,5 +406,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l162xd.s b/Source/Templates/gcc/startup_stm32l162xd.s
index ef8188b..2f5fb61 100644
--- a/Source/Templates/gcc/startup_stm32l162xd.s
+++ b/Source/Templates/gcc/startup_stm32l162xd.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -414,5 +415,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l162xdx.s b/Source/Templates/gcc/startup_stm32l162xdx.s
index 47e0939..d2814fe 100644
--- a/Source/Templates/gcc/startup_stm32l162xdx.s
+++ b/Source/Templates/gcc/startup_stm32l162xdx.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -411,5 +412,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l162xe.s b/Source/Templates/gcc/startup_stm32l162xe.s
index 72ad12f..8cbf96e 100644
--- a/Source/Templates/gcc/startup_stm32l162xe.s
+++ b/Source/Templates/gcc/startup_stm32l162xe.s
@@ -13,15 +13,14 @@
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
- *
* @attention
*
- * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -61,6 +60,10 @@
.type Reset_Handler, %function
Reset_Handler:
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
@@ -92,8 +95,6 @@
cmp r2, r4
bcc FillZerobss
-/* Call the clock system intitialization function.*/
- bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@@ -411,5 +412,5 @@
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l100xb.s b/Source/Templates/iar/startup_stm32l100xb.s
index f4e7c0b..55f839f 100644
--- a/Source/Templates/iar/startup_stm32l100xb.s
+++ b/Source/Templates/iar/startup_stm32l100xb.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -457,4 +455,4 @@
B TIM7_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l100xba.s b/Source/Templates/iar/startup_stm32l100xba.s
index 51ad5ab..797e79d 100644
--- a/Source/Templates/iar/startup_stm32l100xba.s
+++ b/Source/Templates/iar/startup_stm32l100xba.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -457,4 +455,4 @@
B TIM7_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l100xc.s b/Source/Templates/iar/startup_stm32l100xc.s
index 28d70e7..87ff88a 100644
--- a/Source/Templates/iar/startup_stm32l100xc.s
+++ b/Source/Templates/iar/startup_stm32l100xc.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -510,4 +508,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l151xb.s b/Source/Templates/iar/startup_stm32l151xb.s
index 8e8604b..87dbeb6 100644
--- a/Source/Templates/iar/startup_stm32l151xb.s
+++ b/Source/Templates/iar/startup_stm32l151xb.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -451,4 +449,4 @@
B TIM7_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l151xba.s b/Source/Templates/iar/startup_stm32l151xba.s
index 87947a5..fb6f3e1 100644
--- a/Source/Templates/iar/startup_stm32l151xba.s
+++ b/Source/Templates/iar/startup_stm32l151xba.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -451,4 +449,4 @@
B TIM7_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l151xc.s b/Source/Templates/iar/startup_stm32l151xc.s
index fb0139d..9a70e4f 100644
--- a/Source/Templates/iar/startup_stm32l151xc.s
+++ b/Source/Templates/iar/startup_stm32l151xc.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -510,4 +508,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l151xca.s b/Source/Templates/iar/startup_stm32l151xca.s
index 3506dac..5deeeaf 100644
--- a/Source/Templates/iar/startup_stm32l151xca.s
+++ b/Source/Templates/iar/startup_stm32l151xca.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -509,4 +507,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l151xd.s b/Source/Templates/iar/startup_stm32l151xd.s
index 813a99b..6ab06b4 100644
--- a/Source/Templates/iar/startup_stm32l151xd.s
+++ b/Source/Templates/iar/startup_stm32l151xd.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -526,4 +524,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l151xdx.s b/Source/Templates/iar/startup_stm32l151xdx.s
index 52723f8..419eda2 100644
--- a/Source/Templates/iar/startup_stm32l151xdx.s
+++ b/Source/Templates/iar/startup_stm32l151xdx.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -521,4 +519,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l151xe.s b/Source/Templates/iar/startup_stm32l151xe.s
index a5f4fff..68eea71 100644
--- a/Source/Templates/iar/startup_stm32l151xe.s
+++ b/Source/Templates/iar/startup_stm32l151xe.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -521,4 +519,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l152xb.s b/Source/Templates/iar/startup_stm32l152xb.s
index 84dbd23..aa55b94 100644
--- a/Source/Templates/iar/startup_stm32l152xb.s
+++ b/Source/Templates/iar/startup_stm32l152xb.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -457,4 +455,4 @@
B TIM7_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l152xba.s b/Source/Templates/iar/startup_stm32l152xba.s
index 73224c2..efb91a0 100644
--- a/Source/Templates/iar/startup_stm32l152xba.s
+++ b/Source/Templates/iar/startup_stm32l152xba.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -457,4 +455,4 @@
B TIM7_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l152xc.s b/Source/Templates/iar/startup_stm32l152xc.s
index f2aa3f8..a4935eb 100644
--- a/Source/Templates/iar/startup_stm32l152xc.s
+++ b/Source/Templates/iar/startup_stm32l152xc.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -516,4 +514,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l152xca.s b/Source/Templates/iar/startup_stm32l152xca.s
index 3a47617..afa9408 100644
--- a/Source/Templates/iar/startup_stm32l152xca.s
+++ b/Source/Templates/iar/startup_stm32l152xca.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -516,4 +514,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l152xd.s b/Source/Templates/iar/startup_stm32l152xd.s
index 904ea76..4c5af27 100644
--- a/Source/Templates/iar/startup_stm32l152xd.s
+++ b/Source/Templates/iar/startup_stm32l152xd.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -532,4 +530,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l152xdx.s b/Source/Templates/iar/startup_stm32l152xdx.s
index f70889c..7ba7d57 100644
--- a/Source/Templates/iar/startup_stm32l152xdx.s
+++ b/Source/Templates/iar/startup_stm32l152xdx.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -526,4 +524,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l152xe.s b/Source/Templates/iar/startup_stm32l152xe.s
index 382e893..322f941 100644
--- a/Source/Templates/iar/startup_stm32l152xe.s
+++ b/Source/Templates/iar/startup_stm32l152xe.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -526,4 +524,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l162xc.s b/Source/Templates/iar/startup_stm32l162xc.s
index c84379e..84340ca 100644
--- a/Source/Templates/iar/startup_stm32l162xc.s
+++ b/Source/Templates/iar/startup_stm32l162xc.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -522,4 +520,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l162xca.s b/Source/Templates/iar/startup_stm32l162xca.s
index 55bb30e..50eed29 100644
--- a/Source/Templates/iar/startup_stm32l162xca.s
+++ b/Source/Templates/iar/startup_stm32l162xca.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -521,4 +519,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l162xd.s b/Source/Templates/iar/startup_stm32l162xd.s
index 7c0508b..cb336c6 100644
--- a/Source/Templates/iar/startup_stm32l162xd.s
+++ b/Source/Templates/iar/startup_stm32l162xd.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -538,4 +536,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l162xdx.s b/Source/Templates/iar/startup_stm32l162xdx.s
index c6f212e..47b7452 100644
--- a/Source/Templates/iar/startup_stm32l162xdx.s
+++ b/Source/Templates/iar/startup_stm32l162xdx.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017-2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -532,4 +530,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l162xe.s b/Source/Templates/iar/startup_stm32l162xe.s
index bff971a..4522fbd 100644
--- a/Source/Templates/iar/startup_stm32l162xe.s
+++ b/Source/Templates/iar/startup_stm32l162xe.s
@@ -14,15 +14,13 @@
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
-;* @attention
+;* Copyright (c) 2017(2021 STMicroelectronics.
+;* All rights reserved.
;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -532,4 +530,4 @@
B COMP_ACQ_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/system_stm32l1xx.c b/Source/Templates/system_stm32l1xx.c
index 42f02a1..b68e3de 100644
--- a/Source/Templates/system_stm32l1xx.c
+++ b/Source/Templates/system_stm32l1xx.c
@@ -21,13 +21,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -67,7 +66,7 @@
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000U) /*!< Default value of the Internal oscillator in Hz.
+ #define HSI_VALUE ((uint32_t)16000000U) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
@@ -424,4 +423,4 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/_htmresc/favicon.png b/_htmresc/favicon.png
new file mode 100644
index 0000000..06713ee
--- /dev/null
+++ b/_htmresc/favicon.png
Binary files differ
diff --git a/_htmresc/mini-st.css b/_htmresc/mini-st_2020.css
similarity index 77%
rename from _htmresc/mini-st.css
rename to _htmresc/mini-st_2020.css
index 71fbc14..3d9e81a 100644
--- a/_htmresc/mini-st.css
+++ b/_htmresc/mini-st_2020.css
@@ -1,39 +1,39 @@
@charset "UTF-8";
/*
- Flavor name: Default (mini-default)
- Author: Angelos Chalaris (chalarangelo@gmail.com)
- Maintainers: Angelos Chalaris
- mini.css version: v3.0.0-alpha.3
+ Flavor name: Custom (mini-custom)
+ Generated online - https://minicss.org/flavors
+ mini.css version: v3.0.1
*/
/*
Browsers resets and base typography.
*/
/* Core module CSS variable definitions */
:root {
- --fore-color: #111;
- --secondary-fore-color: #444;
- --back-color: #f8f8f8;
- --secondary-back-color: #f0f0f0;
- --blockquote-color: #f57c00;
- --pre-color: #1565c0;
- --border-color: #aaa;
- --secondary-border-color: #ddd;
- --heading-ratio: 1.19;
+ --fore-color: #03234b;
+ --secondary-fore-color: #03234b;
+ --back-color: #ffffff;
+ --secondary-back-color: #ffffff;
+ --blockquote-color: #e6007e;
+ --pre-color: #e6007e;
+ --border-color: #3cb4e6;
+ --secondary-border-color: #3cb4e6;
+ --heading-ratio: 1.2;
--universal-margin: 0.5rem;
- --universal-padding: 0.125rem;
- --universal-border-radius: 0.125rem;
- --a-link-color: #0277bd;
- --a-visited-color: #01579b; }
+ --universal-padding: 0.25rem;
+ --universal-border-radius: 0.075rem;
+ --background-margin: 1.5%;
+ --a-link-color: #3cb4e6;
+ --a-visited-color: #8c0078; }
html {
- font-size: 14px; }
+ font-size: 13.5px; }
a, b, del, em, i, ins, q, span, strong, u {
font-size: 1em; }
html, * {
- font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif;
- line-height: 1.4;
+ font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif;
+ line-height: 1.25;
-webkit-text-size-adjust: 100%; }
* {
@@ -42,7 +42,10 @@
body {
margin: 0;
color: var(--fore-color);
- background: var(--back-color); }
+ @background: var(--back-color);
+ background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top;
+ background-size: var(--background-margin);
+ }
details {
display: block; }
@@ -62,9 +65,9 @@
height: auto; }
h1, h2, h3, h4, h5, h6 {
- line-height: 1.2;
+ line-height: 1.25;
margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
- font-weight: 500; }
+ font-weight: 400; }
h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
color: var(--secondary-fore-color);
display: block;
@@ -74,21 +77,15 @@
font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
h2 {
- font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); );
- background: var(--mark-back-color);
- font-weight: 600;
- padding: 0.1em 0.5em 0.2em 0.5em;
- color: var(--mark-fore-color); }
-
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) );
+ border-style: none none solid none ;
+ border-width: thin;
+ border-color: var(--border-color); }
h3 {
- font-size: calc(1rem * var(--heading-ratio));
- padding-left: calc(2 * var(--universal-margin));
- /* background: var(--border-color); */
- }
+ font-size: calc(1rem * var(--heading-ratio) ); }
h4 {
- font-size: 1rem;);
- padding-left: calc(4 * var(--universal-margin)); }
+ font-size: calc(1rem * var(--heading-ratio)); }
h5 {
font-size: 1rem; }
@@ -101,7 +98,7 @@
ol, ul {
margin: var(--universal-margin);
- padding-left: calc(6 * var(--universal-margin)); }
+ padding-left: calc(3 * var(--universal-margin)); }
b, strong {
font-weight: 700; }
@@ -111,7 +108,7 @@
border: 0;
line-height: 1.25em;
margin: var(--universal-margin);
- height: 0.0625rem;
+ height: 0.0714285714rem;
background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
blockquote {
@@ -121,16 +118,16 @@
color: var(--secondary-fore-color);
margin: var(--universal-margin);
padding: calc(3 * var(--universal-padding));
- border: 0.0625rem solid var(--secondary-border-color);
- border-left: 0.375rem solid var(--blockquote-color);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.3rem solid var(--blockquote-color);
border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
blockquote:before {
position: absolute;
top: calc(0rem - var(--universal-padding));
left: 0;
font-family: sans-serif;
- font-size: 3rem;
- font-weight: 700;
+ font-size: 2rem;
+ font-weight: 800;
content: "\201c";
color: var(--blockquote-color); }
blockquote[cite]:after {
@@ -160,8 +157,8 @@
background: var(--secondary-back-color);
padding: calc(1.5 * var(--universal-padding));
margin: var(--universal-margin);
- border: 0.0625rem solid var(--secondary-border-color);
- border-left: 0.25rem solid var(--pre-color);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.2857142857rem solid var(--pre-color);
border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
sup, sub, code, kbd {
@@ -204,7 +201,8 @@
box-sizing: border-box;
display: flex;
flex: 0 1 auto;
- flex-flow: row wrap; }
+ flex-flow: row wrap;
+ margin: 0 0 0 var(--background-margin); }
.col-sm,
[class^='col-sm-'],
@@ -565,9 +563,9 @@
order: 999; } }
/* Card component CSS variable definitions */
:root {
- --card-back-color: #f8f8f8;
- --card-fore-color: #111;
- --card-border-color: #ddd; }
+ --card-back-color: #3cb4e6;
+ --card-fore-color: #03234b;
+ --card-border-color: #03234b; }
.card {
display: flex;
@@ -578,7 +576,7 @@
width: 100%;
background: var(--card-back-color);
color: var(--card-fore-color);
- border: 0.0625rem solid var(--card-border-color);
+ border: 0.0714285714rem solid var(--card-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
overflow: hidden; }
@@ -592,7 +590,7 @@
margin: 0;
border: 0;
border-radius: 0;
- border-bottom: 0.0625rem solid var(--card-border-color);
+ border-bottom: 0.0714285714rem solid var(--card-border-color);
padding: var(--universal-padding);
width: 100%; }
.card > .sectione.media {
@@ -617,17 +615,18 @@
width: auto; }
.card.warning {
-/* --card-back-color: #ffca28; */
--card-back-color: #e5b8b7;
- --card-border-color: #e8b825; }
+ --card-fore-color: #3b234b;
+ --card-border-color: #8c0078; }
.card.error {
- --card-back-color: #b71c1c;
- --card-fore-color: #f8f8f8;
- --card-border-color: #a71a1a; }
+ --card-back-color: #464650;
+ --card-fore-color: #ffffff;
+ --card-border-color: #8c0078; }
.card > .sectione.dark {
- --card-back-color: #e0e0e0; }
+ --card-back-color: #3b234b;
+ --card-fore-color: #ffffff; }
.card > .sectione.double-padded {
padding: calc(1.5 * var(--universal-padding)); }
@@ -637,12 +636,12 @@
*/
/* Input_control module CSS variable definitions */
:root {
- --form-back-color: #f0f0f0;
- --form-fore-color: #111;
- --form-border-color: #ddd;
- --input-back-color: #f8f8f8;
- --input-fore-color: #111;
- --input-border-color: #ddd;
+ --form-back-color: #ffe97f;
+ --form-fore-color: #03234b;
+ --form-border-color: #3cb4e6;
+ --input-back-color: #ffffff;
+ --input-fore-color: #03234b;
+ --input-border-color: #3cb4e6;
--input-focus-color: #0288d1;
--input-invalid-color: #d32f2f;
--button-back-color: #e2e2e2;
@@ -655,13 +654,13 @@
form {
background: var(--form-back-color);
color: var(--form-fore-color);
- border: 0.0625rem solid var(--form-border-color);
+ border: 0.0714285714rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
fieldset {
- border: 0.0625rem solid var(--form-border-color);
+ border: 0.0714285714rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 4);
padding: var(--universal-padding); }
@@ -671,7 +670,7 @@
display: table;
max-width: 100%;
white-space: normal;
- font-weight: 700;
+ font-weight: 500;
padding: calc(var(--universal-padding) / 2); }
label {
@@ -716,7 +715,7 @@
box-sizing: border-box;
background: var(--input-back-color);
color: var(--input-fore-color);
- border: 0.0625rem solid var(--input-border-color);
+ border: 0.0714285714rem solid var(--input-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 2);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
@@ -763,8 +762,8 @@
[type="radio"]:checked:before {
border-radius: 100%;
content: '';
- top: calc(0.0625rem + var(--universal-padding) / 2);
- left: calc(0.0625rem + var(--universal-padding) / 2);
+ top: calc(0.0714285714rem + var(--universal-padding) / 2);
+ left: calc(0.0714285714rem + var(--universal-padding) / 2);
background: var(--input-fore-color);
width: 0.5rem;
height: 0.5rem; }
@@ -793,7 +792,7 @@
display: inline-block;
background: var(--button-back-color);
color: var(--button-fore-color);
- border: 0.0625rem solid var(--button-border-color);
+ border: 0.0714285714rem solid var(--button-border-color);
border-radius: var(--universal-border-radius);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
margin: var(--universal-margin);
@@ -814,7 +813,7 @@
.button-group {
display: flex;
- border: 0.0625rem solid var(--button-group-border-color);
+ border: 0.0714285714rem solid var(--button-group-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
.button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
@@ -826,13 +825,13 @@
border-radius: 0;
box-shadow: none; }
.button-group > :not(:first-child) {
- border-left: 0.0625rem solid var(--button-group-border-color); }
+ border-left: 0.0714285714rem solid var(--button-group-border-color); }
@media screen and (max-width: 499px) {
.button-group {
flex-direction: column; }
.button-group > :not(:first-child) {
border: 0;
- border-top: 0.0625rem solid var(--button-group-border-color); } }
+ border-top: 0.0714285714rem solid var(--button-group-border-color); } }
/*
Custom elements for forms and input elements.
@@ -874,29 +873,29 @@
*/
/* Navigation module CSS variable definitions */
:root {
- --header-back-color: #f8f8f8;
- --header-hover-back-color: #f0f0f0;
- --header-fore-color: #444;
- --header-border-color: #ddd;
- --nav-back-color: #f8f8f8;
- --nav-hover-back-color: #f0f0f0;
- --nav-fore-color: #444;
- --nav-border-color: #ddd;
- --nav-link-color: #0277bd;
- --footer-fore-color: #444;
- --footer-back-color: #f8f8f8;
- --footer-border-color: #ddd;
- --footer-link-color: #0277bd;
- --drawer-back-color: #f8f8f8;
- --drawer-hover-back-color: #f0f0f0;
- --drawer-border-color: #ddd;
- --drawer-close-color: #444; }
+ --header-back-color: #03234b;
+ --header-hover-back-color: #ffd200;
+ --header-fore-color: #ffffff;
+ --header-border-color: #3cb4e6;
+ --nav-back-color: #ffffff;
+ --nav-hover-back-color: #ffe97f;
+ --nav-fore-color: #e6007e;
+ --nav-border-color: #3cb4e6;
+ --nav-link-color: #3cb4e6;
+ --footer-fore-color: #ffffff;
+ --footer-back-color: #03234b;
+ --footer-border-color: #3cb4e6;
+ --footer-link-color: #3cb4e6;
+ --drawer-back-color: #ffffff;
+ --drawer-hover-back-color: #ffe97f;
+ --drawer-border-color: #3cb4e6;
+ --drawer-close-color: #e6007e; }
header {
- height: 3.1875rem;
+ height: 2.75rem;
background: var(--header-back-color);
color: var(--header-fore-color);
- border-bottom: 0.0625rem solid var(--header-border-color);
+ border-bottom: 0.0714285714rem solid var(--header-border-color);
padding: calc(var(--universal-padding) / 4) 0;
white-space: nowrap;
overflow-x: auto;
@@ -927,7 +926,7 @@
nav {
background: var(--nav-back-color);
color: var(--nav-fore-color);
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
nav * {
@@ -946,10 +945,10 @@
nav .sublink-1:before {
position: absolute;
left: calc(var(--universal-padding) - 1 * var(--universal-padding));
- top: -0.0625rem;
+ top: -0.0714285714rem;
content: '';
height: 100%;
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-left: 0; }
nav .sublink-2 {
position: relative;
@@ -957,16 +956,16 @@
nav .sublink-2:before {
position: absolute;
left: calc(var(--universal-padding) - 3 * var(--universal-padding));
- top: -0.0625rem;
+ top: -0.0714285714rem;
content: '';
height: 100%;
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-left: 0; }
footer {
background: var(--footer-back-color);
color: var(--footer-fore-color);
- border-top: 0.0625rem solid var(--footer-border-color);
+ border-top: 0.0714285714rem solid var(--footer-border-color);
padding: calc(2 * var(--universal-padding)) var(--universal-padding);
font-size: 0.875rem; }
footer a, footer a:visited {
@@ -1013,7 +1012,7 @@
height: 100vh;
overflow-y: auto;
background: var(--drawer-back-color);
- border: 0.0625rem solid var(--drawer-border-color);
+ border: 0.0714285714rem solid var(--drawer-border-color);
border-radius: 0;
margin: 0;
z-index: 1110;
@@ -1060,38 +1059,36 @@
*/
/* Table module CSS variable definitions. */
:root {
- --table-border-color: #aaa;
- --table-border-separator-color: #666;
- --table-head-back-color: #e6e6e6;
- --table-head-fore-color: #111;
- --table-body-back-color: #f8f8f8;
- --table-body-fore-color: #111;
- --table-body-alt-back-color: #eee; }
+ --table-border-color: #03234b;
+ --table-border-separator-color: #03234b;
+ --table-head-back-color: #03234b;
+ --table-head-fore-color: #ffffff;
+ --table-body-back-color: #ffffff;
+ --table-body-fore-color: #03234b;
+ --table-body-alt-back-color: #f4f4f4; }
table {
border-collapse: separate;
border-spacing: 0;
- : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ margin: 0;
display: flex;
flex: 0 1 auto;
flex-flow: row wrap;
padding: var(--universal-padding);
- padding-top: 0;
- margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); }
+ padding-top: 0; }
table caption {
- font-size: 1.25 * rem;
+ font-size: 1rem;
margin: calc(2 * var(--universal-margin)) 0;
max-width: 100%;
- flex: 0 0 100%;
- text-align: left;}
+ flex: 0 0 100%; }
table thead, table tbody {
display: flex;
flex-flow: row wrap;
- border: 0.0625rem solid var(--table-border-color); }
+ border: 0.0714285714rem solid var(--table-border-color); }
table thead {
z-index: 999;
border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
- border-bottom: 0.0625rem solid var(--table-border-separator-color); }
+ border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
table tbody {
border-top: 0;
margin-top: calc(0 - var(--universal-margin));
@@ -1109,11 +1106,11 @@
table td {
background: var(--table-body-back-color);
color: var(--table-body-fore-color);
- border-top: 0.0625rem solid var(--table-border-color); }
+ border-top: 0.0714285714rem solid var(--table-border-color); }
table:not(.horizontal) {
overflow: auto;
- max-height: 850px; }
+ max-height: 100%; }
table:not(.horizontal) thead, table:not(.horizontal) tbody {
max-width: 100%;
flex: 0 0 100%; }
@@ -1134,32 +1131,33 @@
border: 0; }
table.horizontal thead, table.horizontal tbody {
border: 0;
+ flex: .2 0 0;
flex-flow: row nowrap; }
table.horizontal tbody {
overflow: auto;
justify-content: space-between;
- flex: 1 0 0;
- margin-left: calc( 4 * var(--universal-margin));
+ flex: .8 0 0;
+ margin-left: 0;
padding-bottom: calc(var(--universal-padding) / 4); }
table.horizontal tr {
flex-direction: column;
flex: 1 0 auto; }
table.horizontal th, table.horizontal td {
- width: 100%;
+ width: auto;
border: 0;
- border-bottom: 0.0625rem solid var(--table-border-color); }
+ border-bottom: 0.0714285714rem solid var(--table-border-color); }
table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
border-top: 0; }
table.horizontal th {
text-align: right;
- border-left: 0.0625rem solid var(--table-border-color);
- border-right: 0.0625rem solid var(--table-border-separator-color); }
+ border-left: 0.0714285714rem solid var(--table-border-color);
+ border-right: 0.0714285714rem solid var(--table-border-separator-color); }
table.horizontal thead tr:first-child {
padding-left: 0; }
table.horizontal th:first-child, table.horizontal td:first-child {
- border-top: 0.0625rem solid var(--table-border-color); }
+ border-top: 0.0714285714rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td {
- border-right: 0.0625rem solid var(--table-border-color); }
+ border-right: 0.0714285714rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td:first-child {
border-top-right-radius: 0.25rem; }
table.horizontal tbody tr:last-child td:last-child {
@@ -1191,12 +1189,12 @@
display: table-row-group; }
table tr, table.horizontal tr {
display: block;
- border: 0.0625rem solid var(--table-border-color);
+ border: 0.0714285714rem solid var(--table-border-color);
border-radius: var(--universal-border-radius);
- background: #fafafa;
+ background: #ffffff;
padding: var(--universal-padding);
margin: var(--universal-margin);
- margin-bottom: calc(2 * var(--universal-margin)); }
+ margin-bottom: calc(1 * var(--universal-margin)); }
table th, table td, table.horizontal th, table.horizontal td {
width: auto; }
table td, table.horizontal td {
@@ -1211,9 +1209,6 @@
border-top: 0; }
table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
border-right: 0; } }
-:root {
- --table-body-alt-back-color: #eee; }
-
table tr:nth-of-type(2n) > td {
background: var(--table-body-alt-back-color); }
@@ -1234,8 +1229,8 @@
*/
/* Contextual module CSS variable definitions */
:root {
- --mark-back-color: #0277bd;
- --mark-fore-color: #fafafa; }
+ --mark-back-color: #3cb4e6;
+ --mark-fore-color: #ffffff; }
mark {
background: var(--mark-back-color);
@@ -1243,11 +1238,11 @@
font-size: 0.95em;
line-height: 1em;
border-radius: var(--universal-border-radius);
- padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+ padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
mark.inline-block {
display: inline-block;
font-size: 1em;
- line-height: 1.5;
+ line-height: 1.4;
padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
:root {
@@ -1314,8 +1309,8 @@
:root {
--modal-overlay-color: rgba(0, 0, 0, 0.45);
- --modal-close-color: #444;
- --modal-close-hover-color: #f0f0f0; }
+ --modal-close-color: #e6007e;
+ --modal-close-hover-color: #ffe97f; }
[type="checkbox"].modal {
height: 1px;
@@ -1368,13 +1363,14 @@
z-index: 1211; }
:root {
- --collapse-label-back-color: #e8e8e8;
- --collapse-label-fore-color: #212121;
- --collapse-label-hover-back-color: #f0f0f0;
- --collapse-selected-label-back-color: #ececec;
- --collapse-border-color: #ddd;
- --collapse-content-back-color: #fafafa;
- --collapse-selected-label-border-color: #0277bd; }
+ --collapse-label-back-color: #03234b;
+ --collapse-label-fore-color: #ffffff;
+ --collapse-label-hover-back-color: #3cb4e6;
+ --collapse-selected-label-back-color: #3cb4e6;
+ --collapse-border-color: var(--collapse-label-back-color);
+ --collapse-selected-border-color: #ceecf8;
+ --collapse-content-back-color: #ffffff;
+ --collapse-selected-label-border-color: #3cb4e6; }
.collapse {
width: calc(100% - 2 * var(--universal-margin));
@@ -1395,13 +1391,13 @@
.collapse > label {
flex-grow: 1;
display: inline-block;
- height: 1.5rem;
+ height: 1.25rem;
cursor: pointer;
- transition: background 0.3s;
+ transition: background 0.2s;
color: var(--collapse-label-fore-color);
background: var(--collapse-label-back-color);
- border: 0.0625rem solid var(--collapse-border-color);
- padding: calc(1.5 * var(--universal-padding)); }
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ padding: calc(1.25 * var(--universal-padding)); }
.collapse > label:hover, .collapse > label:focus {
background: var(--collapse-label-hover-back-color); }
.collapse > label + div {
@@ -1418,7 +1414,7 @@
max-height: 1px; }
.collapse > :checked + label {
background: var(--collapse-selected-label-back-color);
- border-bottom-color: var(--collapse-selected-label-border-color); }
+ border-color: var(--collapse-selected-label-border-color); }
.collapse > :checked + label + div {
box-sizing: border-box;
position: relative;
@@ -1427,13 +1423,13 @@
overflow: auto;
margin: 0;
background: var(--collapse-content-back-color);
- border: 0.0625rem solid var(--collapse-border-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
border-top: 0;
padding: var(--universal-padding);
clip: auto;
-webkit-clip-path: inset(0%);
clip-path: inset(0%);
- max-height: 850px; }
+ max-height: 100%; }
.collapse > label:not(:first-of-type) {
border-top: 0; }
.collapse > label:first-of-type {
@@ -1450,11 +1446,8 @@
/*
Custom elements for contextual background elements, toasts and tooltips.
*/
-mark.secondary {
- --mark-back-color: #d32f2f; }
-
mark.tertiary {
- --mark-back-color: #308732; }
+ --mark-back-color: #3cb4e6; }
mark.tag {
padding: calc(var(--universal-padding)/2) var(--universal-padding);
@@ -1463,9 +1456,9 @@
/*
Definitions for progress elements and spinners.
*/
-/* Progess module CSS variable definitions */
+/* Progress module CSS variable definitions */
:root {
- --progress-back-color: #ddd;
+ --progress-back-color: #3cb4e6;
--progress-fore-color: #555; }
progress {
@@ -1558,45 +1551,45 @@
filter: invert(100%); }
span.icon-alert {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-bookmark {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-calendar {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-credit {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-edit {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
span.icon-link {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-help {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-home {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-info {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-lock {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-mail {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-location {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-phone {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-rss {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-search {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-settings {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-share {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-cart {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-upload {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-user {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
/*
Definitions for utilities and helper classes.
@@ -1604,7 +1597,7 @@
/* Utility module CSS variable definitions */
:root {
--generic-border-color: rgba(0, 0, 0, 0.3);
- --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); }
+ --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); }
.hidden {
display: none !important; }
@@ -1622,7 +1615,7 @@
overflow: hidden !important; }
.bordered {
- border: 0.0625rem solid var(--generic-border-color) !important; }
+ border: 0.0714285714rem solid var(--generic-border-color) !important; }
.rounded {
border-radius: var(--universal-border-radius) !important; }
@@ -1697,4 +1690,14 @@
clip-path: inset(100%) !important;
overflow: hidden !important; } }
-/*# sourceMappingURL=mini-default.css.map */
+/*# sourceMappingURL=mini-custom.css.map */
+
+img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; }
+img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;}
+
+.figure {
+ display: block;
+ margin-left: auto;
+ margin-right: auto;
+ text-align: center;
+}
\ No newline at end of file
diff --git a/_htmresc/st_logo.png b/_htmresc/st_logo.png
deleted file mode 100644
index 8b80057..0000000
--- a/_htmresc/st_logo.png
+++ /dev/null
Binary files differ
diff --git a/_htmresc/st_logo_2020.png b/_htmresc/st_logo_2020.png
new file mode 100644
index 0000000..d6cebb5
--- /dev/null
+++ b/_htmresc/st_logo_2020.png
Binary files differ
