Release v1.9.0
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 805a9a5..e57e823 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -315,6 +315,11 @@
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
#endif
#if defined(STM32H7)
@@ -643,6 +648,10 @@
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
#endif /* STM32G4 */
#if defined(STM32H7)
@@ -1531,18 +1540,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -3243,7 +3252,7 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
diff --git a/Inc/stm32h7xx_hal.h b/Inc/stm32h7xx_hal.h
index f8743fa..8f9946f 100644
--- a/Inc/stm32h7xx_hal.h
+++ b/Inc/stm32h7xx_hal.h
@@ -117,10 +117,34 @@
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
-#endif /* ! SYSCFG_PMCR_BOOSTEN */
/**
* @}
*/
+#endif /* ! SYSCFG_PMCR_BOOSTEN */
+
+
+#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) || defined(SYSCFG_ADC2ALT_ADC2_ROUT1)
+/** @defgroup SYSCFG_Adc2_Alternate_Connection SYSCFG ADC2 Alternate Connection
+ * @{
+ */
+
+/** @brief Adc2 Alternate Connection on Vinp[16] and Vinp[17]
+ */
+#define SYSCFG_ADC2_ROUT0_DAC1_1 ((uint32_t)0x00000000) /*!< DAC1_out1 connected to ADC2 VINP[16] */
+#define SYSCFG_ADC2_ROUT0_VBAT4 SYSCFG_ADC2ALT_ADC2_ROUT0 /*!< VBAT/4 connected to ADC2 VINP[16] */
+#define SYSCFG_ADC2_ROUT1_DAC1_2 ((uint32_t)0x00000000) /*!< DAC1_out2 connected to ADC2 VINP[17] */
+#define SYSCFG_ADC2_ROUT1_VREFINT SYSCFG_ADC2ALT_ADC2_ROUT1 /*!< VREFINT connected to ADC2 VINP[17] */
+
+#define IS_SYSCFG_ADC2ALT_ROUT0(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT0_DAC1_1) || \
+ ((__VALUE__) == SYSCFG_ADC2_ROUT0_VBAT4))
+#define IS_SYSCFG_ADC2ALT_ROUT1(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT1_DAC1_2) || \
+ ((__VALUE__) == SYSCFG_ADC2_ROUT1_VREFINT))
+
+/**
+ * @}
+ */
+#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0 || SYSCFG_ADC2ALT_ADC2_ROUT1*/
+
/** @defgroup SYSCFG_Ethernet_Config Ethernet Config
* @{
@@ -145,10 +169,6 @@
#define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< Select PC3 analog switch */
-#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
- (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
- (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
- (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO /*!< PA0 analog switch opened */
@@ -160,6 +180,16 @@
#define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO /*!< PC3 analog switch opened */
#define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000) /*!< PC3 analog switch closed */
+/**
+ * @}
+ */
+
+#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
+ (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
+ (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
+ (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
+
+
#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \
(((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \
(((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \
@@ -168,9 +198,7 @@
(((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE) || \
(((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN) || \
(((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))
-/**
- * @}
- */
+
/** @defgroup SYSCFG_Boot_Config Boot Config
* @{
@@ -327,6 +355,9 @@
#define EXTI_LINE86 ((uint32_t)0x56) /* Not available in all family lines */
#define EXTI_LINE87 ((uint32_t)0x57)
#define EXTI_LINE88 ((uint32_t)0x58) /* Not available in all family lines */
+#define EXTI_LINE89 ((uint32_t)0x59) /* Not available in all family lines */
+#define EXTI_LINE90 ((uint32_t)0x5A) /* Not available in all family lines */
+#define EXTI_LINE91 ((uint32_t)0x5B) /* Not available in all family lines */
#if defined(DUAL_CORE)
#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
@@ -349,13 +380,13 @@
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
- ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
- ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
- ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
- ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
- ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
- ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
- ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
+ ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+ ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+ ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+ ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+ ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+ ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+ ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
#endif /* DUAL_CORE */
@@ -444,7 +475,8 @@
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
- ((LINE) == EXTI_LINE88))
+ ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \
+ ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
@@ -530,7 +562,8 @@
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
- ((LINE) == EXTI_LINE88))
+ ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \
+ ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
@@ -608,7 +641,7 @@
((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
- ((LINE) == EXTI_LINE53))
+ ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE88))
#else
#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
@@ -667,10 +700,10 @@
/* Exported macro ------------------------------------------------------------*/
+#if defined(DUAL_CORE)
/** @defgroup ART_Exported_Macros ART Exported Macros
* @{
*/
-#if defined(DUAL_CORE)
/** @brief ART Enable Macro.
* Enable the Cortex-M4 ART cache.
@@ -687,10 +720,10 @@
*/
#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__) MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL))
-#endif /* DUAL_CORE */
/**
* @}
*/
+#endif /* DUAL_CORE */
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
* @{
@@ -820,8 +853,19 @@
#define __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
#define __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
#define __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
+#if defined(I2C5)
+#define __HAL_DBGMCU_FREEZE_I2C5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C5))
+#endif /*I2C5*/
+#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
#define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
+#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
+#if defined(TIM23)
+#define __HAL_DBGMCU_FREEZE_TIM23() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM23))
+#endif /*TIM23*/
+#if defined(TIM24)
+#define __HAL_DBGMCU_FREEZE_TIM24() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM24))
+#endif /*TIM24*/
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
@@ -854,8 +898,19 @@
#define __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
#define __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
#define __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
+#if defined(I2C5)
+#define __HAL_DBGMCU_UnFreeze_I2C5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C5))
+#endif /*I2C5*/
+#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
#define __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
+#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
+#if defined(TIM23)
+#define __HAL_DBGMCU_UnFreeze_TIM23() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM23))
+#endif /*TIM23*/
+#if defined(TIM24)
+#define __HAL_DBGMCU_UnFreeze_TIM24() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM24))
+#endif /*TIM24*/
#define __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
#define __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
@@ -1060,6 +1115,12 @@
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
+#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0)
+void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0);
+#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/
+#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1)
+void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1);
+#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/
/**
* @}
diff --git a/Inc/stm32h7xx_hal_adc.h b/Inc/stm32h7xx_hal_adc.h
index 259eb5a..5be1e1a 100644
--- a/Inc/stm32h7xx_hal_adc.h
+++ b/Inc/stm32h7xx_hal_adc.h
@@ -49,8 +49,12 @@
*/
typedef struct
{
- uint32_t Ratio; /*!< Configures the oversampling ratio.
- This parameter can be a value between 1 and 1024 */
+ uint32_t Ratio; /*!< Configures the oversampling ratio. */
+#if defined(ADC_VER_V5_V90)
+ /* On devices STM32H72xx and STM32H73xx, this parameter can be a value from 1 to 1023 for ADC1/2 or a value of @ref ADC_HAL_EC_OVS_RATIO for ADC3*/
+#else
+ /*This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+#endif
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
@@ -100,6 +104,13 @@
uint32_t Resolution; /*!< Configure the ADC resolution.
This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
+#if defined(ADC_VER_V5_V90)
+ uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
+ Refer to reference manual for alignments formats versus resolutions.
+ This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN
+ This parameter is reserved for ADC3 on devices STM32H72xx and STM32H73xx*/
+#endif
+
uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
@@ -156,7 +167,22 @@
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
This parameter can be a value of @ref ADC_ConversionDataManagement.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups
- (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+ (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).*/
+#if defined(ADC_VER_V5_V90)
+ /*Note: On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */
+
+ uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion.
+ This parameter can be a value of @ref ADC_regular_sampling_mode.
+ Note:
+ - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */
+
+ FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
+ or in continuous mode (DMA transfer unlimited, whatever number of conversions).
+ This parameter can be set to ENABLE or DISABLE.
+ Notes:
+ - In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+ - Specific to ADC3 only on devices STM32H72xx and STM32H73xx */
+#endif
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter applies to ADC group regular only.
@@ -239,7 +265,20 @@
FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction.
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE.*/
-
+#if defined(ADC_VER_V5_V90)
+ uint32_t OffsetSign; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data.
+ This parameter can be a value of @ref ADCEx_OffsetSign.
+ Note:
+ - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
+ without continuous mode or external trigger that could launch a conversion).
+ - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+ FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
+ This parameter value can be ENABLE or DISABLE.
+ Note:
+ - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
+ without continuous mode or external trigger that could launch a conversion).
+ - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#endif
FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE. */
@@ -291,6 +330,13 @@
impacted: the comparison of analog watchdog thresholds is done
on oversampling intermediate computation (after ratio, before shift
application): intermediate register bitfield [32:7] (26 most significant bits). */
+#if defined(ADC_VER_V5_V90)
+ uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider.
+ Before setting flag or raising interrupt, analog watchdog can wait to have several
+ consecutive out-of-window samples. This parameter allows to configure this number.
+ This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE.
+ This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. Applicable for ADC3 on devices STM32H72xx and STM32H73xx. */
+#endif
} ADC_AnalogWDGConfTypeDef;
/**
@@ -464,15 +510,35 @@
/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
* @{
*/
-#define ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B) /*!< ADC resolution 16 bits */
-#define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits */
+#define ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B) /*!< ADC resolution 16 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
+#define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
+
+#if defined (ADC_VER_V5_X)
+#define ADC_RESOLUTION_14B_OPT (LL_ADC_RESOLUTION_14B_OPT) /*!< ADC resolution 14 bits optimized for power consumption, available on for devices revision V only */
+#define ADC_RESOLUTION_12B_OPT (LL_ADC_RESOLUTION_12B_OPT) /*!< ADC resolution 12 bits optimized for power consumption, available on for devices revision V only */
+#endif
+
+#if defined(ADC_VER_V5_V90)
+#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
+#endif /* ADC_VER_V5_V90 */
/**
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
+ * @{
+ */
+#define ADC3_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define ADC3_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+#endif
+
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
* @{
*/
@@ -508,6 +574,12 @@
#define ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
+#if defined(TIM23)
+#define ADC_EXTERNALTRIG_T23_TRGO (LL_ADC_REG_TRIG_EXT_TIM23_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM23 TRGO event. Trigger edge set to rising edge (default setting). */
+#endif /*TIM23*/
+#if defined(TIM24)
+#define ADC_EXTERNALTRIG_T24_TRGO (LL_ADC_REG_TRIG_EXT_TIM24_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM24 TRGO event. Trigger edge set to rising edge (default setting). */
+#endif /*TIM24*/
/**
* @}
*/
@@ -522,6 +594,23 @@
/**
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
+ * @{
+ */
+#define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
+#define ADC_SAMPLING_MODE_BULB (ADC3_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
+ Notes:
+ - First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME)
+ - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC3_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events:
+ Trigger rising edge = start sampling
+ Trigger falling edge = stop sampling and start conversion
+ Note: Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+/**
+ * @}
+ */
+#endif
/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
* @{
@@ -567,17 +656,35 @@
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
-#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycles */
-#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */
-#define ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5) /*!< Sampling time 8.5 ADC clock cycles */
-#define ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5) /*!< Sampling time 16.5 ADC clock cycles */
-#define ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5) /*!< Sampling time 32.5 ADC clock cycles */
-#define ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5) /*!< Sampling time 64.5 ADC clock cycles */
-#define ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5) /*!< Sampling time 387.5 ADC clock cycles */
-#define ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5) /*!< Sampling time 810.5 ADC clock cycles */
+#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
+#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
+#define ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5) /*!< Sampling time 8.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
+#define ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5) /*!< Sampling time 16.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
+#define ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5) /*!< Sampling time 32.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
+#define ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5) /*!< Sampling time 64.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
+#define ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5) /*!< Sampling time 387.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
+#define ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5) /*!< Sampling time 810.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */
/**
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define ADC3_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
+#define ADC3_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
+#define ADC3_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
+#define ADC3_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
+#define ADC3_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
+#define ADC3_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
+#define ADC3_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
+#define ADC3_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
+#define ADC3_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously.
+ On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */
+/**
+ * @}
+ */
+#endif
/** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode
* @{
@@ -628,10 +735,10 @@
/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
* @{
*/
-#define ADC_CONVERSIONDATA_DR (0x00000000UL) /*!< Regular Conversion data stored in DR register only */
-#define ADC_CONVERSIONDATA_DFSDM (ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */
-#define ADC_CONVERSIONDATA_DMA_ONESHOT (ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */
-#define ADC_CONVERSIONDATA_DMA_CIRCULAR (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1) /*!< DMA circular mode selected */
+#define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000) /*!< Regular Conversion data stored in DR register only */
+#define ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */
+#define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */
+#define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */
/**
* @}
*/
@@ -645,6 +752,23 @@
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration
+ * @{
+ */
+#define ADC3_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_2SAMPLES ((ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_3SAMPLES ((ADC3_TR1_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_4SAMPLES ((ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_5SAMPLES ((ADC3_TR1_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_6SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_7SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_8SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+/**
+ * @}
+ */
+#endif
+
/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
* @{
*/
@@ -658,6 +782,24 @@
/**
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
+ * @{
+ */
+#define ADC3_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_OVERSAMPLING_RATIO_512 (LL_ADC_OVS_RATIO_512) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_OVERSAMPLING_RATIO_1024 (LL_ADC_OVS_RATIO_1024) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+/**
+ * @}
+ */
+#endif
/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
* @{
@@ -863,6 +1005,16 @@
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
+#if defined(ADC_VER_V5_V90)
+/**
+ * @brief Verify that a given value is aligned with the ADC resolution range. Applicable for ADC3 on devices STM32H72xx and STM32H73xx.
+ * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
+ * @param __ADC_VALUE__ value checked against the resolution.
+ * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
+ */
+#define IS_ADC3_RANGE(__RESOLUTION__, __ADC_VALUE__) \
+ ((__ADC_VALUE__) <= __LL_ADC3_DIGITAL_SCALE(__RESOLUTION__))
+#endif
/**
* @brief Verify the length of the scheduled regular conversions group.
* @param __LENGTH__ number of programmed conversions.
@@ -905,11 +1057,29 @@
* @param __RESOLUTION__ programmed ADC resolution.
* @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
*/
+#if defined(ADC_VER_V5_V90)
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
+#elif defined (ADC_VER_V5_X)
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_14B_OPT) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_12B_OPT) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_8B) )
+#else /* ADC_VER_V5_3 */
#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
((__RESOLUTION__) == ADC_RESOLUTION_8B) )
+#endif /* ADC_VER_V5_V90*/
+
/**
* @brief Verify the ADC resolution setting when limited to 8 bits.
* @param __RESOLUTION__ programmed ADC resolution when limited to 8 bits.
@@ -917,6 +1087,26 @@
*/
#define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B))
+#if defined(ADC_VER_V5_V90)
+/**
+ * @brief Verify the ADC converted data alignment. Applicable for ADC3 on devices STM32H72xx and STM32H73xx.
+ * @param __ALIGN__ programmed ADC converted data alignment.
+ * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
+ */
+#define IS_ADC3_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC3_DATAALIGN_RIGHT) || \
+ ((__ALIGN__) == ADC3_DATAALIGN_LEFT) )
+
+/**
+ * @brief Verify the ADC regular conversions external trigger.
+ * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
+ * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid)
+ */
+#define IS_ADC3_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \
+ ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \
+ ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) )
+
+#endif
+
/**
* @brief Verify the ADC scan mode.
* @param __SCAN_MODE__ programmed ADC scan mode.
@@ -940,6 +1130,7 @@
* @param __REGTRIG__ programmed ADC regular conversions external trigger.
* @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
*/
+#if defined(ADC_VER_V5_V90)
#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
@@ -961,7 +1152,34 @@
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T23_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T24_TRGO) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
+#else
+#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \
+ ((__REGTRIG__) == ADC_SOFTWARE_START) )
+#endif /* ADC_VER_V5_V90*/
+
/**
* @brief Verify the ADC regular conversions check for converted data availability.
@@ -1044,7 +1262,7 @@
/* Delay for ADC voltage regulator startup time */
/* Maximum delay is 10 microseconds */
/* (refer device RM, parameter Tadcvreg_stup). */
-#define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */
+#define ADC_STAB_DELAY_US (10UL) /*!< ADC voltage regulator startup time */
/**
* @}
@@ -1069,10 +1287,10 @@
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
do{ \
- (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
@@ -1225,7 +1443,7 @@
* @arg @ref ADC_CHANNEL_VBAT (1)
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
- *
+ *
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@@ -1233,7 +1451,7 @@
* @retval Value between Min_Data=0 and Max_Data=18
*/
#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
/**
* @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
@@ -1267,7 +1485,7 @@
* @arg @ref ADC_CHANNEL_VBAT (1)
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
- *
+ *
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@@ -1277,7 +1495,7 @@
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
+ __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
/**
* @brief Helper macro to determine whether the selected channel
@@ -1321,7 +1539,7 @@
* @arg @ref ADC_CHANNEL_VBAT (1)
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
- *
+ *
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@@ -1330,7 +1548,7 @@
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/
#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
- __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
+ __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
/**
* @brief Helper macro to convert a channel defined from parameter
@@ -1370,7 +1588,7 @@
* @arg @ref ADC_CHANNEL_VBAT (1)
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
- *
+ *
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@@ -1397,7 +1615,7 @@
* @arg @ref ADC_CHANNEL_18
*/
#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
- __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
+ __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
/**
* @brief Helper macro to determine whether the internal channel
@@ -1419,14 +1637,14 @@
* @arg @ref ADC_CHANNEL_VBAT (1)
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)
- *
+ *
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.
* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
* Value "1" if the internal channel selected is available on the ADC instance selected.
*/
#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
+ __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
/**
* @brief Helper macro to get the ADC multimode conversion data of ADC master
@@ -1442,7 +1660,7 @@
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
- __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
+ __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
/**
* @brief Helper macro to select the ADC common instance
@@ -1455,7 +1673,7 @@
* @retval ADC common register instance
*/
#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
- __LL_ADC_COMMON_INSTANCE((__ADCx__))
+ __LL_ADC_COMMON_INSTANCE((__ADCx__))
/**
* @brief Helper macro to check if all ADC instances sharing the same
@@ -1475,7 +1693,7 @@
* is enabled.
*/
#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
- __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
+ __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
/**
* @brief Helper macro to define the ADC conversion data full-scale digital
@@ -1492,7 +1710,7 @@
* @retval ADC conversion data full-scale digital value
*/
#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
- __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
+ __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
/**
* @brief Helper macro to convert the ADC conversion data from
@@ -1517,9 +1735,9 @@
#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
__ADC_RESOLUTION_TARGET__) \
- __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \
- (__ADC_RESOLUTION_CURRENT__), \
- (__ADC_RESOLUTION_TARGET__))
+ __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
+ (__ADC_RESOLUTION_CURRENT__),\
+ (__ADC_RESOLUTION_TARGET__))
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
@@ -1541,9 +1759,9 @@
#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\
__ADC_RESOLUTION__) \
- __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \
- (__ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+ (__ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate analog reference voltage (Vref+)
@@ -1573,8 +1791,8 @@
*/
#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
__ADC_RESOLUTION__) \
- __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1625,9 +1843,9 @@
#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__) \
- __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \
- (__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1680,12 +1898,12 @@
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__) \
- __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \
- (__TEMPSENSOR_TYP_CALX_V__), \
- (__TEMPSENSOR_CALX_TEMP__), \
- (__VREFANALOG_VOLTAGE__), \
- (__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
+ (__TEMPSENSOR_TYP_CALX_V__),\
+ (__TEMPSENSOR_CALX_TEMP__),\
+ (__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @}
@@ -1713,10 +1931,10 @@
void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
- pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
@@ -1757,9 +1975,9 @@
*/
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
+ * @brief Peripheral Control functions
+ * @{
+ */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
@@ -1793,7 +2011,7 @@
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAError(DMA_HandleTypeDef *hdma);
-void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc);
+void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc);
/**
* @}
diff --git a/Inc/stm32h7xx_hal_adc_ex.h b/Inc/stm32h7xx_hal_adc_ex.h
index 3388553..b86c259 100644
--- a/Inc/stm32h7xx_hal_adc_ex.h
+++ b/Inc/stm32h7xx_hal_adc_ex.h
@@ -46,8 +46,12 @@
*/
typedef struct
{
- uint32_t Ratio; /*!< Configures the oversampling ratio.
- This parameter can be a value between 1 and 1024 */
+ uint32_t Ratio; /*!< Configures the oversampling ratio. */
+#if defined(ADC_VER_V5_V90)
+ /* On devices STM32H72xx and STM32H73xx this parameter can be a value from 1 to 1023 for ADC1/2 and value of @ref ADC_HAL_EC_OVS_RATIO for ADC3*/
+#else
+ /* This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+#endif
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
@@ -117,13 +121,24 @@
uint32_t InjectedOffsetRightShift; /*!< Specifies whether the 1 bit Right-shift feature is used or not.
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE. */
+#if defined(ADC_VER_V5_V90)
+ uint32_t InjectedOffsetSign; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data.
+ This parameter can be a value of @ref ADCEx_OffsetSign.
+ Note:
+ - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
+ - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */
+ FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
+ This parameter value can be ENABLE or DISABLE.
+ Note:
+ - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
+ - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */
+
+#endif
FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not.
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE. */
- uint32_t InjectedLeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
- This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
-
+
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
@@ -276,6 +291,17 @@
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
+ * @{
+ */
+#define ADC3_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is substracted */
+#define ADC3_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */
+/**
+ * @}
+ */
+#endif
+
/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
* @{
*/
@@ -372,6 +398,17 @@
/**
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
+ * @{
+ */
+/* ADC_CFGR fields of parameters that can be updated when no conversion
+ (neither regular nor injected) is on-going */
+#define ADC3_CFGR_FIELDS_2 ((ADC3_CFGR_DMACFG | ADC_CFGR_AUTDLY))
+/**
+ * @}
+ */
+#endif
#if defined(DFSDM1_Channel0)
/** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
@@ -449,13 +486,15 @@
#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
(LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
+
+#if defined (ADC3)
/**
* @brief Check whether or not ADC is independent.
* @param __HANDLE__ ADC handle.
* @note When multimode feature is not available, the macro always returns SET.
* @retval SET (ADC is independent) or RESET (ADC is not).
*/
-#if defined (ADC3)
+
#define ADC_IS_INDEPENDENT(__HANDLE__) \
( ( ( ((__HANDLE__)->Instance) == ADC3) \
)? \
@@ -522,6 +561,14 @@
*/
#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
+#if defined(ADC_VER_V5_V90)
+/**
+ * @brief Configure the ADC DMA continuous request.
+ * @param __DMACONTREQ_MODE__ DMA continuous request mode.
+ * @retval None
+ */
+#define ADC3_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC3_CFGR_DMACFG_Pos)
+#endif
/**
* @brief Configure the channel number into offset OFRx register.
* @param __CHANNEL__ ADC Channel.
@@ -597,6 +644,12 @@
)
#endif /* ADC_VER_V5_3 */
+#if defined(ADC_VER_V5_V90)
+#define ADC3_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
+ ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC3_CFGR_RES) >> 3UL) * 2UL))
+
+#endif /* ADC_VER_V5_V90 */
+
/**
* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
* @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.
@@ -611,6 +664,17 @@
* @retval None
*/
#if defined(ADC_VER_V5_3)
+#if defined(ADC_VER_V5_V90)
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+ ( ((__HANDLE__)->Instance == ADC3) \
+ ?((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC3_CFGR_RES)>> 3UL)*2UL)) \
+ : \
+ ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
+ ?((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
+ : \
+ ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
+ )
+#else
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
( \
((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
@@ -618,6 +682,8 @@
: \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)
+#endif
+
#else
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
(((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
@@ -643,8 +709,8 @@
* @param __THRESHOLD__: Value to be shifted
* @retval None
*/
-#if defined(ADC_VER_V5_3)
-#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+#if defined(ADC_VER_V5_3) || defined(ADC_VER_V5_V90)
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
( \
((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
@@ -707,9 +773,9 @@
#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
)? \
- ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
: \
RESET \
)
@@ -719,12 +785,12 @@
* @param __HANDLE__: ADC handle
* @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
*/
-#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
+#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \
)? \
SET \
: \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
)
#if defined (ADC3)
/**
@@ -734,10 +800,10 @@
*/
#define ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
( ( ((__HANDLE__)->Instance == ADC3) \
- )? \
- SET \
- : \
- ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
+ )? \
+ SET \
+ : \
+ ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
)
#endif
/**
@@ -751,8 +817,8 @@
)? \
SET \
: \
- ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
#else
#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
@@ -760,8 +826,8 @@
)? \
SET \
: \
- ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
#endif
@@ -771,22 +837,22 @@
* @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
*/
#if defined (ADC3)
-#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
)? \
SET \
: \
- ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
#else
-#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
- ( ( ((__HANDLE__)->Instance == ADC1) \
+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) \
)? \
SET \
: \
- ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
- ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
#endif
@@ -954,7 +1020,15 @@
((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
-
+#if defined(ADC_VER_V5_V90)
+/**
+ * @brief Verify the ADC offset sign setting.
+ * @param __OFFSET_SIGN__ ADC offset sign.
+ * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
+ */
+#define IS_ADC3_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC3_OFFSET_SIGN_NEGATIVE) || \
+ ((__OFFSET_SIGN__) == ADC3_OFFSET_SIGN_POSITIVE) )
+#endif /* ADC_VER_V5_V90 */
/**
* @brief Verify the ADC injected channel setting.
* @param __CHANNEL__ programmed ADC injected channel.
@@ -994,24 +1068,24 @@
* @param __EDGE__ programmed ADC edge trigger setting.
* @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
*/
-#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
- ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
- ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
- ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
/**
* @brief Verify the ADC multimode setting.
* @param __MODE__ programmed ADC multimode setting.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
-#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
- ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
- ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
- ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
- ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
- ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
- ((__MODE__) == ADC_DUALMODE_INTERL) || \
- ((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
+#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_INTERL) || \
+ ((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
/**
* @brief Verify the ADC dual data mode setting.
@@ -1059,26 +1133,43 @@
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
+#if defined(ADC_VER_V5_V90)
+/**
+ * @brief Verify the ADC analog watchdog filtering setting.
+ * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
+ * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE_ADC3(__FILTERING_MODE__) (((__FILTERING_MODE__) == ADC3_AWD_FILTERING_NONE) || \
+ ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_2SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_3SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_4SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_5SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_6SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_7SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_8SAMPLES) )
+
+#endif /* ADC_VER_V5_V90 */
+
/**
* @brief Verify the ADC conversion (regular or injected or both).
* @param __CONVERSION__ ADC conversion group.
* @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
*/
-#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
- ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
- ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
+ ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
+ ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
/**
* @brief Verify the ADC event type.
* @param __EVENT__ ADC event.
* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
*/
-#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
- ((__EVENT__) == ADC_AWD_EVENT) || \
- ((__EVENT__) == ADC_AWD2_EVENT) || \
- ((__EVENT__) == ADC_AWD3_EVENT) || \
- ((__EVENT__) == ADC_OVR_EVENT) || \
- ((__EVENT__) == ADC_JQOVF_EVENT) )
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
+ ((__EVENT__) == ADC_AWD_EVENT) || \
+ ((__EVENT__) == ADC_AWD2_EVENT) || \
+ ((__EVENT__) == ADC_AWD3_EVENT) || \
+ ((__EVENT__) == ADC_OVR_EVENT) || \
+ ((__EVENT__) == ADC_JQOVF_EVENT) )
/**
* @brief Verify the ADC oversampling ratio.
@@ -1087,6 +1178,22 @@
*/
#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))
+#if defined(ADC_VER_V5_V90)
+/**
+ * @brief Verify the ADC3 oversampling ratio.
+ * @param __RATIO__ programmed ADC oversampling ratio.
+ * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
+ */
+#define IS_ADC_OVERSAMPLING_RATIO_ADC3(__RATIO__) (((__RATIO__) == ADC3_OVERSAMPLING_RATIO_2 ) || \
+ ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_4 ) || \
+ ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_8 ) || \
+ ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_16 ) || \
+ ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_32 ) || \
+ ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_64 ) || \
+ ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_128 ) || \
+ ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_256 ))
+#endif /* ADC_VER_V5_V90 */
+
/**
* @brief Verify the ADC oversampling shift.
* @param __SHIFT__ programmed ADC oversampling shift.
@@ -1165,9 +1272,9 @@
/* ADC calibration */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff);
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
-HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer);
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
-HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer);
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc);
@@ -1209,7 +1316,7 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected);
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
diff --git a/Inc/stm32h7xx_hal_conf_template.h b/Inc/stm32h7xx_hal_conf_template.h
index 70d54f8..10ed9ea 100644
--- a/Inc/stm32h7xx_hal_conf_template.h
+++ b/Inc/stm32h7xx_hal_conf_template.h
@@ -38,6 +38,7 @@
#define HAL_ADC_MODULE_ENABLED
#define HAL_CEC_MODULE_ENABLED
#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORDIC_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
@@ -53,6 +54,7 @@
#define HAL_FDCAN_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GFXMMU_MODULE_ENABLED
+#define HAL_FMAC_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
@@ -102,11 +104,11 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
-#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+ #define HSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@@ -114,7 +116,7 @@
* This value is the default CSI value after Reset.
*/
#if !defined (CSI_VALUE)
- #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+ #define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
/**
@@ -123,7 +125,7 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+ #define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
@@ -131,16 +133,16 @@
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
- #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+ #define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
+ #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
#if !defined (LSI_VALUE)
- #define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/
+ #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
@@ -151,7 +153,7 @@
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
- #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
+ #define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -161,8 +163,8 @@
/**
* @brief This is the HAL system configuration section
*/
-#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY (0x0FUL) /*!< tick interrupt priority */
#define USE_RTOS 0
#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */
#define USE_SPI_CRC 1U /*!< use CRC in SPI */
@@ -170,6 +172,7 @@
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
@@ -179,6 +182,7 @@
#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
+#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
@@ -218,12 +222,12 @@
#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
-#define ETH_MAC_ADDR0 ((uint8_t)0x02)
-#define ETH_MAC_ADDR1 ((uint8_t)0x00)
-#define ETH_MAC_ADDR2 ((uint8_t)0x00)
-#define ETH_MAC_ADDR3 ((uint8_t)0x00)
-#define ETH_MAC_ADDR4 ((uint8_t)0x00)
-#define ETH_MAC_ADDR5 ((uint8_t)0x00)
+#define ETH_MAC_ADDR0 (0x02UL)
+#define ETH_MAC_ADDR1 (0x00UL)
+#define ETH_MAC_ADDR2 (0x00UL)
+#define ETH_MAC_ADDR3 (0x00UL)
+#define ETH_MAC_ADDR4 (0x00UL)
+#define ETH_MAC_ADDR5 (0x00UL)
/* ########################## Assert Selection ############################## */
/**
@@ -306,6 +310,10 @@
#include "stm32h7xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
+#ifdef HAL_CORDIC_MODULE_ENABLED
+ #include "stm32h7xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32h7xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
@@ -326,6 +334,10 @@
#include "stm32h7xx_hal_gfxmmu.h"
#endif /* HAL_GFXMMU_MODULE_ENABLED */
+#ifdef HAL_FMAC_MODULE_ENABLED
+ #include "stm32h7xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32h7xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
diff --git a/Inc/stm32h7xx_hal_cordic.h b/Inc/stm32h7xx_hal_cordic.h
new file mode 100644
index 0000000..1fb9208
--- /dev/null
+++ b/Inc/stm32h7xx_hal_cordic.h
@@ -0,0 +1,599 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_cordic.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the CORDIC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_CORDIC_H
+#define STM32H7xx_HAL_CORDIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+#if defined(CORDIC)
+/** @addtogroup STM32H7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORDIC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORDIC_Exported_Types CORDIC Exported Types
+ * @{
+ */
+
+/**
+ * @brief CORDIC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_CORDIC_STATE_RESET = 0x00U, /*!< CORDIC not yet initialized or disabled */
+ HAL_CORDIC_STATE_READY = 0x01U, /*!< CORDIC initialized and ready for use */
+ HAL_CORDIC_STATE_BUSY = 0x02U, /*!< CORDIC internal process is ongoing */
+ HAL_CORDIC_STATE_ERROR = 0x03U /*!< CORDIC error state */
+} HAL_CORDIC_StateTypeDef;
+
+/**
+ * @brief CORDIC Handle Structure definition
+ */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+typedef struct __CORDIC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+{
+ CORDIC_TypeDef *Instance; /*!< Register base address */
+
+ int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */
+
+ int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */
+
+ uint32_t NbCalcToOrder; /*!< Remaining number of calculation to order */
+
+ uint32_t NbCalcToGet; /*!< Remaining number of calculation result to get */
+
+ uint32_t DMADirection; /*!< Direction of CORDIC DMA transfers */
+
+ DMA_HandleTypeDef *hdmaIn; /*!< CORDIC peripheral input data DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaOut; /*!< CORDIC peripheral output data DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CORDIC locking object */
+
+ __IO HAL_CORDIC_StateTypeDef State; /*!< CORDIC state */
+
+ __IO uint32_t ErrorCode; /*!< CORDIC peripheral error code
+ This parameter can be a value of @ref CORDIC_Error_Code */
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ void (* ErrorCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC error callback */
+ void (* CalculateCpltCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC calculate complete callback */
+
+ void (* MspInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp Init callback */
+ void (* MspDeInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp DeInit callback */
+
+#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
+
+} CORDIC_HandleTypeDef;
+
+/**
+ * @brief CORDIC Config Structure definition
+ */
+typedef struct
+{
+ uint32_t Function; /*!< Function
+ This parameter can be a value of @ref CORDIC_Function */
+
+ uint32_t Scale; /*!< Scaling factor
+ This parameter can be a value of @ref CORDIC_Scale */
+
+ uint32_t InSize; /*!< Width of input data
+ This parameter can be a value of @ref CORDIC_In_Size */
+
+ uint32_t OutSize; /*!< Width of output data
+ This parameter can be a value of @ref CORDIC_Out_Size */
+
+ uint32_t NbWrite; /*!< Number of 32-bit write expected for one calculation
+ This parameter can be a value of @ref CORDIC_Nb_Write */
+
+ uint32_t NbRead; /*!< Number of 32-bit read expected after one calculation
+ This parameter can be a value of @ref CORDIC_Nb_Read */
+
+ uint32_t Precision; /*!< Number of cycles for calculation
+ This parameter can be a value of @ref CORDIC_Precision_In_Cycles_Number */
+
+} CORDIC_ConfigTypeDef;
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+/**
+ * @brief HAL CORDIC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_CORDIC_ERROR_CB_ID = 0x00U, /*!< CORDIC error callback ID */
+ HAL_CORDIC_CALCULATE_CPLT_CB_ID = 0x01U, /*!< CORDIC calculate complete callback ID */
+
+ HAL_CORDIC_MSPINIT_CB_ID = 0x02U, /*!< CORDIC MspInit callback ID */
+ HAL_CORDIC_MSPDEINIT_CB_ID = 0x03U, /*!< CORDIC MspDeInit callback ID */
+
+} HAL_CORDIC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL CORDIC Callback pointer definition
+ */
+typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< pointer to a CORDIC callback function */
+
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants
+ * @{
+ */
+
+/** @defgroup CORDIC_Error_Code CORDIC Error code
+ * @{
+ */
+#define HAL_CORDIC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_CORDIC_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Wrong parameter error */
+#define HAL_CORDIC_ERROR_NOT_READY ((uint32_t)0x00000002U) /*!< Peripheral not ready */
+#define HAL_CORDIC_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
+#define HAL_CORDIC_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA error */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+#define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Function CORDIC Function
+ * @{
+ */
+#define CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */
+#define CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */
+#define CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */
+#define CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */
+#define CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */
+#define CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */
+#define CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */
+#define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
+#define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
+#define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Precision_In_Cycles_Number CORDIC Precision in Cycles Number
+ * @{
+ */
+/* Note: 1 cycle corresponds to 4 algorithm iterations */
+#define CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
+#define CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
+#define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
+#define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
+#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
+#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Scale CORDIC Scaling factor
+ * @{
+ */
+/* Scale factor value 'n' implies that the input data have been multiplied
+ by a factor 2exp(-n), and/or the output data need to be multiplied by 2exp(n). */
+#define CORDIC_SCALE_0 (0x00000000U)
+#define CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
+#define CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
+#define CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
+#define CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
+#define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
+#define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
+#define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Interrupts_Enable CORDIC Interrupts Enable bit
+ * @{
+ */
+#define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_DMAR DMA Read Request Enable bit
+ * @{
+ */
+#define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_DMAW DMA Write Request Enable bit
+ * @{
+ */
+#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Nb_Write CORDIC Number of 32-bit write required for one calculation
+ * @{
+ */
+#define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
+ 32-bit data input (Q1.31 format), or two 16-bit
+ data input (Q1.15 format) packed in one 32 bits Data */
+#define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
+ (Q1.31 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Nb_Read CORDIC Number of 32-bit read required after one calculation
+ * @{
+ */
+#define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
+ 32-bit data ouput (Q1.31 format), or two 16-bit
+ data output (Q1.15 format) packed in one 32 bits Data */
+#define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
+ (Q1.31 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_In_Size CORDIC input data size
+ * @{
+ */
+#define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
+#define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Out_Size CORDIC Results Size
+ * @{
+ */
+#define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
+#define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Flags CORDIC status flags
+ * @{
+ */
+#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_DMA_Direction CORDIC DMA direction
+ * @{
+ */
+#define CORDIC_DMA_DIR_NONE ((uint32_t)0x00000000U) /*!< DMA direction : none */
+#define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */
+#define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */
+#define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CORDIC_Exported_Macros CORDIC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CORDIC handle state.
+ * @param __HANDLE__ CORDIC handle
+ * @retval None
+ */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET)
+#endif /*USE_HAL_CORDIC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the CORDIC interrupt when result is ready
+ * @param __HANDLE__ CORDIC handle.
+ * @param __INTERRUPT__ CORDIC Interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_IT_IEN Enable Interrupt
+ * @retval None
+ */
+#define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the CORDIC interrupt
+ * @param __HANDLE__ CORDIC handle.
+ * @param __INTERRUPT__ CORDIC Interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_IT_IEN Enable Interrupt
+ * @retval None
+ */
+#define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
+
+/** @brief Check whether the specified CORDIC interrupt occurred or not.
+ Dummy macro as no interrupt status flag.
+ * @param __HANDLE__ CORDIC handle.
+ * @param __INTERRUPT__ CORDIC interrupt to check
+ * @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
+ */
+#define __HAL_CORDIC_GET_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
+
+/** @brief Clear specified CORDIC interrupt status. Dummy macro as no
+ interrupt status flag.
+ * @param __HANDLE__ CORDIC handle.
+ * @param __INTERRUPT__ CORDIC interrupt to clear
+ * @retval None
+ */
+#define __HAL_CORDIC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
+
+/** @brief Check whether the specified CORDIC status flag is set or not.
+ * @param __HANDLE__ CORDIC handle.
+ * @param __FLAG__ CORDIC flag to check
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
+ * @retval SET (flag is set) or RESET (flag is reset)
+ */
+#define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear specified CORDIC status flag. Dummy macro as no
+ flag can be cleared.
+ * @param __HANDLE__ CORDIC handle.
+ * @param __FLAG__ CORDIC flag to clear
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
+ * @retval None
+ */
+#define __HAL_CORDIC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
+
+/** @brief Check whether the specified CORDIC interrupt is enabled or not.
+ * @param __HANDLE__ CORDIC handle.
+ * @param __INTERRUPT__ CORDIC interrupt to check
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_IT_IEN Enable Interrupt
+ * @retval FlagStatus
+ */
+#define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CORDIC_Private_Macros CORDIC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Verify the CORDIC function.
+ * @param __FUNCTION__ Name of the function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_CORDIC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == CORDIC_FUNCTION_COSINE) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_SINE) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_PHASE) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_MODULUS) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_ARCTANGENT) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_HCOSINE) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_HSINE) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_HARCTANGENT) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_NATURALLOG) || \
+ ((__FUNCTION__) == CORDIC_FUNCTION_SQUAREROOT))
+
+
+/**
+ * @brief Verify the CORDIC precision.
+ * @param __PRECISION__ CORDIC Precision in Cycles Number.
+ * @retval SET (__PRECISION__ is a valid value) or RESET (__PRECISION__ is invalid)
+ */
+#define IS_CORDIC_PRECISION(__PRECISION__) (((__PRECISION__) == CORDIC_PRECISION_1CYCLE) || \
+ ((__PRECISION__) == CORDIC_PRECISION_2CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_3CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_4CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_5CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_6CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_7CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_8CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_9CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_10CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_11CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_12CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_13CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_14CYCLES) || \
+ ((__PRECISION__) == CORDIC_PRECISION_15CYCLES))
+
+/**
+ * @brief Verify the CORDIC scaling factor.
+ * @param __SCALE__ Number of cycles for calculation, 1 cycle corresponding to 4 algorithm iterations.
+ * @retval SET (__SCALE__ is a valid value) or RESET (__SCALE__ is invalid)
+ */
+#define IS_CORDIC_SCALE(__SCALE__) (((__SCALE__) == CORDIC_SCALE_0) || \
+ ((__SCALE__) == CORDIC_SCALE_1) || \
+ ((__SCALE__) == CORDIC_SCALE_2) || \
+ ((__SCALE__) == CORDIC_SCALE_3) || \
+ ((__SCALE__) == CORDIC_SCALE_4) || \
+ ((__SCALE__) == CORDIC_SCALE_5) || \
+ ((__SCALE__) == CORDIC_SCALE_6) || \
+ ((__SCALE__) == CORDIC_SCALE_7))
+
+/**
+ * @brief Verify the CORDIC number of 32-bits write expected for one calculation.
+ * @param __NBWRITE__ Number of 32-bits write expected for one calculation.
+ * @retval SET (__NBWRITE__ is a valid value) or RESET (__NBWRITE__ is invalid)
+ */
+#define IS_CORDIC_NBWRITE(__NBWRITE__) (((__NBWRITE__) == CORDIC_NBWRITE_1) || \
+ ((__NBWRITE__) == CORDIC_NBWRITE_2))
+
+/**
+ * @brief Verify the CORDIC number of 32-bits read expected after one calculation.
+ * @param __NBREAD__ Number of 32-bits read expected after one calculation.
+ * @retval SET (__NBREAD__ is a valid value) or RESET (__NBREAD__ is invalid)
+ */
+#define IS_CORDIC_NBREAD(__NBREAD__) (((__NBREAD__) == CORDIC_NBREAD_1) || \
+ ((__NBREAD__) == CORDIC_NBREAD_2))
+
+/**
+ * @brief Verify the CORDIC input data size for one calculation.
+ * @param __INSIZE__ input data size for one calculation.
+ * @retval SET (__INSIZE__ is a valid value) or RESET (__INSIZE__ is invalid)
+ */
+#define IS_CORDIC_INSIZE(__INSIZE__) (((__INSIZE__) == CORDIC_INSIZE_32BITS) || \
+ ((__INSIZE__) == CORDIC_INSIZE_16BITS))
+
+/**
+ * @brief Verify the CORDIC output data size for one calculation.
+ * @param __OUTSIZE__ output data size for one calculation.
+ * @retval SET (__OUTSIZE__ is a valid value) or RESET (__OUTSIZE__ is invalid)
+ */
+#define IS_CORDIC_OUTSIZE(__OUTSIZE__) (((__OUTSIZE__) == CORDIC_OUTSIZE_32BITS) || \
+ ((__OUTSIZE__) == CORDIC_OUTSIZE_16BITS))
+
+/**
+ * @brief Verify the CORDIC DMA transfer Direction.
+ * @param __DMADIR__ DMA transfer direction.
+ * @retval SET (__DMADIR__ is a valid value) or RESET (__DMADIR__ is invalid)
+ */
+#define IS_CORDIC_DMA_DIRECTION(__DMADIR__) (((__DMADIR__) == CORDIC_DMA_DIR_IN) || \
+ ((__DMADIR__) == CORDIC_DMA_DIR_OUT) || \
+ ((__DMADIR__) == CORDIC_DMA_DIR_IN_OUT))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Exported_Functions
+ * @{
+ */
+/* Exported functions ------------------------------------------------------- */
+
+/** @addtogroup CORDIC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic);
+HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic);
+void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic);
+void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic);
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, pCORDIC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID);
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Exported_Functions_Group2
+ * @{
+ */
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig);
+HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc);
+HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection);
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Exported_Functions_Group3
+ * @{
+ */
+/* Callback functions *********************************************************/
+void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic);
+void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic);
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Exported_Functions_Group4
+ * @{
+ */
+/* IRQ handler management *****************************************************/
+void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic);
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Exported_Functions_Group5
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic);
+uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* CORDIC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_CORDIC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_cryp.h b/Inc/stm32h7xx_hal_cryp.h
index 3ed76b2..fc24fbf 100644
--- a/Inc/stm32h7xx_hal_cryp.h
+++ b/Inc/stm32h7xx_hal_cryp.h
@@ -64,8 +64,8 @@
uint32_t HeaderSize; /*!< The size of header buffer in word */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
- uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
- Vector only once and to skip configuration for consecutive processings.
+ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to configure Key and Initialization
+ Vector only once and to skip configuration for consecutive processing.
This parameter can be a value of @ref CRYP_Configuration_Skip */
} CRYP_ConfigTypeDef;
@@ -108,7 +108,7 @@
__IO uint16_t CrypOutCount; /*!< Counter of output data */
- uint16_t Size; /*!< length of input data in word */
+ uint16_t Size; /*!< length of input data in word or in byte, according to DataWidthUnit */
uint32_t Phase; /*!< CRYP peripheral phase */
diff --git a/Inc/stm32h7xx_hal_dfsdm.h b/Inc/stm32h7xx_hal_dfsdm.h
index 57fb4db..648ef94 100644
--- a/Inc/stm32h7xx_hal_dfsdm.h
+++ b/Inc/stm32h7xx_hal_dfsdm.h
@@ -237,7 +237,7 @@
uint32_t ErrorCode; /*!< DFSDM filter error code */
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
- uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */
+ uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */
void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */
void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */
void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */
@@ -302,8 +302,8 @@
/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
* @{
*/
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
/**
* @}
*/
@@ -331,8 +331,8 @@
/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
* @{
*/
-#define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */
-#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
+#define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */
+#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
/**
* @}
*/
@@ -340,10 +340,10 @@
/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
* @{
*/
-#define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */
-#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
-#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
-#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
+#define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */
+#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
+#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
+#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
/**
* @}
*/
@@ -383,15 +383,15 @@
/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
* @{
*/
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */
-#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */
-#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
-#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */
-#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
-#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3) /*!< For all DFSDM filters */
@@ -399,12 +399,16 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0) /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */
-#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32H7B0xx) || defined(STM32H7B0xxQ)
+#if (STM32H7_DEV_ID == 0x480UL)
#define DFSDM_FILTER_EXT_TRIG_COMP1_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
- DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)
+ DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)
#define DFSDM_FILTER_EXT_TRIG_COMP2_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
-#endif /* STM32H7A3xx || STM32H7A3xxQ || STM32H7B3xx || STM32H7B3xxQ || STM32H7B0xx || STM32H7B0xxQ */
+#elif (STM32H7_DEV_ID == 0x483UL)
+#define DFSDM_FILTER_EXT_TRIG_TIM23_TRGO (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | \
+ DFSDM_FLTCR1_JEXTSEL_0)
+#define DFSDM_FILTER_EXT_TRIG_TIM24_TRGO (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2 )
+#endif /* STM32H7_DEV_ID == 0x480UL */
/**
* @}
*/
@@ -750,7 +754,7 @@
#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
-#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32H7B0xx) || defined(STM32H7B0xxQ)
+#if (STM32H7_DEV_ID == 0x480UL)
#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
@@ -767,6 +771,24 @@
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP1_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP2_OUT))
+#elif (STM32H7_DEV_ID == 0x483UL)
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM23_TRGO) || \
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM24_TRGO))
+
#else
#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
@@ -784,7 +806,7 @@
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT))
-#endif /* STM32H7A3xx || STM32H7A3xxQ || STM32H7B3xx || STM32H7B3xxQ || STM32H7B0xx || STM32H7B0xxQ */
+#endif /* STM32H7_DEV_ID == 0x480UL */
#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
diff --git a/Inc/stm32h7xx_hal_dma.h b/Inc/stm32h7xx_hal_dma.h
index 61d3a99..3c1f6fe 100644
--- a/Inc/stm32h7xx_hal_dma.h
+++ b/Inc/stm32h7xx_hal_dma.h
@@ -332,8 +332,11 @@
#define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */
#define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */
+
+#if defined(SAI2)
#define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */
#define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */
+#endif /* SAI2 */
#define DMA_REQUEST_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */
#define DMA_REQUEST_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */
@@ -385,6 +388,38 @@
#define DMA_REQUEST_USART10_TX 119U /*!< DMAMUX1 USART10 request */
#endif /* USART10 */
+#if defined(FMAC)
+#define DMA_REQUEST_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */
+#define DMA_REQUEST_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */
+#endif /* FMAC */
+
+#if defined(CORDIC)
+#define DMA_REQUEST_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */
+#define DMA_REQUEST_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */
+#endif /* CORDIC */
+
+#if defined(I2C5)
+#define DMA_REQUEST_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */
+#define DMA_REQUEST_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */
+#endif /* I2C5 */
+
+#if defined(TIM23)
+#define DMA_REQUEST_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */
+#define DMA_REQUEST_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */
+#define DMA_REQUEST_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */
+#define DMA_REQUEST_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */
+#define DMA_REQUEST_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */
+#define DMA_REQUEST_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */
+#endif /* TIM23 */
+
+#if defined(TIM24)
+#define DMA_REQUEST_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */
+#define DMA_REQUEST_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */
+#define DMA_REQUEST_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */
+#define DMA_REQUEST_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */
+#define DMA_REQUEST_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */
+#define DMA_REQUEST_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */
+#endif /* TIM24 */
/* DMAMUX2 requests */
#define BDMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
@@ -1200,11 +1235,13 @@
* @{
*/
-#if defined(ADC3)
+#if defined(TIM24)
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_TIM24_TRIG))
+#elif defined(ADC3)
#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
#else
#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
-#endif /* ADC3 */
+#endif /* TIM24 */
#if defined(ADC3)
#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
diff --git a/Inc/stm32h7xx_hal_eth.h b/Inc/stm32h7xx_hal_eth.h
index 223f346..039dc66 100644
--- a/Inc/stm32h7xx_hal_eth.h
+++ b/Inc/stm32h7xx_hal_eth.h
@@ -25,10 +25,12 @@
extern "C" {
#endif
-#if defined(ETH)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
+#if defined(ETH)
+
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
@@ -60,8 +62,8 @@
__IO uint32_t DESC1;
__IO uint32_t DESC2;
__IO uint32_t DESC3;
- __IO uint32_t BackupAddr0; /* used to store rx buffer 1 address */
- __IO uint32_t BackupAddr1; /* used to store rx buffer 2 address */
+ uint32_t BackupAddr0; /* used to store rx buffer 1 address */
+ uint32_t BackupAddr1; /* used to store rx buffer 2 address */
}ETH_DMADescTypeDef;
/**
*
diff --git a/Inc/stm32h7xx_hal_eth_ex.h b/Inc/stm32h7xx_hal_eth_ex.h
index 0512a0e..cec3887 100644
--- a/Inc/stm32h7xx_hal_eth_ex.h
+++ b/Inc/stm32h7xx_hal_eth_ex.h
@@ -36,7 +36,7 @@
/** @addtogroup ETHEx
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup ETHEx_Exported_Types ETHEx Exported Types
diff --git a/Inc/stm32h7xx_hal_exti.h b/Inc/stm32h7xx_hal_exti.h
index 94a6ea3..18cffec 100644
--- a/Inc/stm32h7xx_hal_exti.h
+++ b/Inc/stm32h7xx_hal_exti.h
@@ -150,22 +150,30 @@
#define EXTI_LINE_49 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x11U)
#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x12U)
#define EXTI_LINE_51 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x13U)
-#if !defined(UART9)
+#if defined(LPTIM4)
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x14U)
#else
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)
-#endif /* UART9 */
-#if !defined(USART10)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x15U)
#else
#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
-#endif /* USART10 */
+#endif /*LPTIM5*/
#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
+#if defined(EXTI_IMR2_IM57)
#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)
+#else
+#define EXTI_LINE_57 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x19U)
+#endif /*EXTI_IMR2_IM57*/
#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
+#if defined(EXTI_IMR2_IM59)
#define EXTI_LINE_59 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
+#else
+#define EXTI_LINE_59 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x1BU)
+#endif /*EXTI_IMR2_IM59*/
#define EXTI_LINE_60 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
#define EXTI_LINE_61 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
#define EXTI_LINE_62 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
@@ -202,15 +210,12 @@
#define EXTI_LINE_79 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)
#define EXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
#endif /* DUAL_CORE */
-
#define EXTI_LINE_81 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)
-
#if defined (DUAL_CORE)
#define EXTI_LINE_82 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U)
#else
#define EXTI_LINE_82 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)
#endif /* DUAL_CORE */
-
#define EXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
#if defined (DUAL_CORE)
#define EXTI_LINE_84 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U)
@@ -227,6 +232,15 @@
#if defined(DTS)
#define EXTI_LINE_88 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)
#endif /* DTS */
+#if defined(EXTI_IMR3_IM89)
+#define EXTI_LINE_89 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)
+#endif /*EXTI_IMR3_IM89*/
+#if defined(EXTI_IMR3_IM90)
+#define EXTI_LINE_90 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
+#endif /*EXTI_IMR3_IM90*/
+#if defined(I2C5)
+#define EXTI_LINE_91 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
+#endif /*I2C5*/
/**
* @}
@@ -271,7 +285,9 @@
#define EXTI_GPIOF 0x00000005U
#define EXTI_GPIOG 0x00000006U
#define EXTI_GPIOH 0x00000007U
+#if defined(GPIOI)
#define EXTI_GPIOI 0x00000008U
+#endif /*GPIOI*/
#define EXTI_GPIOJ 0x00000009U
#define EXTI_GPIOK 0x0000000AU
@@ -378,11 +394,13 @@
/**
* @brief EXTI Line number
*/
-#if defined (EXTI_LINE_88)
+#if (STM32H7_DEV_ID == 0x483UL)
+#define EXTI_LINE_NB 92UL
+#elif (STM32H7_DEV_ID == 0x480UL)
#define EXTI_LINE_NB 89UL
#else
#define EXTI_LINE_NB 88UL
-#endif /* EXTI_LINE_88 */
+#endif /* EXTI_LINE_91 */
/**
* @}
@@ -420,6 +438,7 @@
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00UL)
+#if defined(GPIOI)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
@@ -431,6 +450,18 @@
((__PORT__) == EXTI_GPIOI) || \
((__PORT__) == EXTI_GPIOJ) || \
((__PORT__) == EXTI_GPIOK))
+#else
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH) || \
+ ((__PORT__) == EXTI_GPIOJ) || \
+ ((__PORT__) == EXTI_GPIOK))
+#endif /*GPIOI*/
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16UL)
#if defined (LPTIM4) && defined (LPTIM5)
diff --git a/Inc/stm32h7xx_hal_fdcan.h b/Inc/stm32h7xx_hal_fdcan.h
index a2c4791..ecc6290 100644
--- a/Inc/stm32h7xx_hal_fdcan.h
+++ b/Inc/stm32h7xx_hal_fdcan.h
@@ -28,6 +28,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
+#if defined(FDCAN1)
+
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
@@ -2403,6 +2405,7 @@
/**
* @}
*/
+#endif /* FDCAN1 */
#ifdef __cplusplus
}
diff --git a/Inc/stm32h7xx_hal_flash.h b/Inc/stm32h7xx_hal_flash.h
index f94029d..8a47e0b 100644
--- a/Inc/stm32h7xx_hal_flash.h
+++ b/Inc/stm32h7xx_hal_flash.h
@@ -544,9 +544,13 @@
#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))
+#if defined (DUAL_BANK)
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
__HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
__HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))
+#else
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__)
+#endif /* DUAL_BANK */
/**
@@ -588,9 +592,13 @@
#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))
+#if defined (DUAL_BANK)
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
__HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
__HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))
+#else
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__)
+#endif /* DUAL_BANK */
/**
@@ -637,8 +645,12 @@
#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))
+#if defined (DUAL_BANK)
#define __HAL_FLASH_GET_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
__HAL_FLASH_GET_FLAG_BANK2(__FLAG__))
+#else
+#define __HAL_FLASH_GET_FLAG(__FLAG__) __HAL_FLASH_GET_FLAG_BANK1(__FLAG__)
+#endif /* DUAL_BANK */
/**
@@ -682,8 +694,12 @@
#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))
+#if defined (DUAL_BANK)
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
- __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
+ __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
+#else
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__)
+#endif /* DUAL_BANK */
/**
* @}
@@ -768,16 +784,23 @@
#endif /* FLASH_OPTCR_PG_OTP */
#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
-
+#if defined (DUAL_BANK)
#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))
+#endif /* DUAL_BANK */
#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
-
+#if defined (DUAL_BANK)
#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
+#endif /* DUAL_BANK */
+#if defined (DUAL_BANK)
#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
+#else
+#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) <= FLASH_END))
+#endif /* DUAL_BANK */
+#if defined (DUAL_BANK)
#if defined (FLASH_OPTCR_PG_OTP)
#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
@@ -787,16 +810,28 @@
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
#endif /* FLASH_OPTCR_PG_OTP */
+#else
+#if defined (FLASH_OPTCR_PG_OTP)
+#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
+ IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))
+#else
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS))
+#endif /* FLASH_OPTCR_PG_OTP */
+#endif /* DUAL_BANK */
-#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
+#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
- ((BANK) == FLASH_BANK_2) || \
- ((BANK) == FLASH_BANK_BOTH))
-
-#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
- ((BANK) == FLASH_BANK_2))
-
+#if defined (DUAL_BANK)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
+ ((BANK) == FLASH_BANK_2) || \
+ ((BANK) == FLASH_BANK_BOTH))
+#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
+ ((BANK) == FLASH_BANK_2))
+#else
+#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
+#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
+#endif /* DUAL_BANK */
/**
* @}
diff --git a/Inc/stm32h7xx_hal_flash_ex.h b/Inc/stm32h7xx_hal_flash_ex.h
index ce67854..3c4c81a 100644
--- a/Inc/stm32h7xx_hal_flash_ex.h
+++ b/Inc/stm32h7xx_hal_flash_ex.h
@@ -138,6 +138,16 @@
This parameter must be a value of @ref FLASHEx_OTP_Blocks */
#endif /* FLASH_OTPBL_LOCKBL */
+#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
+ uint32_t SharedRamConfig; /*!< Specifies the configuration of TCM / AXI shared RAM.
+ This parameter must be a value of @ref FLASHEx_OB_TCM_AXI_SHARED */
+#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
+
+#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
+ uint32_t FreqBoostState; /*!< Specifies the state of CPU Frequency Boost.
+ This parameter must be a value of @ref FLASHEx_OB_CPUFREQ_BOOST */
+#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
+
} FLASH_OBProgramInitTypeDef;
/**
@@ -227,6 +237,30 @@
#if defined (FLASH_OTPBL_LOCKBL)
#define OPTIONBYTE_OTP_LOCK 0x80U /*!< OTP Lock option byte configuration */
#endif /* FLASH_OTPBL_LOCKBL */
+#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
+#define OPTIONBYTE_SHARED_RAM 0x100U /*!< TCM / AXI Shared RAM option byte configuration */
+#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
+#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
+#define OPTIONBYTE_FREQ_BOOST 0x200U /*!< CPU Frequency Boost option byte configuration */
+#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
+
+#if defined (DUAL_CORE)
+#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
+ OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
+ OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD) /*!< All option byte configuration */
+#elif defined (FLASH_OTPBL_LOCKBL)
+#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
+ OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
+ OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK) /*!< All option byte configuration */
+#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
+#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
+ OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
+ OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST) /*!< All option byte configuration */
+#else
+#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
+ OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
+ OPTIONBYTE_BOOTADD) /*!< All option byte configuration */
+#endif /* DUAL_CORE */
/**
* @}
*/
@@ -255,8 +289,8 @@
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
* @{
*/
-#define OB_IWDG_SW 0x20U /*!< Software IWDG selected */
-#define OB_IWDG_HW 0x00U /*!< Hardware IWDG selected */
+#define OB_IWDG_SW OB_IWDG1_SW /*!< Software IWDG selected */
+#define OB_IWDG_HW OB_IWDG1_HW /*!< Hardware IWDG selected */
/**
* @}
*/
@@ -351,8 +385,10 @@
* @{
*/
#define FLASH_BANK_1 0x01U /*!< Bank 1 */
+#if defined (DUAL_BANK)
#define FLASH_BANK_2 0x02U /*!< Bank 2 */
-#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
+#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
+#endif /* DUAL_BANK */
/**
* @}
*/
@@ -500,7 +536,7 @@
* @}
*/
-#if defined (DUAL_CORE)
+#if defined (FLASH_OPTSR_NRST_STOP_D2)
/** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2
* @{
*/
@@ -518,7 +554,7 @@
/**
* @}
*/
-#endif /* DUAL_CORE */
+#endif /* FLASH_OPTSR_NRST_STOP_D2 */
/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK
* @{
@@ -549,15 +585,29 @@
*/
#endif /* FLASH_OPTSR_VDDMMC_HSLV */
-/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION
+#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
+/** @defgroup FLASHEx_OB_CPUFREQ_BOOST FLASHEx OB CPUFREQ BOOST
* @{
*/
-#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */
-#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */
-#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */
+#define OB_CPUFREQ_BOOST_DISABLE 0x00000000U /*!< CPUFREQ BOOST disabled */
+#define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST /*!< CPUFREQ BOOST enabled */
/**
* @}
*/
+#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
+
+#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
+/** @defgroup FLASHEx_OB_TCM_AXI_SHARED FLASHEx OB TCM AXI SHARED
+ * @{
+ */
+#define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U /*!< 64KB ITCM / 320KB system AXI */
+#define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0 /*!< 128KB ITCM / 256KB system AXI */
+#define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1 /*!< 192KB ITCM / 192KB system AXI */
+#define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED /*!< 256KB ITCM / 128KB system AXI */
+/**
+ * @}
+ */
+#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
/** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type
* @{
@@ -570,7 +620,9 @@
#define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */
#define OB_USER_SECURITY 0x0040U /*!< security selection */
#define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */
+#if defined (DUAL_BANK)
#define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */
+#endif /* DUAL_BANK */
#if defined (FLASH_OPTSR_VDDMMC_HSLV)
#define OB_USER_VDDMMC_HSLV 0x0200U /*!< VDDMMC HSLV selection */
#endif /* FLASH_OPTSR_VDDMMC_HSLV */
@@ -578,10 +630,43 @@
#define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */
#define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */
#define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */
-#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection*/
-#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection*/
#endif /*DUAL_CORE*/
+#if defined (FLASH_OPTSR_NRST_STOP_D2)
+#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection */
+#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection */
+#endif /* FLASH_OPTSR_NRST_STOP_D2 */
+#if defined (DUAL_CORE)
+#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
+ OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
+ OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
+ OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\
+ OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
+#elif defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
+ OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
+ OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
+ OB_USER_VDDMMC_HSLV)
+#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
+#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
+ OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
+ OB_USER_SECURITY | OB_USER_IOHSLV |\
+ OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
+#else
+#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
+ OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
+ OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK )
+#endif /* DUAL_CORE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION
+ * @{
+ */
+#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */
+#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */
+#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */
/**
* @}
*/
@@ -678,9 +763,13 @@
* @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
* @retval none
*/
+#if defined (DUAL_BANK)
#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \
MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
+#else
+#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__))
+#endif /* DUAL_BANK */
/**
* @brief Get the FLASH Program/Erase parallelism.
@@ -688,9 +777,14 @@
* @retval FLASH Program/Erase parallelism
* This return value can be a value of @ref FLASH_Program_Parallelism
*/
+#if defined (DUAL_BANK)
#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \
READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
+#else
+#define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)
+#endif /* DUAL_BANK */
+
#endif /* FLASH_CR_PSIZE */
/**
@@ -724,8 +818,10 @@
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
+#if defined (DUAL_BANK)
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
+#endif /* DUAL_BANK */
HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
@@ -761,13 +857,8 @@
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
((VALUE) == OB_WRPSTATE_ENABLE))
-#if defined (FLASH_OPTSR_VDDMMC_HSLV)
-#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))
-#elif defined (DUAL_CORE)
-#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
-#else
-#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
-#endif /*DUAL_CORE*/
+#define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \
+ (((VALUE) & ~OPTIONBYTE_ALL) == 0U))
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
@@ -850,16 +941,25 @@
#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
+#endif /* DUAL_CORE */
+#if defined (FLASH_OPTSR_NRST_STOP_D2)
#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
-#endif /* DUAL_CORE */
-#if defined (DUAL_CORE)
-#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))
-#else
-#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
-#endif /* DUAL_CORE */
+#endif /* FLASH_OPTSR_NRST_STOP_D2 */
+
+#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
+#define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \
+ ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB))
+#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
+
+#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
+#define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE))
+#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
+
+#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \
+ (((TYPE) & ~OB_USER_ALL) == 0U))
#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
((VALUE) == OB_BOOT_ADD1) || \
diff --git a/Inc/stm32h7xx_hal_fmac.h b/Inc/stm32h7xx_hal_fmac.h
new file mode 100644
index 0000000..8eb9941
--- /dev/null
+++ b/Inc/stm32h7xx_hal_fmac.h
@@ -0,0 +1,696 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_fmac.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the FMAC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FMAC_H
+#define STM32H7xx_HAL_FMAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+#if defined(FMAC)
+/** @addtogroup STM32H7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FMAC_Exported_Types FMAC Exported Types
+ * @{
+ */
+
+/**
+ * @brief FMAC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_FMAC_STATE_RESET = 0x00U, /*!< FMAC not yet initialized or disabled */
+ HAL_FMAC_STATE_READY = 0x20U, /*!< FMAC initialized and ready for use */
+ HAL_FMAC_STATE_BUSY = 0x24U, /*!< FMAC internal process is ongoing */
+ HAL_FMAC_STATE_BUSY_RD = 0x25U, /*!< FMAC reading configuration is ongoing */
+ HAL_FMAC_STATE_BUSY_WR = 0x26U, /*!< FMAC writing configuration is ongoing */
+ HAL_FMAC_STATE_TIMEOUT = 0xA0U, /*!< FMAC in Timeout state */
+ HAL_FMAC_STATE_ERROR = 0xE0U /*!< FMAC in Error state */
+} HAL_FMAC_StateTypeDef;
+
+/**
+ * @brief FMAC Handle Structure definition
+ */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+typedef struct __FMAC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+{
+ FMAC_TypeDef *Instance; /*!< Register base address */
+
+ uint32_t FilterParam; /*!< Filter configuration (operation and parameters).
+ Set to 0 if no valid configuration was applied. */
+
+ uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
+ This parameter can be a value of @ref FMAC_Buffer_Access. */
+
+ uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
+ This parameter can be a value of @ref FMAC_Buffer_Access. */
+
+ int16_t *pInput; /*!< Pointer to FMAC input data buffer */
+
+ uint16_t InputCurrentSize; /*!< Number of the input elements already written into FMAC */
+
+ uint16_t *pInputSize; /*!< Number of input elements to write (memory allocated to pInput).
+ In case of early interruption of the filter operation, its value will be updated. */
+
+ int16_t *pOutput; /*!< Pointer to FMAC output data buffer */
+
+ uint16_t OutputCurrentSize; /*!< Number of the output elements already read from FMAC */
+
+ uint16_t *pOutputSize; /*!< Number of output elements to read (memory allocated to pOutput).
+ In case of early interruption of the filter operation, its value will be updated. */
+
+ DMA_HandleTypeDef *hdmaIn; /*!< FMAC peripheral input data DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaOut; /*!< FMAC peripheral output data DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle parameters */
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC error callback */
+
+ void (* HalfGetDataCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC get half data callback */
+
+ void (* GetDataCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC get data callback */
+
+ void (* HalfOutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC half output data ready callback */
+
+ void (* OutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC output data ready callback */
+
+ void (* FilterConfigCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC filter configuration callback */
+
+ void (* FilterPreloadCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC filter preload callback */
+
+ void (* MspInitCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC Msp DeInit callback */
+
+#endif /* (USE_HAL_FMAC_REGISTER_CALLBACKS) */
+
+ HAL_LockTypeDef Lock; /*!< FMAC locking object */
+
+ __IO HAL_FMAC_StateTypeDef State; /*!< FMAC state related to global handle management
+ This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
+
+ __IO HAL_FMAC_StateTypeDef RdState; /*!< FMAC state related to read operations (access to Y buffer)
+ This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
+
+ __IO HAL_FMAC_StateTypeDef WrState; /*!< FMAC state related to write operations (access to X1 buffer)
+ This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< FMAC peripheral error code
+ This parameter can be a value of @ref FMAC_Error_Code */
+
+} FMAC_HandleTypeDef;
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief FMAC Callback ID structure definition
+ */
+typedef enum
+{
+ HAL_FMAC_ERROR_CB_ID = 0x00U, /*!< FMAC error callback ID */
+ HAL_FMAC_HALF_GET_DATA_CB_ID = 0x01U, /*!< FMAC get half data callback ID */
+ HAL_FMAC_GET_DATA_CB_ID = 0x02U, /*!< FMAC get data callback ID */
+ HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID = 0x03U, /*!< FMAC half output data ready callback ID */
+ HAL_FMAC_OUTPUT_DATA_READY_CB_ID = 0x04U, /*!< FMAC output data ready callback ID */
+ HAL_FMAC_FILTER_CONFIG_CB_ID = 0x05U, /*!< FMAC filter configuration callback ID */
+ HAL_FMAC_FILTER_PRELOAD_CB_ID = 0x06U, /*!< FMAC filter preload callback ID */
+
+ HAL_FMAC_MSPINIT_CB_ID = 0x07U, /*!< FMAC MspInit callback ID */
+ HAL_FMAC_MSPDEINIT_CB_ID = 0x08U, /*!< FMAC MspDeInit callback ID */
+} HAL_FMAC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL FMAC Callback pointer definition
+ */
+typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer to an FMAC callback function */
+
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+
+/**
+ * @brief FMAC Filter Configuration Structure definition
+ */
+typedef struct
+{
+ uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF).
+ Ignored if InputBufferSize is set to 0 (previous configuration kept).
+ NB: the buffers can overlap or even coincide exactly. */
+
+ uint8_t InputBufferSize; /*!< Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ 0 if a previous configuration should be kept. */
+
+ uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces
+ in the buffer is inferior to this threshold.
+ This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
+
+ uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF).
+ Ignored if CoeffBufferSize is set to 0 (previous configuration kept).
+ NB: the buffers can overlap or even coincide exactly. */
+
+ uint8_t CoeffBufferSize; /*!< Number of 16-bit addresses allocated to the coefficient buffer.
+ 0 if a previous configuration should be kept. */
+
+ uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF).
+ Ignored if OuputBufferSize is set to 0 (previous configuration kept).
+ NB: the buffers can overlap or even coincide exactly. */
+
+ uint8_t OutputBufferSize; /*!< Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ 0 if a previous configuration should be kept. */
+
+ uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values
+ in the buffer is inferior to this threshold.
+ This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
+
+ int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A.
+ If not needed, it should be set to NULL. */
+
+ uint8_t CoeffASize; /*!< Size of the coefficient vector A. */
+
+ int16_t *pCoeffB; /*!< Initialization of the coefficient vector B.
+ If not needed (re-use of a previously loaded buffer), it should be set to NULL. */
+
+ uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */
+
+ uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMT, IT, Polling, None.
+ This parameter can be a value of @ref FMAC_Buffer_Access. */
+
+ uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
+ This parameter can be a value of @ref FMAC_Buffer_Access. */
+
+ uint32_t Clip; /*!< Enable or disable the clipping feature (wrapping when the q1.15 range is exceeded).
+ This parameter can be a value of @ref FMAC_Clip_State. */
+
+ uint32_t Filter; /*!< Filter type.
+ This parameter can be a value of @ref FMAC_Functions (filter related values). */
+
+ uint8_t P; /*!< Parameter P (vector length, number of filter taps, etc.). */
+
+ uint8_t Q; /*!< Parameter Q (vector length, etc.). Ignored if not needed. */
+
+ uint8_t R; /*!< Parameter R (gain, etc.). Ignored if not needed. */
+
+} FMAC_FilterConfigTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup FMAC_Exported_Constants FMAC Exported Constants
+ * @{
+ */
+
+/** @defgroup FMAC_Error_Code FMAC Error code
+ * @{
+ */
+#define HAL_FMAC_ERROR_NONE 0x00000000UL /*!< No error */
+#define HAL_FMAC_ERROR_SAT 0x00000001UL /*!< Saturation error */
+#define HAL_FMAC_ERROR_UNFL 0x00000002UL /*!< Underflow error */
+#define HAL_FMAC_ERROR_OVFL 0x00000004UL /*!< Overflow error */
+#define HAL_FMAC_ERROR_DMA 0x00000008UL /*!< DMA error */
+#define HAL_FMAC_ERROR_RESET 0x00000010UL /*!< Reset error */
+#define HAL_FMAC_ERROR_PARAM 0x00000020UL /*!< Parameter error */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040UL /*!< Invalid Callback error */
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+#define HAL_FMAC_ERROR_TIMEOUT 0x00000080UL /*!< Timeout error */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Functions FMAC Functions
+ * @{
+ */
+#define FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */
+#define FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */
+#define FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */
+#define FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */
+#define FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Data_Buffer_Threshold FMAC Data Buffer Threshold
+ * @{
+ * @note This parameter sets a watermark for buffer full (input) or buffer empty (output).
+ */
+#define FMAC_THRESHOLD_1 0x00000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
+ Output: Buffer empty flag set if the number of unread values in the buffer is less than 1. */
+#define FMAC_THRESHOLD_2 0x01000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
+ Output: Buffer empty flag set if the number of unread values in the buffer is less than 2. */
+#define FMAC_THRESHOLD_4 0x02000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
+ Output: Buffer empty flag set if the number of unread values in the buffer is less than 4. */
+#define FMAC_THRESHOLD_8 0x03000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
+ Output: Buffer empty flag set if the number of unread values in the buffer is less than 8. */
+#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFUL /*!< The configured threshold value shouldn't be changed */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Buffer_Access FMAC Buffer Access
+ * @{
+ */
+#define FMAC_BUFFER_ACCESS_NONE 0x00U /*!< Buffer handled by an external IP (ADC for instance) */
+#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through the FMAC DMA */
+#define FMAC_BUFFER_ACCESS_POLLING 0x02U /*!< Buffer accessed through polling */
+#define FMAC_BUFFER_ACCESS_IT 0x03U /*!< Buffer accessed through interruptions */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Clip_State FMAC Clip State
+ * @{
+ */
+#define FMAC_CLIP_DISABLED 0x00000000UL /*!< Clipping disabled */
+#define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN /*!< Clipping enabled */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Flags FMAC status flags
+ * @{
+ */
+#define FMAC_FLAG_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */
+#define FMAC_FLAG_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
+#define FMAC_FLAG_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
+#define FMAC_FLAG_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
+#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Interrupts_Enable FMAC Interrupts Enable bit
+ * @{
+ */
+#define FMAC_IT_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */
+#define FMAC_IT_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
+#define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
+#define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
+#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_DMAR DMA Read Request Enable bit
+ * @{
+ */
+#define FMAC_DMA_REN FMAC_CR_DMAREN /*!< DMA Read Requests Enable */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_DMAW DMA Write Request Enable bit
+ * @{
+ */
+#define FMAC_DMA_WEN FMAC_CR_DMAWEN /*!< DMA Write Channel Enable */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_DMAS DMA START bit
+ * @{
+ */
+#define FMAC_START FMAC_PARAM_START /*!< DMA Start */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_TimeOut_Value FMAC polling-based communications time-out value
+ * @{
+ */
+#define HAL_FMAC_TIMEOUT_VALUE 1000UL /*!< FMAC polling-based communications time-out value */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Reset_TimeOut_Value FMAC reset time-out value
+ * @{
+ */
+#define HAL_FMAC_RESET_TIMEOUT_VALUE 500UL /*!< FMAC reset time-out value */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FMAC_Exported_Macros FMAC Exported Macros
+ * @{
+ */
+
+/** @brief Reset FMAC handle state.
+ * @param __HANDLE__ FMAC handle.
+ * @retval None
+ */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_FMAC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMAC_STATE_RESET)
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the FMAC interrupt when result is ready
+ * @param __HANDLE__ FMAC handle.
+ * @param __INTERRUPT__ FMAC Interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref FMAC_IT_RIEN Read interrupt enable
+ * @arg @ref FMAC_IT_WIEN Write interrupt enable
+ * @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
+ * @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
+ * @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
+ * @retval None
+ */
+#define __HAL_FMAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the FMAC interrupt
+ * @param __HANDLE__ FMAC handle.
+ * @param __INTERRUPT__ FMAC Interrupt.
+ * This parameter can be one of the following values:
+ * @arg @ref FMAC_IT_RIEN Read interrupt enable
+ * @arg @ref FMAC_IT_WIEN Write interrupt enable
+ * @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
+ * @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
+ * @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
+ * @retval None
+ */
+#define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief Check whether the specified FMAC interrupt occurred or not.
+ * @param __HANDLE__ FMAC handle.
+ * @param __INTERRUPT__ FMAC interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
+ * @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
+ * @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
+ * @arg @ref FMAC_FLAG_UNFL Underflow Error Flag
+ * @arg @ref FMAC_FLAG_SAT Saturation Error Flag
+ * @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
+ */
+#define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
+
+/** @brief Clear specified FMAC interrupt status. Dummy macro as the
+ interrupt status flags are read-only.
+ * @param __HANDLE__ FMAC handle.
+ * @param __INTERRUPT__ FMAC interrupt to clear.
+ * @retval None
+ */
+#define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
+
+/** @brief Check whether the specified FMAC status flag is set or not.
+ * @param __HANDLE__ FMAC handle.
+ * @param __FLAG__ FMAC flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
+ * @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
+ * @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
+ * @arg @ref FMAC_FLAG_UNFL Underflow Error Flag
+ * @arg @ref FMAC_FLAG_SAT Saturation error Flag
+ * @retval SET (flag is set) or RESET (flag is reset)
+ */
+#define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear specified FMAC status flag. Dummy macro as no
+ flag can be cleared.
+ * @param __HANDLE__ FMAC handle.
+ * @param __FLAG__ FMAC flag to clear.
+ * @retval None
+ */
+#define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
+
+/** @brief Check whether the specified FMAC interrupt is enabled or not.
+ * @param __HANDLE__ FMAC handle.
+ * @param __INTERRUPT__ FMAC interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMAC_IT_RIEN Read interrupt enable
+ * @arg @ref FMAC_IT_WIEN Write interrupt enable
+ * @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
+ * @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
+ * @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
+ * @retval FlagStatus
+ */
+#define __HAL_FMAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CR) & (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup FMAC_Private_Macros
+ * @{
+ */
+
+/**
+ * @brief Verify the FMAC function.
+ * @param __FUNCTION__ ID of the function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_FMAC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
+ ((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
+ ((__FUNCTION__) == FMAC_FUNC_LOAD_Y) || \
+ ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
+ ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
+
+/**
+ * @brief Verify the FMAC load function.
+ * @param __FUNCTION__ ID of the load function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_FMAC_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
+ ((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
+ ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
+
+/**
+ * @brief Verify the FMAC load function.
+ * @param __FUNCTION__ ID of the load function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_FMAC_N_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
+ ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
+
+/**
+ * @brief Verify the FMAC load function.
+ * @param __FUNCTION__ ID of the load function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_FMAC_N_M_LOAD_FUNCTION(__FUNCTION__) ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)
+
+/**
+ * @brief Verify the FMAC filter function.
+ * @param __FUNCTION__ ID of the filter function.
+ * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
+ */
+#define IS_FMAC_FILTER_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
+ ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
+
+
+/**
+ * @brief Verify the FMAC threshold.
+ * @param __THRESHOLD__ Value of the threshold.
+ * @retval SET (__THRESHOLD__ is a valid value) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_FMAC_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == FMAC_THRESHOLD_1) || \
+ ((__THRESHOLD__) == FMAC_THRESHOLD_2) || \
+ ((__THRESHOLD__) == FMAC_THRESHOLD_4) || \
+ ((__THRESHOLD__) == FMAC_THRESHOLD_NO_VALUE) || \
+ ((__THRESHOLD__) == FMAC_THRESHOLD_8))
+
+/**
+ * @brief Verify the FMAC filter parameter P.
+ * @param __P__ Value of the filter parameter P.
+ * @param __FUNCTION__ ID of the filter function.
+ * @retval SET (__P__ is a valid value) or RESET (__P__ is invalid)
+ */
+#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
+ (((__P__) >= 2U) && ((__P__) <= 127U))) || \
+ (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
+ (((__P__) >= 2U) && ((__P__) <= 64U))) )
+
+/**
+ * @brief Verify the FMAC filter parameter Q.
+ * @param __Q__ Value of the filter parameter Q.
+ * @param __FUNCTION__ ID of the filter function.
+ * @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid)
+ */
+#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
+ (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
+ (((__Q__) >= 1U) && ((__Q__) <= 63U))) )
+
+/**
+ * @brief Verify the FMAC filter parameter R.
+ * @param __R__ Value of the filter parameter.
+ * @param __FUNCTION__ ID of the filter function.
+ * @retval SET (__R__ is a valid value) or RESET (__R__ is invalid)
+ */
+#define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
+ ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) && \
+ ((__R__) <= 7U))
+
+/**
+ * @brief Verify the FMAC buffer access.
+ * @param __BUFFER_ACCESS__ Type of access.
+ * @retval SET (__BUFFER_ACCESS__ is a valid value) or RESET (__BUFFER_ACCESS__ is invalid)
+ */
+#define IS_FMAC_BUFFER_ACCESS(__BUFFER_ACCESS__) (((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_NONE) || \
+ ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_DMA) || \
+ ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_POLLING) || \
+ ((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_IT))
+
+/**
+ * @brief Verify the FMAC clip feature.
+ * @param __CLIP_STATE__ Clip state.
+ * @retval SET (__CLIP_STATE__ is a valid value) or RESET (__CLIP_STATE__ is invalid)
+ */
+#define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED) || \
+ ((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
+
+/**
+ * @}
+ */
+
+/* Exported functions ------------------------------------------------------- */
+/** @addtogroup FMAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMAC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac);
+HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_MspInit(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac);
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
+ pFMAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup FMAC_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
+HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
+HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize);
+HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize);
+HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
+HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize);
+HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
+HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout);
+HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac);
+/**
+ * @}
+ */
+
+/** @addtogroup FMAC_Exported_Functions_Group3
+ * @{
+ */
+/* Callback functions *********************************************************/
+void HAL_FMAC_ErrorCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_HalfGetDataCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_GetDataCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_HalfOutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_OutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_FilterConfigCallback(FMAC_HandleTypeDef *hfmac);
+void HAL_FMAC_FilterPreloadCallback(FMAC_HandleTypeDef *hfmac);
+/**
+ * @}
+ */
+
+/** @addtogroup FMAC_Exported_Functions_Group4
+ * @{
+ */
+/* IRQ handler management *****************************************************/
+void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac);
+/**
+ * @}
+ */
+
+/** @addtogroup FMAC_Exported_Functions_Group5
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac);
+uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMAC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FMAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_gpio_ex.h b/Inc/stm32h7xx_hal_gpio_ex.h
index 933a4c5..dc56483 100644
--- a/Inc/stm32h7xx_hal_gpio_ex.h
+++ b/Inc/stm32h7xx_hal_gpio_ex.h
@@ -77,6 +77,11 @@
#if defined(HRTIM1)
#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
+#if defined(SAI4)
+#define GPIO_AF1_SAI4 ((uint8_t)0x01) /* SAI4 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
+#endif /* SAI4 */
+#define GPIO_AF1_FMC ((uint8_t)0x01) /* FMC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
+
/**
* @brief AF 2 selection
@@ -89,7 +94,10 @@
#if defined(HRTIM1)
#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
+#if defined(FDCAN3)
+#define GPIO_AF2_FDCAN3 ((uint8_t)0x02) /* FDCAN3 Alternate Function mapping */
+#endif /*FDCAN3*/
/**
* @brief AF 3 selection
@@ -108,6 +116,7 @@
#if defined(HRTIM1)
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
+#define GPIO_AF3_LTDC ((uint8_t)0x03) /* LTDC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
/**
* @brief AF 4 selection
@@ -116,17 +125,27 @@
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
+#if defined(I2C5)
+#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */
+#endif /* I2C5*/
#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
+#if defined(USART10)
+#define GPIO_AF4_USART10 ((uint8_t)0x04) /* USART10 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
+#endif /*USART10*/
#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
#if defined(DFSDM2_BASE)
#define GPIO_AF4_DFSDM2 ((uint8_t)0x04) /* DFSDM2 Alternate Function mapping */
#endif /* DFSDM2_BASE */
+#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
#if defined(PSSI)
#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
#endif /* PSSI */
+#if defined(OCTOSPIM)
+#define GPIO_AF4_OCTOSPIM_P1 ((uint8_t)0x04) /* OCTOSPI Manager Port 1 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */
+#endif /* OCTOSPIM */
/**
* @brief AF 5 selection
@@ -138,6 +157,9 @@
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
+#if defined(FDCAN3)
+#define GPIO_AF5_FDCAN3 ((uint8_t)0x05) /* FDCAN3 Alternate Function mapping */
+#endif /*FDCAN3*/
/**
* @brief AF 6 selection
@@ -146,6 +168,9 @@
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
+#if defined(I2C5)
+#define GPIO_AF6_I2C5 ((uint8_t)0x06) /* I2C5 Alternate Function mapping */
+#endif /* I2C5*/
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
#if defined(DFSDM2_BASE)
@@ -169,14 +194,15 @@
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
-#define GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */
#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
+#if defined(SAI2)
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
+#endif /*SAI2*/
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
@@ -212,7 +238,9 @@
/**
* @brief AF 10 selection
*/
+#if defined(SAI2)
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
+#endif /*SAI2*/
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */
#if defined(USB2_OTG_FS)
#define GPIO_AF10_OTG2_FS ((uint8_t)0x0A) /* OTG2_FS Alternate Function mapping */
@@ -230,13 +258,14 @@
#define GPIO_AF10_SAI4 ((uint8_t)0x0A) /* SAI4 Alternate Function mapping */
#endif /* SAI4 */
#if !defined(USB2_OTG_FS)
-#define GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+#define GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
#endif /* !USB2_OTG_FS */
#define GPIO_AF10_OTG1_HS ((uint8_t)0x0A) /* OTG1_HS Alternate Function mapping */
#if defined(OCTOSPIM)
#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OCTOSPI Manager Port 1 Alternate Function mapping */
#endif /* OCTOSPIM */
#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
/**
* @brief AF 11 selection
@@ -264,7 +293,7 @@
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
#endif /* ETH */
#if defined(LTDC)
-#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */
#endif /*LTDC*/
#if defined(OCTOSPIM)
#define GPIO_AF11_OCTOSPIM_P1 ((uint8_t)0x0B) /* OCTOSPI Manager Port 1 Alternate Function mapping */
@@ -286,6 +315,9 @@
#if defined(USB2_OTG_FS)
#define GPIO_AF12_OTG1_FS ((uint8_t)0x0C) /* OTG1_FS Alternate Function mapping */
#endif /* USB2_OTG_FS */
+#if defined(OCTOSPIM)
+#define GPIO_AF12_OCTOSPIM_P1 ((uint8_t)0x0C) /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
/**
* @brief AF 13 selection
@@ -303,12 +335,18 @@
#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */
#endif /* PSSI */
#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */
+#if defined(TIM23)
+#define GPIO_AF13_TIM23 ((uint8_t)0x0D) /* TIM23 Alternate Function mapping */
+#endif /*TIM23*/
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
+#if defined(TIM24)
+#define GPIO_AF14_TIM24 ((uint8_t)0x0E) /* TIM24 Alternate Function mapping */
+#endif /*TIM24*/
/**
* @brief AF 15 selection
@@ -360,11 +398,21 @@
#define GPIOE_PIN_AVAILABLE GPIO_PIN_All
#define GPIOF_PIN_AVAILABLE GPIO_PIN_All
#define GPIOG_PIN_AVAILABLE GPIO_PIN_All
+#if defined(GPIOI)
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
+#endif /*GPIOI*/
+#if defined(GPIOI)
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
+#else
+#define GPIOJ_PIN_AVAILABLE (GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 )
+#endif /* GPIOI */
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
+#if defined(GPIOI)
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
+#else
+#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 )
+#endif /* GPIOI */
/**
* @}
@@ -377,6 +425,7 @@
/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
* @{
*/
+#if defined(GPIOI)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
((__GPIOx__) == (GPIOB))? 1UL :\
((__GPIOx__) == (GPIOC))? 2UL :\
@@ -387,6 +436,18 @@
((__GPIOx__) == (GPIOH))? 7UL :\
((__GPIOx__) == (GPIOI))? 8UL :\
((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
+#else
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
+ ((__GPIOx__) == (GPIOB))? 1UL :\
+ ((__GPIOx__) == (GPIOC))? 2UL :\
+ ((__GPIOx__) == (GPIOD))? 3UL :\
+ ((__GPIOx__) == (GPIOE))? 4UL :\
+ ((__GPIOx__) == (GPIOF))? 5UL :\
+ ((__GPIOx__) == (GPIOG))? 6UL :\
+ ((__GPIOx__) == (GPIOH))? 7UL :\
+ ((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
+#endif /* GPIOI */
+
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_hcd.h b/Inc/stm32h7xx_hal_hcd.h
index 1e60d55..fa00ecc 100644
--- a/Inc/stm32h7xx_hal_hcd.h
+++ b/Inc/stm32h7xx_hal_hcd.h
@@ -109,8 +109,8 @@
* @{
*/
#define HCD_SPEED_HIGH USBH_HS_SPEED
-#define HCD_SPEED_FULL USBH_FS_SPEED
-#define HCD_SPEED_LOW USBH_LS_SPEED
+#define HCD_SPEED_FULL USBH_FSLS_SPEED
+#define HCD_SPEED_LOW USBH_FSLS_SPEED
/**
* @}
@@ -170,19 +170,15 @@
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address,
+ uint8_t speed, uint8_t ep_type, uint16_t mps);
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
-void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
@@ -191,14 +187,14 @@
*/
typedef enum
{
- HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
- HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
- HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
- HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
- HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
+ HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
+ HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
+ HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
+ HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
+ HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
- HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
- HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
+ HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
+ HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
} HAL_HCD_CallbackIDTypeDef;
/**
@@ -232,25 +228,20 @@
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t direction,
- uint8_t ep_type,
- uint8_t token,
- uint8_t *pbuff,
- uint16_t length,
- uint8_t do_ping);
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t direction, uint8_t ep_type,
+ uint8_t token, uint8_t *pbuff,
+ uint16_t length, uint8_t do_ping);
/* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
/**
* @}
*/
@@ -259,9 +250,9 @@
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
@@ -272,8 +263,8 @@
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
diff --git a/Inc/stm32h7xx_hal_i2c_ex.h b/Inc/stm32h7xx_hal_i2c_ex.h
index 1fbd4e5..797cd4c 100644
--- a/Inc/stm32h7xx_hal_i2c_ex.h
+++ b/Inc/stm32h7xx_hal_i2c_ex.h
@@ -55,6 +55,7 @@
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
+#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
@@ -63,6 +64,11 @@
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
+#if defined(SYSCFG_PMCR_I2C5_FMP)
+#define I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported */
+#endif
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_i2s.h b/Inc/stm32h7xx_hal_i2s.h
index b451896..66762f4 100644
--- a/Inc/stm32h7xx_hal_i2s.h
+++ b/Inc/stm32h7xx_hal_i2s.h
@@ -65,7 +65,7 @@
This parameter can be a value of @ref I2S_Clock_Polarity */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref I2S_MSB_LSB_transmission */
+ This parameter can be a value of @ref I2S_MSB_LSB_Transmission */
uint32_t WSInversion; /*!< Control the Word Select Inversion.
This parameter can be a value of @ref I2S_WSInversion */
@@ -74,7 +74,7 @@
This parameter can be a value of @ref I2S_Data_24Bit_Alignment */
uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
- This parameter can be a value of @ref SPI_Master_Keep_IO_State */
+ This parameter can be a value of @ref I2S_Master_Keep_IO_State */
} I2S_InitTypeDef;
@@ -88,6 +88,7 @@
HAL_I2S_STATE_BUSY = 0x02UL, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06UL, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07UL /*!< I2S error state */
} HAL_I2S_StateTypeDef;
@@ -98,46 +99,48 @@
typedef struct __I2S_HandleTypeDef
{
SPI_TypeDef *Instance; /*!< I2S registers base address */
-
+
I2S_InitTypeDef Init; /*!< I2S communication parameters */
-
+
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
-
+
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
-
+
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
-
+
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
-
+
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
-
+
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received
NbSamplesReceived = RxBufferSize-RxBufferCount) */
-
+
void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
-
+
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
-
+
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
-
+
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
-
+
__IO uint32_t ErrorCode; /*!< I2S Error code
This parameter can be a value of @ref I2S_Error */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
+ void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
+ void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
@@ -154,8 +157,10 @@
{
HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL, /*!< I2S Tx Completed callback ID */
HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL, /*!< I2S Rx Completed callback ID */
+ HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< I2S TxRx Completed callback ID */
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< I2S Tx Half Completed callback ID */
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< I2S Rx Half Completed callback ID */
+ HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< I2S TxRx Half Completed callback ID */
HAL_I2S_ERROR_CB_ID = 0x06UL, /*!< I2S Error callback ID */
HAL_I2S_MSPINIT_CB_ID = 0x07UL, /*!< I2S Msp Init callback ID */
HAL_I2S_MSPDEINIT_CB_ID = 0x08UL /*!< I2S Msp DeInit callback ID */
@@ -178,7 +183,7 @@
*/
/** @defgroup I2S_Error I2S Error
* @{
- */
+ */
#define HAL_I2S_ERROR_NONE (0x00000000UL) /*!< No error */
#define HAL_I2S_ERROR_TIMEOUT (0x00000001UL) /*!< Timeout error */
#define HAL_I2S_ERROR_OVR (0x00000002UL) /*!< OVR error */
@@ -257,7 +262,7 @@
* @}
*/
-/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
+/** @defgroup I2S_Clock_Polarity I2S FullDuplex Mode
* @{
*/
#define I2S_CPOL_LOW (0x00000000UL)
@@ -307,6 +312,7 @@
*/
#define I2S_IT_RXP SPI_IER_RXPIE
#define I2S_IT_TXP SPI_IER_TXPIE
+#define I2S_IT_DXP SPI_IER_DXPIE
#define I2S_IT_UDR SPI_IER_UDRIE
#define I2S_IT_OVR SPI_IER_OVRIE
#define I2S_IT_FRE SPI_IER_TIFREIE
@@ -320,11 +326,12 @@
*/
#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
+#define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */
#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
-#define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
+#define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
/**
* @}
*/
@@ -401,6 +408,7 @@
* This parameter can be one of the following values:
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
+ * @arg I2S_IT_DXP : Tx-Packet space available interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_FRE : TI mode frame format error interrupt
@@ -440,11 +448,11 @@
* @retval None
*/
#define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
-
/**
* @}
*/
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2S_Exported_Functions
* @{
@@ -475,15 +483,22 @@
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size);
+
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
@@ -494,6 +509,8 @@
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
/**
* @}
@@ -575,6 +592,9 @@
#define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
((__MODE__) == I2S_MODE_SLAVE_RX) || \
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
+
+#define IS_I2S_FULLDUPLEX(__MODE__) (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX) || \
+ ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
((__STANDARD__) == I2S_STANDARD_MSB) || \
diff --git a/Inc/stm32h7xx_hal_i2s_ex.h b/Inc/stm32h7xx_hal_i2s_ex.h
index b3857c6..0f74507 100644
--- a/Inc/stm32h7xx_hal_i2s_ex.h
+++ b/Inc/stm32h7xx_hal_i2s_ex.h
@@ -16,5 +16,13 @@
*
******************************************************************************
*/
- /* The I2S Full duplex feature is not supported by this HAL Driver */
+
+/**
+ ******************************************************************************
+ ===== I2S FULL DUPLEX FEATURE =====
+ I2S Full Duplex APIs are available in stm32h7xx_hal_i2s.c/.h
+ ******************************************************************************
+ */
+
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_mdma.h b/Inc/stm32h7xx_hal_mdma.h
index 354dfac..afd2aeb 100644
--- a/Inc/stm32h7xx_hal_mdma.h
+++ b/Inc/stm32h7xx_hal_mdma.h
@@ -598,8 +598,8 @@
/**
* @brief Checks whether the specified MDMA Channel interrupt is enabled or not.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * @param __HANDLE__: MDMA handle
+ * @param __INTERRUPT__: specifies the MDMA interrupt source to check.
* @arg MDMA_IT_TE : Transfer Error interrupt mask
* @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
* @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
@@ -610,6 +610,21 @@
#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
+ * @brief Writes the number of data in bytes to be transferred on the MDMA Channelx.
+ * @param __HANDLE__ : MDMA handle
+ * @param __COUNTER__: Number of data in bytes to be transferred.
+ * @retval None
+ */
+#define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT))
+
+/**
+ * @brief Returns the number of remaining data in bytes in the current MDMA Channelx transfer.
+ * @param __HANDLE__ : MDMA handle
+ * @retval The number of remaining data in bytes in the current MDMA Channelx transfer.
+ */
+#define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT)
+
+/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_mmc.h b/Inc/stm32h7xx_hal_mmc.h
index a5a8458..b3dc7cc 100644
--- a/Inc/stm32h7xx_hal_mmc.h
+++ b/Inc/stm32h7xx_hal_mmc.h
@@ -358,6 +358,43 @@
* @}
*/
+/** @defgroup MMC_Exported_Constansts_Group5 MMC Erase Type
+ * @{
+ */
+#define HAL_MMC_ERASE 0x00000000U /*!< Erase the erase groups identified by CMD35 & 36 */
+#define HAL_MMC_TRIM 0x00000001U /*!< Erase the write blocks identified by CMD35 & 36 */
+#define HAL_MMC_DISCARD 0x00000003U /*!< Discard the write blocks identified by CMD35 & 36 */
+#define HAL_MMC_SECURE_ERASE 0x80000000U /*!< Perform a secure purge according SRT on the erase groups identified by CMD35 & 36 */
+#define HAL_MMC_SECURE_TRIM_STEP1 0x80000001U /*!< Mark the write blocks identified by CMD35 & 36 for secure erase */
+#define HAL_MMC_SECURE_TRIM_STEP2 0x80008000U /*!< Perform a secure purge according SRT on the write blocks previously identified */
+
+#define IS_MMC_ERASE_TYPE(TYPE) (((TYPE) == HAL_MMC_ERASE) || \
+ ((TYPE) == HAL_MMC_TRIM) || \
+ ((TYPE) == HAL_MMC_DISCARD) || \
+ ((TYPE) == HAL_MMC_SECURE_ERASE) || \
+ ((TYPE) == HAL_MMC_SECURE_TRIM_STEP1) || \
+ ((TYPE) == HAL_MMC_SECURE_TRIM_STEP2))
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group6 MMC Secure Removal Type
+ * @{
+ */
+#define HAL_MMC_SRT_ERASE 0x00000001U /*!< Information removed by an erase */
+#define HAL_MMC_SRT_WRITE_CHAR_ERASE 0x00000002U /*!< Information removed by an overwriting with a character followed by an erase */
+#define HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM 0x00000004U /*!< Information removed by an overwriting with a character, its complement then a random character */
+#define HAL_MMC_SRT_VENDOR_DEFINED 0x00000008U /*!< Information removed using a vendor defined */
+
+
+#define IS_MMC_SRT_TYPE(TYPE) (((TYPE) == HAL_MMC_SRT_ERASE) || \
+ ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_ERASE) || \
+ ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM) || \
+ ((TYPE) == HAL_MMC_SRT_VENDOR_DEFINED))
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -661,7 +698,7 @@
* @}
*/
-/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
+/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management
* @{
*/
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
@@ -670,6 +707,17 @@
* @}
*/
+/** @defgroup MMC_Exported_Functions_Group7 Peripheral Erase management
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode);
+HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT);
+/**
+ * @}
+ */
+
/* Private types -------------------------------------------------------------*/
/** @defgroup MMC_Private_Types MMC Private Types
* @{
diff --git a/Inc/stm32h7xx_hal_mmc_ex.h b/Inc/stm32h7xx_hal_mmc_ex.h
index 2db6b08..b5c9424 100644
--- a/Inc/stm32h7xx_hal_mmc_ex.h
+++ b/Inc/stm32h7xx_hal_mmc_ex.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_MMC_EX_H
@@ -35,7 +35,7 @@
/** @addtogroup MMCEx
* @brief SD HAL extended module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup MMCEx_Exported_Types MMCEx Exported Types
@@ -44,7 +44,7 @@
/** @defgroup MMCEx_Exported_Types_Group1 MMC Internal DMA Buffer structure
* @{
- */
+ */
typedef enum
{
MMC_DMA_BUFFER0 = 0x00U, /*!< selects MMC internal DMA Buffer 0 */
@@ -53,20 +53,20 @@
}HAL_MMCEx_DMABuffer_MemoryTypeDef;
-/**
+/**
* @}
*/
-
-/**
+
+/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions
* @{
*/
-
+
/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
* @{
*/
@@ -83,11 +83,11 @@
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@@ -95,7 +95,7 @@
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
+
/**
* @}
*/
@@ -108,6 +108,6 @@
#endif
-#endif /* STM32H7xx_HAL_MMCEx_H */
+#endif /* STM32H7xx_HAL_MMCEx_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_otfdec.h b/Inc/stm32h7xx_hal_otfdec.h
index 23cde06..ebd4ea7 100644
--- a/Inc/stm32h7xx_hal_otfdec.h
+++ b/Inc/stm32h7xx_hal_otfdec.h
@@ -18,14 +18,13 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_OTFDEC_H
-#define __STM32H7xx_HAL_OTFDEC_H
+#ifndef STM32H7xx_HAL_OTFDEC_H
+#define STM32H7xx_HAL_OTFDEC_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(OTFDEC1)
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
@@ -33,6 +32,8 @@
* @{
*/
+#if defined(OTFDEC1)
+
/** @addtogroup OTFDEC
* @{
*/
@@ -266,6 +267,38 @@
*/
#define __HAL_OTFDEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__))
+ /** @brief Check whether the specified combination of OTFDEC interrupt flags is set or not.
+ * @param __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param __FLAG__ mask on combination of interrupts flags
+ * This parameter can be one of the following values:
+ * @arg @ref OTFDEC_SEC_ERROR_INT OTFDEC security error interrupt flag
+ * @arg @ref OTFDEC_EXE_ERROR_INT OTFDEC execution error interrupt flag
+ * @arg @ref OTFDEC_KEY_ERROR_INT OTFDEC key error interrupt flag
+ * @arg @ref OTFDEC_SEC_EXE_ERROR_INT OTFDEC security and execution errors interrupts flags
+ * @arg @ref OTFDEC_SEC_KEY_ERROR_INT OTFDEC security and key errors interrupts flags
+ * @arg @ref OTFDEC_EXE_KEY_ERROR_INT OTFDEC execution and key errors interrupts flag
+ * @arg @ref OTFDEC_ALL_INT OTFDEC all interrupts flags
+ * @retval The state of __FLAG__ (TRUE or FALSE).
+ */
+ #define __HAL_OTFDEC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified combination of OTFDEC interrupt flags.
+ * @param __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
+ * the configuration information for OTFDEC module
+ * @param __FLAG__ mask on combination of interrupts flags
+ * This parameter can be one of the following values:
+ * @arg @ref OTFDEC_SEC_ERROR_INT OTFDEC security error interrupt flag
+ * @arg @ref OTFDEC_EXE_ERROR_INT OTFDEC execution error interrupt flag
+ * @arg @ref OTFDEC_KEY_ERROR_INT OTFDEC key error interrupt flag
+ * @arg @ref OTFDEC_SEC_EXE_ERROR_INT OTFDEC security and execution errors interrupts flags
+ * @arg @ref OTFDEC_SEC_KEY_ERROR_INT OTFDEC security and key errors interrupts flags
+ * @arg @ref OTFDEC_EXE_KEY_ERROR_INT OTFDEC execution and key errors interrupts flag
+ * @arg @ref OTFDEC_ALL_INT OTFDEC all interrupts flags
+ * @retval None
+ */
+#define __HAL_OTFDEC_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->ICR, (__FLAG__))
+
/**
* @}
*/
@@ -428,17 +461,17 @@
* @}
*/
+#endif /* OTFDEC1 */
/**
* @}
*/
-#endif /* OTFDEC1 */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32H7xx_HAL_OTFDEC_H */
+#endif /* STM32H7xx_HAL_OTFDEC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_pcd.h b/Inc/stm32h7xx_hal_pcd.h
index c90cc16..821f8d9 100644
--- a/Inc/stm32h7xx_hal_pcd.h
+++ b/Inc/stm32h7xx_hal_pcd.h
@@ -96,16 +96,16 @@
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- __IO uint32_t ErrorCode; /*!< PCD Error code */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ __IO uint32_t ErrorCode; /*!< PCD Error code */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
@@ -244,7 +244,7 @@
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
- HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
+ HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
@@ -363,14 +363,6 @@
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 12) /*!< USB FS EXTI Line WakeUp Interrupt */
#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 11) /*!< USB HS EXTI Line WakeUp Interrupt */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
diff --git a/Inc/stm32h7xx_hal_pwr.h b/Inc/stm32h7xx_hal_pwr.h
index 18da4cd..9dbf404 100644
--- a/Inc/stm32h7xx_hal_pwr.h
+++ b/Inc/stm32h7xx_hal_pwr.h
@@ -228,11 +228,11 @@
* Scale 2 mode.
* @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
* Scale 3 mode.
- * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines,
- * configuring Voltage Scale 0 is only possible when Vcore is supplied
- * from LDO (Low DropOut). The SYSCFG Clock must be enabled through
- * __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale
- * 0 using __HAL_PWR_VOLTAGESCALING_CONFIG().
+ * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is
+ * only possible when Vcore is supplied from LDO (Low DropOut). The
+ * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE()
+ * macro before configuring Voltage Scale 0 using
+ * __HAL_PWR_VOLTAGESCALING_CONFIG().
* Transition to Voltage Scale 0 is only possible when the system is
* already in Voltage Scale 1.
* Transition from Voltage Scale 0 is only possible to Voltage Scale 1
@@ -245,16 +245,18 @@
* low power mode.
* @retval None.
*/
-#if defined(PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
+#if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
do { \
__IO uint32_t tmpreg = 0x00; \
+ /* Configure the Voltage Scaling */ \
MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \
/* Delay after setting the voltage scaling */ \
tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \
UNUSED(tmpreg); \
} while(0)
-#else /* All H7 lines except STM32H7Axxx and STM32H7Bxxx lines */
+#else /* 3 power domains devices */
+#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
do { \
__IO uint32_t tmpreg = 0x00; \
@@ -283,7 +285,18 @@
} \
UNUSED(tmpreg); \
} while(0)
-#endif /* PWR_SRDCR_VOS */
+#else /* STM32H72xxx and STM32H73xxx lines */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
+do { \
+ __IO uint32_t tmpreg = 0x00; \
+ /* Configure the Voltage Scaling */ \
+ MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
+ /* Delay after setting the voltage scaling */ \
+ tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
+ UNUSED(tmpreg); \
+} while(0)
+#endif /* defined(SYSCFG_PWRCR_ODEN) */
+#endif /* defined (PWR_SRDCR_VOS) */
/** @brief Check PWR flags are set or not.
* @param __FLAG__ : Specifies the flag to check.
@@ -356,10 +369,10 @@
* family except STM32H7Axxx and STM32H7Bxxx lines.
* The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and
* STM32H7Bxxx lines.
- * The PWR_FLAG_SCUEN flag is used for STM32H743, STM32H753, STM32H742,
- * STM32H750, STM32H7Axx and STM32H7Bxx lines.
- * The PWR_FLAG_SMPSEXTRDY flag is used for dual core and STM32H7AxxQ,
- * STM32H7BxxQ lines.
+ * The PWR_FLAG_SCUEN flag is used for devices that support only LDO
+ * regulator.
+ * The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO
+ * and SMPS regulators.
* @retval The (__FLAG__) state (TRUE or FALSE).
*/
#if defined (DUAL_CORE) /* Dual core lines */
@@ -386,7 +399,25 @@
((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
#else /* Single core lines */
-#if defined (PWR_CPUCR_SBF_D2) /* STM32H743, STM32H753, STM32H742 and STM32H750 lines */
+#if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */
+#if defined (SMPS) /* STM32H725 and STM32H735 lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__) \
+(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
+ ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
+ ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
+ ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
+ ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
+ ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
+ ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
+ ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
+ ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */
#define __HAL_PWR_GET_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
@@ -403,9 +434,10 @@
((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#endif /* defined (SMPS) */
#else /* STM32H7Axxx and STM32H7Bxxx lines */
-#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ SMPS lines */
-#define __HAL_PWR_GET_FLAG(__FLAG__) \
+#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
@@ -420,8 +452,8 @@
((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
-#else /* STM32H7Axx and STM32H7Bxx LDO lines */
-#define __HAL_PWR_GET_FLAG(__FLAG__) \
+#else /* STM32H7Axx and STM32H7Bxx lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
@@ -449,6 +481,8 @@
* @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
* @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
* @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+ * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices
+ * that support GPIOI port.
* @retval The (__FLAG__) state (TRUE or FALSE).
*/
#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
@@ -475,8 +509,9 @@
* @note This parameter is not used for the STM32H7 family and is kept as
* parameter just to maintain compatibility with other families.
* @note This macro clear all CPU flags.
- * For STM32H7Axxx and STM32H7Bxxx lines CPU flags are STOPF and SBF.
- * For dual core lines flags are HOLDxF, STOPF, SBF and SBF_Dx.
+ * For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU
+ * flags are STOPF, SBF, SBF_D1 and SBF_D2.
+ * For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF.
* @retval None.
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
@@ -491,6 +526,8 @@
* @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
* @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
* @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+ * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices
+ * that support GPIOI port.
* @retval None.
*/
#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
@@ -640,44 +677,44 @@
* @{
*/
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
+void HAL_PWR_DeInit (void);
+void HAL_PWR_EnableBkUpAccess (void);
+void HAL_PWR_DisableBkUpAccess (void);
/**
* @}
*/
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions
* @{
*/
/* Peripheral Control functions **********************************************/
/* PVD configuration */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
+void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD (void);
+void HAL_PWR_DisablePVD (void);
/* WakeUp pins configuration */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity);
+void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx);
/* Low Power modes entry */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
+void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode (void);
/* Power PVD IRQ Handler */
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
+void HAL_PWR_PVD_IRQHandler (void);
+void HAL_PWR_PVDCallback (void);
/* Cortex System Control functions *******************************************/
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
+void HAL_PWR_EnableSleepOnExit (void);
+void HAL_PWR_DisableSleepOnExit (void);
+void HAL_PWR_EnableSEVOnPend (void);
+void HAL_PWR_DisableSEVOnPend (void);
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_pwr_ex.h b/Inc/stm32h7xx_hal_pwr_ex.h
index 3286df7..563a875 100644
--- a/Inc/stm32h7xx_hal_pwr_ex.h
+++ b/Inc/stm32h7xx_hal_pwr_ex.h
@@ -46,8 +46,8 @@
typedef struct
{
uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This
- parameter can be a value of @ref
- PWREx_AVD_detection_level
+ parameter can be a value of @ref
+ PWREx_AVD_detection_level
*/
uint32_t Mode; /*!< Mode : Specifies the EXTI operating mode for the AVD
@@ -102,25 +102,37 @@
*/
/* High level and No pull (default configuration) */
#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6
+#if defined (PWR_WKUPEPR_WKUPEN5)
#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5
+#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4
+#if defined (PWR_WKUPEPR_WKUPEN3)
#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3
+#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2
#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1
/* High level and No pull */
#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
+#if defined (PWR_WKUPEPR_WKUPEN5)
#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
+#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
+#if defined (PWR_WKUPEPR_WKUPEN3)
#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
+#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
/* Low level and No pull */
#define PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
+#if defined (PWR_WKUPEPR_WKUPP5)
#define PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
+#endif /* defined (PWR_WKUPEPR_WKUPP5) */
#define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
+#if defined (PWR_WKUPEPR_WKUPP3)
#define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
+#endif /* defined (PWR_WKUPEPR_WKUPP3) */
#define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
#define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
/**
@@ -151,13 +163,22 @@
*/
#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */
#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */
+#if defined (PWR_WKUPFR_WKUPF3)
#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */
+#endif /* defined (PWR_WKUPFR_WKUPF3) */
#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
+#if defined (PWR_WKUPFR_WKUPF5)
#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
+#endif /* defined (PWR_WKUPFR_WKUPF5) */
#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */
+#if defined (PWR_WKUPFR_WKUPF3)
#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\
PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)
+#else
+#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
+ PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF6)
+#endif /* defined (PWR_WKUPFR_WKUPF3) */
/**
* @}
*/
@@ -486,12 +507,12 @@
/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
* @{
*/
-HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
-uint32_t HAL_PWREx_GetSupplyConfig(void);
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
-uint32_t HAL_PWREx_GetVoltageRange(void);
-HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
-uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource);
+uint32_t HAL_PWREx_GetSupplyConfig (void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling);
+uint32_t HAL_PWREx_GetVoltageRange (void);
+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling);
+uint32_t HAL_PWREx_GetStopModeVoltageRange (void);
/**
* @}
*/
@@ -501,63 +522,67 @@
*/
/* System low power control functions */
#if defined (PWR_CPUCR_RETDS_CD)
-void HAL_PWREx_EnterSTOP2Mode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry);
#endif /* defined (PWR_CPUCR_RETDS_CD) */
-void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
-void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
-void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
+void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
+void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain);
+void HAL_PWREx_ConfigD3Domain (uint32_t D3State);
/* Clear Cortex-Mx pending flag */
-void HAL_PWREx_ClearPendingEvent(void);
+void HAL_PWREx_ClearPendingEvent (void);
#if defined (DUAL_CORE)
/* Clear domain flags */
-void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);
+void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags);
/* Core Hold/Release functions */
-HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);
-void HAL_PWREx_ReleaseCore(uint32_t CPU);
+HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU);
+void HAL_PWREx_ReleaseCore (uint32_t CPU);
#endif /* defined (DUAL_CORE) */
/* Flash low power control functions */
-void HAL_PWREx_EnableFlashPowerDown(void);
-void HAL_PWREx_DisableFlashPowerDown(void);
+void HAL_PWREx_EnableFlashPowerDown (void);
+void HAL_PWREx_DisableFlashPowerDown (void);
#if defined (PWR_CR1_SRDRAMSO)
/* Memory shut-off functions */
-void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock);
-void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock);
+void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock);
+void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock);
#endif /* defined(PWR_CR1_SRDRAMSO) */
/* Wakeup Pins control functions */
-void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
-void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
-uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
-HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
+void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams);
+void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin);
+uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag);
+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag);
/* Power Wakeup PIN IRQ Handler */
-void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
-void HAL_PWREx_WKUP1_Callback(void);
-void HAL_PWREx_WKUP2_Callback(void);
-void HAL_PWREx_WKUP3_Callback(void);
-void HAL_PWREx_WKUP4_Callback(void);
-void HAL_PWREx_WKUP5_Callback(void);
-void HAL_PWREx_WKUP6_Callback(void);
+void HAL_PWREx_WAKEUP_PIN_IRQHandler (void);
+void HAL_PWREx_WKUP1_Callback (void);
+void HAL_PWREx_WKUP2_Callback (void);
+#if defined (PWR_WKUPEPR_WKUPEN3)
+void HAL_PWREx_WKUP3_Callback (void);
+#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
+void HAL_PWREx_WKUP4_Callback (void);
+#if defined (PWR_WKUPEPR_WKUPEN5)
+void HAL_PWREx_WKUP5_Callback (void);
+#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
+void HAL_PWREx_WKUP6_Callback (void);
/**
* @}
*/
-/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals Control Functions
+/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions
* @{
*/
/* Backup regulator control functions */
-HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
-HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void);
/* USB regulator control functions */
-HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
-HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
-void HAL_PWREx_EnableUSBVoltageDetector(void);
-void HAL_PWREx_DisableUSBVoltageDetector(void);
+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void);
+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void);
+void HAL_PWREx_EnableUSBVoltageDetector (void);
+void HAL_PWREx_DisableUSBVoltageDetector (void);
/* Battery control functions */
-void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
-void HAL_PWREx_DisableBatteryCharging(void);
-#if defined(PWR_CR1_BOOSTE)
+void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue);
+void HAL_PWREx_DisableBatteryCharging (void);
+#if defined (PWR_CR1_BOOSTE)
/* Analog Booster functions */
-void HAL_PWREx_EnableAnalogBooster(void);
-void HAL_PWREx_DisableAnalogBooster(void);
+void HAL_PWREx_EnableAnalogBooster (void);
+void HAL_PWREx_DisableAnalogBooster (void);
#endif /* PWR_CR1_BOOSTE */
/**
* @}
@@ -567,20 +592,20 @@
* @{
*/
/* Power VBAT/Temperature monitoring functions */
-void HAL_PWREx_EnableMonitoring(void);
-void HAL_PWREx_DisableMonitoring(void);
-uint32_t HAL_PWREx_GetTemperatureLevel(void);
-uint32_t HAL_PWREx_GetVBATLevel(void);
-#if defined(PWR_CSR1_MMCVDO)
-PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage(void);
+void HAL_PWREx_EnableMonitoring (void);
+void HAL_PWREx_DisableMonitoring (void);
+uint32_t HAL_PWREx_GetTemperatureLevel (void);
+uint32_t HAL_PWREx_GetVBATLevel (void);
+#if defined (PWR_CSR1_MMCVDO)
+PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void);
#endif /* PWR_CSR1_MMCVDO */
/* Power AVD configuration functions */
-void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
-void HAL_PWREx_EnableAVD(void);
-void HAL_PWREx_DisableAVD(void);
+void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD);
+void HAL_PWREx_EnableAVD (void);
+void HAL_PWREx_DisableAVD (void);
/* Power PVD/AVD IRQ Handler */
-void HAL_PWREx_PVD_AVD_IRQHandler(void);
-void HAL_PWREx_AVDCallback(void);
+void HAL_PWREx_PVD_AVD_IRQHandler (void);
+void HAL_PWREx_AVDCallback (void);
/**
* @}
*/
@@ -636,6 +661,7 @@
((STATE) == PWR_D3_DOMAIN_RUN))
/* Check wake up pin parameter */
+#if defined (PWR_WKUPEPR_WKUPEN3)
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\
((PIN) == PWR_WAKEUP_PIN2) ||\
((PIN) == PWR_WAKEUP_PIN3) ||\
@@ -654,6 +680,20 @@
((PIN) == PWR_WAKEUP_PIN4_LOW) ||\
((PIN) == PWR_WAKEUP_PIN5_LOW) ||\
((PIN) == PWR_WAKEUP_PIN6_LOW))
+#else
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\
+ ((PIN) == PWR_WAKEUP_PIN2) ||\
+ ((PIN) == PWR_WAKEUP_PIN4) ||\
+ ((PIN) == PWR_WAKEUP_PIN6) ||\
+ ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
+ ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
+ ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
+ ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
+ ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\
+ ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\
+ ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\
+ ((PIN) == PWR_WAKEUP_PIN6_LOW))
+#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
/* Check wake up pin polarity parameter */
#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
@@ -665,6 +705,7 @@
((PULL) == PWR_PIN_PULL_DOWN))
/* Check wake up flag parameter */
+#if defined (PWR_WKUPEPR_WKUPEN3)
#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
((FLAG) == PWR_WAKEUP_FLAG2) ||\
((FLAG) == PWR_WAKEUP_FLAG3) ||\
@@ -672,6 +713,13 @@
((FLAG) == PWR_WAKEUP_FLAG5) ||\
((FLAG) == PWR_WAKEUP_FLAG6) ||\
((FLAG) == PWR_WAKEUP_FLAG_ALL))
+#else
+#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
+ ((FLAG) == PWR_WAKEUP_FLAG2) ||\
+ ((FLAG) == PWR_WAKEUP_FLAG4) ||\
+ ((FLAG) == PWR_WAKEUP_FLAG6) ||\
+ ((FLAG) == PWR_WAKEUP_FLAG_ALL))
+#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
/* Check wake up flag parameter */
#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\
diff --git a/Inc/stm32h7xx_hal_rcc.h b/Inc/stm32h7xx_hal_rcc.h
index dc360b0..f4d896d 100644
--- a/Inc/stm32h7xx_hal_rcc.h
+++ b/Inc/stm32h7xx_hal_rcc.h
@@ -211,11 +211,7 @@
#define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION) /*!< HSI_DIV8 clock activation */
-#if defined(RCC_HSICFGR_HSITRIM_6)
-#define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value, for STM32H7 rev.V and above */
-#else
-#define RCC_HSICALIBRATION_DEFAULT (0x20U) /* Default HSI calibration trimming value, for STM32H7 rev.Y */
-#endif
+#define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value for STM32H7 rev.V and above. (0x20 value for rev.Y handled within __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST macro ) */
/**
* @}
*/
@@ -246,11 +242,7 @@
#define RCC_CSI_OFF (0x00000000U)
#define RCC_CSI_ON RCC_CR_CSION
-#if defined(RCC_CSICFGR_CSITRIM_5)
-#define RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value */
-#else
-#define RCC_CSICALIBRATION_DEFAULT (0x10U) /* Default CSI calibration trimming value */
-#endif /* RCC_CSICFGR_CSITRIM_5 */
+#define RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value for STM32H7 rev.V and above. (0x10 value for rev.Y handled within __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST macro ) */
/**
* @}
*/
@@ -1212,6 +1204,26 @@
UNUSED(tmpreg); \
} while(0)
+#if defined(FMAC)
+#define __HAL_RCC_FMAC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* FMAC */
+
+#if defined(CORDIC)
+#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* CORDIC */
+
#if defined(RCC_AHB2ENR_D2SRAM1EN)
#define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1292,6 +1304,12 @@
#endif /* HASH */
#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#if defined(FMAC)
+#define __HAL_RCC_FMAC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_FMACEN))
+#endif /* FMAC */
+#if defined(CORDIC)
+#define __HAL_RCC_CORDIC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CORDICEN))
+#endif /* CORDIC */
#if defined(RCC_AHB2ENR_D2SRAM1EN)
#define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
#else
@@ -1332,6 +1350,12 @@
#endif /* HASH */
#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)
#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)
+#if defined(FMAC)
+#define __HAL_RCC_FMAC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) != 0U)
+#endif /* FMAC */
+#if defined(CORDIC)
+#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) != 0U)
+#endif /* CORDIC */
#if defined(RCC_AHB2ENR_D2SRAM1EN)
#define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)
#else
@@ -1366,6 +1390,12 @@
#endif /* HASH */
#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)
#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)
+#if defined(FMAC)
+#define __HAL_RCC_FMAC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) == 0U)
+#endif /* FMAC */
+#if defined(CORDIC)
+#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) == 0U)
+#endif /* CORDIC */
#if defined(RCC_AHB2ENR_D2SRAM1EN)
#define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)
#else
@@ -1456,6 +1486,7 @@
UNUSED(tmpreg); \
} while(0)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
@@ -1463,6 +1494,7 @@
tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
UNUSED(tmpreg); \
} while(0)
+#endif /* GPIOI */
#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1557,7 +1589,9 @@
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#endif /* GPIOI */
#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
#if defined(RCC_AHB4ENR_CRCEN)
@@ -1595,7 +1629,9 @@
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U)
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U)
#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U)
+#endif /* GPIOI */
#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U)
#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U)
#if defined(RCC_AHB4ENR_CRCEN)
@@ -1626,7 +1662,9 @@
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U)
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U)
#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U)
+#endif /* GPIOI */
#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U)
#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U)
@@ -1891,6 +1929,16 @@
UNUSED(tmpreg); \
} while(0)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* I2C5 */
+
#define __HAL_RCC_CEC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
@@ -1963,6 +2011,25 @@
UNUSED(tmpreg); \
} while(0)
+#if defined(TIM23)
+#define __HAL_RCC_TIM23_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* TIM23 */
+
+#if defined(TIM24)
+#define __HAL_RCC_TIM24_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#endif /* TIM24 */
#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
@@ -1989,6 +2056,9 @@
#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C5EN)
+#endif /* I2C5 */
#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
@@ -1998,6 +2068,12 @@
#define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+#if defined(TIM23)
+#define __HAL_RCC_TIM23_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM23EN)
+#endif /* TIM23 */
+#if defined(TIM24)
+#define __HAL_RCC_TIM24_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM24EN)
+#endif /* TIM24 */
/** @brief Get the enable or disable status of the APB1 peripheral clock
@@ -2029,6 +2105,9 @@
#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U)
#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U)
#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) != 0U)
+#endif /* I2C5 */
#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U)
#define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U)
#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U)
@@ -2038,6 +2117,12 @@
#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U)
#define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U)
#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U)
+#if defined(TIM23)
+#define __HAL_RCC_TIM23_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) != 0U)
+#endif /* TIM23 */
+#if defined(TIM24)
+#define __HAL_RCC_TIM24_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) != 0U)
+#endif /* TIM24 */
#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U)
#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U)
@@ -2062,6 +2147,9 @@
#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U)
#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U)
#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) == 0U)
+#endif /* I2C5 */
#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U)
#define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U)
#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U)
@@ -2071,6 +2159,12 @@
#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U)
#define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U)
#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U)
+#if defined(TIM23)
+#define __HAL_RCC_TIM23_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) == 0U)
+#endif /* TIM23 */
+#if defined(TIM24)
+#define __HAL_RCC_TIM24_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) == 0U)
+#endif /* TIM24 */
/** @brief Enable or disable the APB2 peripheral clock.
@@ -2187,6 +2281,7 @@
UNUSED(tmpreg); \
} while(0)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
@@ -2194,6 +2289,7 @@
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
UNUSED(tmpreg); \
} while(0)
+#endif /*SAI2*/
#if defined(SAI3)
#define __HAL_RCC_SAI3_CLK_ENABLE() do { \
@@ -2240,7 +2336,9 @@
#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#endif /*SAI2*/
#if defined(SAI3)
#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
#endif /*SAI3*/
@@ -2272,7 +2370,9 @@
#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U)
#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)
#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U)
+#endif /*SAI2*/
#if defined(SAI3)
#define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U)
#endif /* SAI3 */
@@ -2298,7 +2398,9 @@
#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U)
#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)
#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U)
+#endif /*SAI2*/
#if defined(SAI3)
#define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U)
#endif /*SAI3*/
@@ -4559,7 +4661,13 @@
/** @brief Enable or disable the AHB3 peripheral reset.
*/
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x7FFFFFFFU)
+#if (STM32H7_DEV_ID == 0x450UL)
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00015031U) /* Resets MDMA, DMA2D, JPEG, FMC, QSPI and SDMMC1 */
+#elif (STM32H7_DEV_ID == 0x480UL)
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x01E95031U) /* Resets MDMA, DMA2D, JPEG, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 and GFXMMU */
+#else
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00E95011U) /* Resets MDMA, DMA2D, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 */
+#endif /* STM32H7_DEV_ID == 0x450UL */
#define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
#if defined(JPEG)
@@ -4623,7 +4731,13 @@
/** @brief Force or release the AHB1 peripheral reset.
*/
-#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#if (STM32H7_DEV_ID == 0x450UL)
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0A00C023U) /* Resets DMA1, DMA2, ADC12, ART, ETHMAC, USB1OTG and USB2OTG */
+#elif (STM32H7_DEV_ID == 0x480UL)
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02000223U) /* Resets DMA1, DMA2, ADC12, CRC and USB1OTG */
+#else
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02008023U) /* Resets DMA1, DMA2, ADC12, ETHMAC and USB1OTG */
+#endif /* STM32H7_DEV_ID == 0x450UL */
#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
@@ -4661,7 +4775,13 @@
/** @brief Force or release the AHB2 peripheral reset.
*/
-#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#if (STM32H7_DEV_ID == 0x450UL)
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000271U) /* Resets DCMI, CRYPT, HASH, RNG and SDMMC2 */
+#elif (STM32H7_DEV_ID == 0x480UL)
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000A75U) /* Resets DCMI_PSSI, HSEM, CRYPT, HASH, RNG, SDMMC2 and BDMA1 */
+#else
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00030271U) /* Resets DCMI_PSSI, CRYPT, HASH, RNG, SDMMC2, FMAC and CORDIC */
+#endif /* STM32H7_DEV_ID == 0x450UL */
#if defined(DCMI) && defined(PSSI)
#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))
#define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/
@@ -4676,6 +4796,12 @@
#endif /* HASH */
#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
+#if defined(FMAC)
+#define __HAL_RCC_FMAC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_FMACRST))
+#endif /*FMAC*/
+#if defined(CORDIC)
+#define __HAL_RCC_CORDIC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CORDICRST))
+#endif /*CORDIC*/
#if defined(RCC_AHB2RSTR_HSEMRST)
#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))
#endif
@@ -4698,6 +4824,12 @@
#endif /* HASH */
#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
+#if defined(FMAC)
+#define __HAL_RCC_FMAC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_FMACRST))
+#endif /*FMAC*/
+#if defined(CORDIC)
+#define __HAL_RCC_CORDIC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CORDICRST))
+#endif /*CORDIC*/
#if defined(RCC_AHB2RSTR_HSEMRST)
#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))
#endif
@@ -4709,7 +4841,13 @@
/** @brief Force or release the AHB4 peripheral reset.
*/
-#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0xFFFFFFFFU)
+#if (STM32H7_DEV_ID == 0x450UL)
+#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032807FFU) /* Resets GPIOA..GPIOK, CRC, BDMA, ADC3 and HSEM */
+#elif (STM32H7_DEV_ID == 0x480UL)
+#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x002007FFU) /* Resets GPIOA..GPIOK and BDMA2 */
+#else
+#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032806FFU) /* Resets GPIOA..GPIOH, GPIOJ, GPIOK, CRC, BDMA, ADC3 and HSEM */
+#endif /* STM32H7_DEV_ID == 0x450UL */
#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
@@ -4718,7 +4856,9 @@
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
+#endif /* GPIOI */
#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
#if defined(RCC_AHB4RSTR_CRCRST)
@@ -4746,7 +4886,9 @@
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
+#endif /* GPIOI */
#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
#if defined(RCC_AHB4RSTR_CRCRST)
@@ -4767,7 +4909,11 @@
/** @brief Force or release the APB3 peripheral reset.
*/
-#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0xFFFFFFFFU)
+#if (STM32H7_DEV_ID == 0x450UL)
+#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000018U) /* Rests LTDC and DSI */
+#else
+#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000008U) /* Rests LTDC */
+#endif /* STM32H7_DEV_ID == 0x450UL */
#if defined(LTDC)
#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
#endif /* LTDC */
@@ -4785,8 +4931,16 @@
/** @brief Force or release the APB1 peripheral reset.
*/
-#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0xFFFFFFFFU)
+#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL)
+#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xE8FFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, CEC, DAC1(2), UART7 and UART8 */
+#else
+#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xEAFFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, I2C5, CEC, DAC12, UART7 and UART8 */
+#endif /* STM32H7_DEV_ID == 0x450UL */
+#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL)
+#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x00000136U) /* Resets CRS, SWP, OPAMP, MDIOS and FDCAN */
+#else
+#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x03000136U) /* Resets CRS, SWP, OPAMP, MDIOS, FDCAN, TIM23 and TIM24 */
+#endif /* STM32H7_DEV_ID == 0x450UL */
#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
@@ -4807,6 +4961,9 @@
#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C5RST)
+#endif /* I2C5 */
#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
#define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
@@ -4816,6 +4973,12 @@
#define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
#define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
#define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
+#if defined(TIM23)
+#define __HAL_RCC_TIM23_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM23RST)
+#endif /* TIM23 */
+#if defined(TIM24)
+#define __HAL_RCC_TIM24_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM24RST)
+#endif /* TIM24 */
#define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U)
#define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U)
@@ -4839,6 +5002,9 @@
#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C5RST)
+#endif /* I2C5 */
#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
#define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
@@ -4848,10 +5014,22 @@
#define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
#define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
#define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
+#if defined(TIM23)
+#define __HAL_RCC_TIM23_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM23RST)
+#endif /* TIM23 */
+#if defined(TIM24)
+#define __HAL_RCC_TIM24_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM24RST)
+#endif /* TIM24 */
/** @brief Force or release the APB2 peripheral reset.
*/
-#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
+#if (STM32H7_DEV_ID == 0x450UL)
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x31D73033U) /* Resets TIM1, TIM8, USART1, USART6, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1..SAI3, DFSDM1 and HRTIM */
+#elif (STM32H7_DEV_ID == 0x480UL)
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x40D730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1, SAI2 and DFSDM1 */
+#else
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x405730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1 and DFSDM1 */
+#endif /* STM32H7_DEV_ID == 0x450UL */
#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
@@ -4869,7 +5047,9 @@
#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
+#endif /* SAI2 */
#if defined(SAI3)
#define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
#endif /*SAI3*/
@@ -4896,7 +5076,9 @@
#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
+#endif /* SAI2 */
#if defined(SAI3)
#define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
#endif /*SAI3*/
@@ -4908,7 +5090,13 @@
/** @brief Force or release the APB4 peripheral reset.
*/
-#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0xFFFFFFFFU)
+#if (STM32H7_DEV_ID == 0x450UL)
+#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0020DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF and SAI4 */
+#elif (STM32H7_DEV_ID == 0x480UL)
+#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0C00E6AAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2, LPTIM3, DAC2, COMP12, VREF, DTS and DFSDM2 */
+#else
+#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0420DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF, SAI4 and DTS */
+#endif /* STM32H7_DEV_ID == 0x450UL */
#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
@@ -5290,6 +5478,12 @@
#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))
#endif
+#if defined(FMAC)
+#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_FMACLPEN))
+#endif /* FMAC */
+#if defined(CORDIC)
+#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CORDICLPEN))
+#endif /* CORDIC */
#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
#else
@@ -5321,6 +5515,12 @@
#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))
#endif
+#if defined(FMAC)
+#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_FMACLPEN))
+#endif /* FMAC */
+#if defined(CORDIC)
+#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CORDICLPEN))
+#endif /* CORDIC */
#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
#else
@@ -5359,6 +5559,12 @@
#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)
#endif
+#if defined(FMAC)
+#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) != 0U)
+#endif /* FMAC */
+#if defined(CORDIC)
+#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) != 0U)
+#endif /* CORDIC */
#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)
#else
@@ -5390,6 +5596,12 @@
#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
#endif
#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U)
+#if defined(FMAC)
+#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) == 0U)
+#endif /* FMAC */
+#if defined(CORDIC)
+#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) == 0U)
+#endif /* CORDIC */
#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)
#else
@@ -5420,7 +5632,9 @@
#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#endif /* GPIOI */
#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
#if defined(RCC_AHB4LPENR_CRCLPEN)
@@ -5451,7 +5665,9 @@
#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#endif /* GPIOI */
#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
#if defined(RCC_AHB4LPENR_CRCLPEN)
@@ -5490,7 +5706,9 @@
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U)
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U)
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U)
+#endif /* GPIOI */
#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U)
#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U)
#if defined(RCC_AHB4LPENR_CRCLPEN)
@@ -5521,7 +5739,9 @@
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U)
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U)
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U)
+#if defined(GPIOI)
#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U)
+#endif /* GPIOI */
#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U)
#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U)
#if defined(RCC_AHB4LPENR_CRCLPEN)
@@ -5625,6 +5845,9 @@
#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C5LPEN)
+#endif /* I2C5 */
#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
@@ -5634,6 +5857,12 @@
#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+#if defined(TIM23)
+#define __HAL_RCC_TIM23_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM23LPEN)
+#endif /* TIM23 */
+#if defined(TIM24)
+#define __HAL_RCC_TIM24_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM24LPEN)
+#endif /* TIM24 */
#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
@@ -5661,6 +5890,9 @@
#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C5LPEN)
+#endif /* I2C5 */
#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
@@ -5670,6 +5902,12 @@
#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+#if defined(TIM23)
+#define __HAL_RCC_TIM23_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM23LPEN)
+#endif /* TIM23 */
+#if defined(TIM24)
+#define __HAL_RCC_TIM24_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM24LPEN)
+#endif /* TIM24 */
/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.
@@ -5702,6 +5940,9 @@
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U)
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U)
#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) != 0U)
+#endif /* I2C5 */
#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U)
#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U)
#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U)
@@ -5711,6 +5952,12 @@
#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U)
#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U)
#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U)
+#if defined(TIM23)
+#define __HAL_RCC_TIM23_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) != 0U)
+#endif /* TIM23 */
+#if defined(TIM24)
+#define __HAL_RCC_TIM24_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) != 0U)
+#endif /* TIM24 */
#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U)
#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U)
@@ -5735,6 +5982,9 @@
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U)
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U)
#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U)
+#if defined(I2C5)
+#define __HAL_RCC_I2C5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) == 0U)
+#endif /* I2C5 */
#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U)
#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U)
#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U)
@@ -5744,6 +5994,12 @@
#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U)
#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U)
#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U)
+#if defined(TIM23)
+#define __HAL_RCC_TIM23_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) == 0U)
+#endif /* TIM23 */
+#if defined(TIM24)
+#define __HAL_RCC_TIM24_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) == 0U)
+#endif /* TIM24 */
/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
@@ -5770,7 +6026,9 @@
#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#endif /* SAI2 */
#if defined(SAI3)
#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
#endif /*SAI3*/
@@ -5796,7 +6054,9 @@
#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#endif /* SAI2 */
#if defined(SAI3)
#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
#endif /*SAI3*/
@@ -5830,7 +6090,9 @@
#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U)
#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U)
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U)
+#endif /* SAI2 */
#if defined(SAI3)
#define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U)
#endif /*SAI3*/
@@ -5856,7 +6118,9 @@
#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U)
#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U)
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U)
+#if defined(SAI2)
#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U)
+#endif /* SAI2 */
#if defined(SAI3)
#define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U)
#endif /*SAI3*/
@@ -6638,6 +6902,9 @@
#if defined(ADC3)
#define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
#endif
+#if defined(RCC_D3AMR_DTSAMEN)
+#define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_DTSAMEN)
+#endif
#if defined(RCC_D3AMR_BKPRAMAMEN)
#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
#endif
@@ -6733,6 +7000,9 @@
#if defined(ADC3)
#define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN)
#endif
+#if defined(RCC_D3AMR_DTSAMEN)
+#define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_DTSAMEN)
+#endif
#if defined(RCC_D3AMR_BKPRAMAMEN)
#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
#endif
@@ -6788,12 +7058,7 @@
#if defined(RCC_CKGAENR_AXICKG)
- /** @brief Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).
- * @note
- * @note
- * @note
- * @param
- * @note
+/** @brief Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).
*/
#define __HAL_RCC_AXI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)
@@ -6909,8 +7174,15 @@
do { \
if(HAL_GetREVID() <= REV_ID_Y) \
{ \
+ if((__HSICalibrationValue__) == RCC_HSICALIBRATION_DEFAULT) \
+ { \
+ MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, ((uint32_t)0x20) << HAL_RCC_REV_Y_HSITRIM_Pos); \
+ } \
+ else \
+ { \
MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos); \
} \
+ } \
else \
{ \
MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); \
@@ -6975,7 +7247,14 @@
do { \
if(HAL_GetREVID() <= REV_ID_Y) \
{ \
- MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \
+ if((__CSICalibrationValue__) == RCC_CSICALIBRATION_DEFAULT) \
+ { \
+ MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, ((uint32_t)0x10) << HAL_RCC_REV_Y_CSITRIM_Pos); \
+ } \
+ else \
+ { \
+ MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \
+ } \
} \
else \
{ \
@@ -7242,11 +7521,13 @@
* (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).
* @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted
* This parameter can be one of the following values:
- * @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 400MHZ or 280MHZ(*)
- * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
- * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+ * @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
+ * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
+ * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
*
- * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+ * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
+ * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
+ * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
*
* @retval None
*/
@@ -7288,7 +7569,7 @@
* between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
*
* @param __PLLP1__: specifies the division factor for system clock.
- * This parameter must be a number between 2 and 128 (where odd numbers are not allowed)
+ * This parameter must be a number between 2 or 1(**) and 128 (where odd numbers are not allowed)
*
* @param __PLLQ1__: specifies the division factor for peripheral kernel clocks
* This parameter must be a number between 1 and 128
@@ -7302,6 +7583,7 @@
* @retval None
*
* (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+ * (**): For stm32h72xxx and stm32h73xxx family lines.
*/
diff --git a/Inc/stm32h7xx_hal_rcc_ex.h b/Inc/stm32h7xx_hal_rcc_ex.h
index 9d62e9e..cab6039 100644
--- a/Inc/stm32h7xx_hal_rcc_ex.h
+++ b/Inc/stm32h7xx_hal_rcc_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -227,8 +227,13 @@
uint32_t RngClockSelection; /*!< Specifies RNG clock source
This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
+#if defined(I2C5)
+ uint32_t I2c1235ClockSelection; /*!< Specifies I2C1/2/3/5 clock source
+ This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */
+#else
uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source
- This parameter can be a value of @ref RCCEx_I2C123_Clock_Source */
+ This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */
+#endif /*I2C5*/
uint32_t UsbClockSelection; /*!< Specifies USB clock source
This parameter can be a value of @ref RCCEx_USB_Clock_Source */
@@ -276,6 +281,13 @@
This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
}RCC_PeriphCLKInitTypeDef;
+/*!< Alias for Inter STM32H7 lines compatibility regarding RCC_PeriphCLKInitTypeDef field : I2C5 available on some lines only */
+#if defined(I2C5)
+#define I2c123ClockSelection I2c1235ClockSelection
+#else
+#define I2c1235ClockSelection I2c123ClockSelection
+#endif /*I2C5*/
+
/**
* @brief RCC_CRS Init structure definition
@@ -362,11 +374,23 @@
#define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578
#define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578
#define RCC_PERIPHCLK_LPUART1 (0x00000004U)
+#if defined(I2C5)
+#define RCC_PERIPHCLK_I2C1235 (0x00000008U)
+#define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C1235
+#define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C1235
+#define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C1235
+/* alias */
+#define RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C1235
+#else
#define RCC_PERIPHCLK_I2C123 (0x00000008U)
#define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123
#define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123
#define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123
+#endif /*I2C5*/
#define RCC_PERIPHCLK_I2C4 (0x00000010U)
+#if defined(I2C5)
+#define RCC_PERIPHCLK_I2C5 RCC_PERIPHCLK_I2C1235
+#endif /*I2C5*/
#define RCC_PERIPHCLK_LPTIM1 (0x00000020U)
#define RCC_PERIPHCLK_LPTIM2 (0x00000040U)
#define RCC_PERIPHCLK_LPTIM345 (0x00000080U)
@@ -517,7 +541,7 @@
#define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2
#define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
-#else
+#elif defined(RCC_CDCCIP2R_USART16910SEL)
#define RCC_USART16910CLKSOURCE_CDPCLK2 (0x00000000U)
/* alias */
#define RCC_USART16910CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_CDPCLK2
@@ -536,6 +560,23 @@
#define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI
#define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI
#define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE
+
+#else /* RCC_D2CCIP2R_USART16910SEL */
+#define RCC_USART16910CLKSOURCE_D2PCLK2 (0x00000000U)
+#define RCC_USART16910CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16910SEL_0
+#define RCC_USART16910CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16910SEL_1
+#define RCC_USART16910CLKSOURCE_HSI (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)
+#define RCC_USART16910CLKSOURCE_CSI RCC_D2CCIP2R_USART16910SEL_2
+#define RCC_USART16910CLKSOURCE_LSE (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)
+
+/* Aliases */
+#define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2
+#define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2
+#define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2
+#define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3
+#define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI
+#define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI
+#define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE
#endif /* RCC_D2CCIP2R_USART16SEL */
/**
* @}
@@ -736,7 +777,7 @@
* @}
*/
-/** @defgroup RCCEx_I2C123_Clock_Source RCCEx I2C1/2/3 Clock Source
+/** @defgroup RCCEx_I2C1235_Clock_Source RCCEx I2C1/2/3/5 Clock Source
* @{
*/
#if defined (RCC_D2CCIP2R_I2C123SEL)
@@ -744,13 +785,33 @@
#define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
#define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
#define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
-#else
+/* aliases */
+#define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
+#elif defined(RCC_CDCCIP2R_I2C123SEL)
#define RCC_I2C123CLKSOURCE_CDPCLK1 (0x00000000U)
/* alias */
#define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_CDPCLK1
#define RCC_I2C123CLKSOURCE_PLL3 RCC_CDCCIP2R_I2C123SEL_0
#define RCC_I2C123CLKSOURCE_HSI RCC_CDCCIP2R_I2C123SEL_1
#define RCC_I2C123CLKSOURCE_CSI (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
+/* aliases */
+#define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
+#elif defined(I2C5)
+#define RCC_I2C1235CLKSOURCE_D2PCLK1 (0x00000000U)
+#define RCC_I2C1235CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C1235SEL_0
+#define RCC_I2C1235CLKSOURCE_HSI RCC_D2CCIP2R_I2C1235SEL_1
+#define RCC_I2C1235CLKSOURCE_CSI (RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)
+/* aliases */
+#define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
+#define RCC_I2C123CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
+#define RCC_I2C123CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
+#define RCC_I2C123CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
#endif /* RCC_D2CCIP2R_I2C123SEL */
/**
* @}
@@ -759,10 +820,17 @@
/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
* @{
*/
+#if defined(I2C5)
+#define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
+#define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
+#define RCC_I2C1CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
+#define RCC_I2C1CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
+#else
#define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
#define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
#define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
#define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
+#endif /*I2C5*/
/**
* @}
@@ -771,10 +839,17 @@
/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
* @{
*/
+#if defined(I2C5)
+#define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
+#define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
+#define RCC_I2C2CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
+#define RCC_I2C2CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
+#else
#define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
#define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
#define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
#define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
+#endif /*I2C5*/
/**
* @}
@@ -783,10 +858,17 @@
/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
* @{
*/
+#if defined(I2C5)
+#define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
+#define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
+#define RCC_I2C3CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
+#define RCC_I2C3CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
+#else
#define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
#define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
#define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
#define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
+#endif /*I2C5*/
/**
* @}
@@ -812,6 +894,19 @@
/**
* @}
*/
+#if defined(I2C5)
+/** @defgroup RCCEx_I2C5_Clock_Source RCCEx I2C5 Clock Source
+ * @{
+ */
+#define RCC_I2C5CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
+#define RCC_I2C5CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
+#define RCC_I2C5CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
+#define RCC_I2C5CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
+
+/**
+ * @}
+ */
+#endif /*I2C5*/
/** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source
* @{
@@ -921,7 +1016,7 @@
#endif /* SAI3 */
#if defined(RCC_CDCCIP1R_SAI2ASEL)
-/** @defgroup RCCEx_SAI2_Clock_A Source SAI2A Clock Source
+/** @defgroup RCCEx_SAI2A_Clock_Source SAI2A Clock Source
* @{
*/
#define RCC_SAI2ACLKSOURCE_PLL (0x00000000U)
@@ -936,7 +1031,7 @@
#endif /* RCC_CDCCIP1R_SAI2ASEL */
#if defined(RCC_CDCCIP1R_SAI2BSEL)
-/** @defgroup RCCEx_SAI2_Block_B Clock_Source SAI2B Clock Source
+/** @defgroup RCCEx_SAI2B_Clock_Source SAI2B Clock Source
* @{
*/
#define RCC_SAI2BCLKSOURCE_PLL (0x00000000U)
@@ -1102,6 +1197,9 @@
#define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1
#define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
#define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2
+#if defined(RCC_VER_3_0)
+#define RCC_SAI4ACLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)
+#endif /*RCC_VER_3_0*/
/**
* @}
@@ -1119,6 +1217,9 @@
#define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1
#define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
#define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2
+#if defined(RCC_VER_3_0)
+#define RCC_SAI4BCLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)
+#endif /* RCC_VER_3_0 */
/**
* @}
@@ -1271,6 +1372,8 @@
/** @defgroup RCCEx_OSPI_Clock_Source RCCEx OSPI Clock Source
* @{
*/
+
+#if defined(RCC_CDCCIPR_OCTOSPISEL)
#define RCC_OSPICLKSOURCE_CDHCLK (0x00000000U)
/*aliases*/
#define RCC_OSPICLKSOURCE_D1HCLK RCC_OSPICLKSOURCE_CDHCLK
@@ -1278,6 +1381,14 @@
#define RCC_OSPICLKSOURCE_PLL RCC_CDCCIPR_OCTOSPISEL_0
#define RCC_OSPICLKSOURCE_PLL2 RCC_CDCCIPR_OCTOSPISEL_1
#define RCC_OSPICLKSOURCE_CLKP RCC_CDCCIPR_OCTOSPISEL
+#else
+#define RCC_OSPICLKSOURCE_D1HCLK (0x00000000U)
+#define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_D1HCLK
+#define RCC_OSPICLKSOURCE_PLL RCC_D1CCIPR_OCTOSPISEL_0
+#define RCC_OSPICLKSOURCE_PLL2 RCC_D1CCIPR_OCTOSPISEL_1
+#define RCC_OSPICLKSOURCE_CLKP RCC_D1CCIPR_OCTOSPISEL
+#endif /* RCC_CDCCIPR_OCTOSPISEL */
+
/**
* @}
@@ -1514,7 +1625,7 @@
/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
* @{
*/
-#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
+#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */
/**
* @}
*/
@@ -1662,11 +1773,13 @@
* This is mainly used to save Power.
* @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted
* This parameter can be one of the following values:
- * @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
- * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
- * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+ * @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
+ * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
+ * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
*
- * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+ * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
+ * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
+ * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
*
* @retval None
*/
@@ -1791,11 +1904,13 @@
* This is mainly used to save Power.
* @param __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted
* This parameter can be one of the following values:
- * @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
- * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
- * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+ * @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
+ * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
+ * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
*
- * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+ * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
+ * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
+ * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
*
* @retval None
*/
@@ -2137,34 +2252,47 @@
#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
#endif /* SAI4_Block_B */
-/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).
+/** @brief macro to configure the I2C1/2/3/5* clock (I2C123CLK).
*
- * @param __I2C123CLKSource__ specifies the I2C1/2/3 clock source.
+ * @param __I2C1235CLKSource__ specifies the I2C1/2/3/5* clock source.
* This parameter can be one of the following values:
- * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
+ * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock
+ * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock
+ * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock
+ * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock
+ *
+ * (**): Available on stm32h72xxx and stm32h73xxx family lines.
*/
#if defined(RCC_D2CCIP2R_I2C123SEL)
-#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
-#else
-#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
- MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
+#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__))
+#elif defined(RCC_CDCCIP2R_I2C123SEL)
+#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \
+ MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__))
+#else /* RCC_D2CCIP2R_I2C1235SEL */
+#define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__))
+/* alias */
+#define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG
#endif /* RCC_D2CCIP2R_I2C123SEL */
-/** @brief macro to get the I2C1/2/3 clock source.
+/** @brief macro to get the I2C1/2/3/5* clock source.
* @retval The clock source can be one of the following values:
- * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
- * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
+ * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock
+ * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock
+ * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock
+ * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock
+ *
+ * (**): Available on stm32h72xxx and stm32h73xxx family lines.
*/
#if defined(RCC_D2CCIP2R_I2C123SEL)
#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
-#else
+#elif defined(RCC_CDCCIP2R_I2C123SEL)
#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))
+#else /* RCC_D2CCIP2R_I2C1235SEL */
+#define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL)))
+/* alias */
+#define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
#endif /* RCC_D2CCIP2R_I2C123SEL */
/** @brief macro to configure the I2C1 clock (I2C1CLK).
@@ -2176,7 +2304,11 @@
* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
* @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
*/
+#if defined(I2C5)
+#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG
+#else
#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG
+#endif /*I2C5*/
/** @brief macro to get the I2C1 clock source.
* @retval The clock source can be one of the following values:
@@ -2185,7 +2317,11 @@
* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
* @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
*/
+#if defined(I2C5)
+#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
+#else
#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+#endif /*I2C5*/
/** @brief macro to configure the I2C2 clock (I2C2CLK).
*
@@ -2196,7 +2332,11 @@
* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
* @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
*/
+#if defined(I2C5)
+#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG
+#else
#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG
+#endif /*I2C5*/
/** @brief macro to get the I2C2 clock source.
* @retval The clock source can be one of the following values:
@@ -2205,7 +2345,11 @@
* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
* @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
*/
+#if defined(I2C5)
+#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
+#else
#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+#endif /*I2C5*/
/** @brief macro to configure the I2C3 clock (I2C3CLK).
*
@@ -2216,7 +2360,11 @@
* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
* @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
*/
+#if defined(I2C5)
+#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG
+#else
#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG
+#endif /*I2C5*/
/** @brief macro to get the I2C3 clock source.
* @retval The clock source can be one of the following values:
@@ -2225,7 +2373,11 @@
* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
* @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
*/
+#if defined(I2C5)
+#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
+#else
#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+#endif /*I2C5*/
/** @brief macro to configure the I2C4 clock (I2C4CLK).
*
@@ -2253,9 +2405,33 @@
*/
#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
+#if defined(I2C5)
+/** @brief macro to configure the I2C5 clock (I2C5CLK).
+ *
+ * @param __I2C5CLKSource__ specifies the I2C5 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C5 clock
+ * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock
+ * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock
+ * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock
+ */
+#define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG
+#endif /* I2C5 */
+
+#if defined(I2C5)
+/** @brief macro to get the I2C5 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK5 selected as I2C5 clock
+ * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock
+ * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock
+ * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock
+ */
+#define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
+#endif /* I2C5 */
+
/** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK).
*
- * @param __USART16CLKSource__ specifies the USART1/6/9* /10* clock source.
+ * @param __USART16910CLKSource__ specifies the USART1/6/9* /10* clock source.
* This parameter can be one of the following values:
* @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
* @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
@@ -2267,13 +2443,18 @@
* (*) : Available on some STM32H7 lines only.
*/
#if defined(RCC_D2CCIP2R_USART16SEL)
-#define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))
-#else
+#define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__))
+#elif defined(RCC_CDCCIP2R_USART16910SEL)
#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
/* alias */
#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG
+#else /* RCC_D2CCIP2R_USART16910SEL */
+#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
+ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
+/* alias */
+#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG
#endif /* RCC_D2CCIP2R_USART16SEL */
/** @brief macro to get the USART1/6/9* /10* clock source.
@@ -2289,10 +2470,14 @@
*/
#if defined(RCC_D2CCIP2R_USART16SEL)
#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
-#else
+#elif defined(RCC_CDCCIP2R_USART16910SEL)
#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))
/* alias*/
#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE
+#else /* RCC_D2CCIP2R_USART16910SEL */
+#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL)))
+/* alias */
+#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE
#endif /* RCC_D2CCIP2R_USART16SEL */
/** @brief macro to configure the USART234578 clock (USART234578CLK).
@@ -2689,8 +2874,8 @@
#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
#else
-#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM3CLKSource__) \
- MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3CLKSource__))
+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
+ MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__))
#endif /* RCC_D3CCIPR_LPTIM345SEL */
/** @brief macro to get the LPTIM3/4/5 clock source.
@@ -2815,9 +3000,13 @@
* @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock
* @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock
*/
+#if defined(RCC_CDCCIPR_OCTOSPISEL)
#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
-
+#else
+#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
+ MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
+#endif /* RCC_CDCCIPR_OCTOSPISEL */
/** @brief macro to get the OSPI clock source.
* @retval The clock source can be one of the following values:
@@ -2826,7 +3015,11 @@
* @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock
* @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock
*/
+#if defined(RCC_CDCCIPR_OCTOSPISEL)
#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))
+#else
+#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL)))
+#endif /* RCC_CDCCIPR_OCTOSPISEL */
#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
@@ -3374,9 +3567,6 @@
#endif /* RCC_D2CCIP2R_RNGSEL */
#if defined(HRTIM1)
-/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
- * @{
- */
/** @brief Macro to configure the HRTIM1 prescaler clock source.
* @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.
* This parameter can be one of the following values:
@@ -3409,10 +3599,6 @@
}while(0)
/**
- * @}
- */
-
-/**
* @brief Enable the RCC LSE CSS Extended Interrupt Line.
* @retval None
*/
@@ -3696,6 +3882,10 @@
/* Exported functions --------------------------------------------------------*/
+ /** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
/** @addtogroup RCCEx_Exported_Functions_Group1
* @{
*/
@@ -3751,6 +3941,10 @@
* @}
*/
+/**
+ * @}
+ */
+
/* Private macros ------------------------------------------------------------*/
/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
* @{
@@ -3884,10 +4078,19 @@
((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \
((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
+#if defined(I2C5)
+#define IS_RCC_I2C1235CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \
+ ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI))
+
+#define IS_RCC_I2C123CLKSOURCE IS_RCC_I2C1235CLKSOURCE /* For API Backward compatibility */
+#else
#define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \
((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \
((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
+#endif /*I2C5*/
#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \
((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
@@ -3909,6 +4112,13 @@
((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
+#if defined(I2C5)
+#define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_I2C5CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \
+ ((SOURCE) == RCC_I2C5CLKSOURCE_CSI))
+#endif /*I2C5*/
+
#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \
((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \
@@ -4253,6 +4463,10 @@
* @}
*/
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/Inc/stm32h7xx_hal_rtc.h b/Inc/stm32h7xx_hal_rtc.h
index 4344e2d..99c0dd1 100644
--- a/Inc/stm32h7xx_hal_rtc.h
+++ b/Inc/stm32h7xx_hal_rtc.h
@@ -60,7 +60,7 @@
typedef struct
{
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
+ This parameter can be a value of @ref RTC_Hour_Formats_Definitions */
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
@@ -69,7 +69,7 @@
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
- This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
+ This parameter can be a value of @ref RTC_Output_selection_Definitions */
uint32_t OutPutRemap; /*!< Specifies the remap for RTC output.
This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */
@@ -1217,6 +1217,7 @@
* @{
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
diff --git a/Inc/stm32h7xx_hal_rtc_ex.h b/Inc/stm32h7xx_hal_rtc_ex.h
index 91d967d..9476718 100644
--- a/Inc/stm32h7xx_hal_rtc_ex.h
+++ b/Inc/stm32h7xx_hal_rtc_ex.h
@@ -733,6 +733,14 @@
* @}
*/
+/** @defgroup RTCEx_MonotonicCounter_Instance RTCEx Monotonic Counter Instance Definition
+ * @{
+ */
+#define RTC_MONOTONIC_COUNTER_1 0u /*!< Monotonic counter 1 */
+/**
+ * @}
+ */
+
/** @defgroup RTCEx_Tamper_Registers_Offset RTC Tamper Registers Offset
* @{
*/
@@ -1412,10 +1420,6 @@
#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
#endif /* RTC_ISR_SHPF */
-/**
- * @}
- */
-
/* ========================================================================== */
/* ##### RTC Wake-up Interrupt exported macros ##### */
/* ========================================================================== */
@@ -1639,10 +1643,6 @@
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
#endif /* EXTI_D1 */
-/**
- * @}
- */
-
#if defined(DUAL_CORE)
/**
* @brief Enable interrupt on the RTC Tamper and Timestamp associated D2 Exti line.
@@ -1840,6 +1840,10 @@
HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc);
#endif /* TAMP_ATCR1_TAMP1AM */
+/**
+ * @}
+ */
+
/* ========================================================================== */
/* ##### RTC Wake-up exported functions ##### */
/* ========================================================================== */
@@ -1893,8 +1897,8 @@
HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
#if defined(TAMP_COUNTR)
-HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter);
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance);
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance);
#endif /* TAMP_COUNTR */
/**
* @}
diff --git a/Inc/stm32h7xx_hal_sai.h b/Inc/stm32h7xx_hal_sai.h
index 518fa64..7db7eb8 100644
--- a/Inc/stm32h7xx_hal_sai.h
+++ b/Inc/stm32h7xx_hal_sai.h
@@ -115,9 +115,10 @@
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
This parameter can be a value of @ref SAI_Audio_Frequency */
- uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
- AudioFrequency the user choice
- This parameter must be a number between Min_Data = 0 and Max_Data = 63. */
+ uint32_t Mckdiv; /*!< Specifies the master clock divider.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 63.
+ @note This parameter is used only if AudioFrequency is set to
+ SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
uint32_t MckOverSampling; /*!< Specifies the master clock oversampling.
This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
@@ -154,6 +155,7 @@
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
* @brief SAI Frame Init structure definition
+ * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
* @{
*/
typedef struct
@@ -186,6 +188,8 @@
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
* @brief SAI Block Slot Init Structure definition
+ * @note For SPDIF protocol, these parameters are not used (set by hardware).
+ * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
* @{
*/
typedef struct
@@ -824,7 +828,7 @@
*/
/* Private macros ------------------------------------------------------------*/
-/** @addtogroup SAI_Private_Macros
+/** @defgroup SAI_Private_Macros SAI Private Macros
* @{
*/
#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
diff --git a/Inc/stm32h7xx_hal_sd.h b/Inc/stm32h7xx_hal_sd.h
index 66f5f65..dd06788 100644
--- a/Inc/stm32h7xx_hal_sd.h
+++ b/Inc/stm32h7xx_hal_sd.h
@@ -156,7 +156,6 @@
void (* Read_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* Write_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* Write_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd);
-
#if (USE_SD_TRANSCEIVER != 0U)
void (* DriveTransceiver_1_8V_Callback) (FlagStatus status);
#endif /* USE_SD_TRANSCEIVER */
diff --git a/Inc/stm32h7xx_hal_sd_ex.h b/Inc/stm32h7xx_hal_sd_ex.h
index f7404a1..800434e 100644
--- a/Inc/stm32h7xx_hal_sd_ex.h
+++ b/Inc/stm32h7xx_hal_sd_ex.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_SD_EX_H
@@ -35,7 +35,7 @@
/** @addtogroup SDEx
* @brief SD HAL extended module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup SDEx_Exported_Types SDEx Exported Types
@@ -44,7 +44,7 @@
/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
* @{
- */
+ */
typedef enum
{
SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */
@@ -52,24 +52,24 @@
}HAL_SDEx_DMABuffer_MemoryTypeDef;
-
-/**
+/**
* @}
*/
-
-/**
+
+/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDEx_Exported_Functions SDEx Exported Functions
* @{
*/
-
+
/** @defgroup SDEx_Exported_Functions_Group1 MultiBuffer functions
* @{
*/
+
HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
@@ -83,11 +83,11 @@
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@@ -95,7 +95,7 @@
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
+
/**
* @}
*/
@@ -108,6 +108,6 @@
#endif
-#endif /* stm32h7xx_HAL_SD_EX_H */
+#endif /* stm32h7xx_HAL_SD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_smbus.h b/Inc/stm32h7xx_hal_smbus.h
index fa13dbe..c82c44b 100644
--- a/Inc/stm32h7xx_hal_smbus.h
+++ b/Inc/stm32h7xx_hal_smbus.h
@@ -132,7 +132,11 @@
* @brief SMBUS handle Structure definition
* @{
*/
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
typedef struct __SMBUS_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
{
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
@@ -326,6 +330,7 @@
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
+#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
@@ -582,11 +587,12 @@
((REQUEST) == SMBUS_NO_STARTSTOP))
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
((REQUEST) == SMBUS_FIRST_FRAME) || \
((REQUEST) == SMBUS_NEXT_FRAME) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
diff --git a/Inc/stm32h7xx_hal_tim.h b/Inc/stm32h7xx_hal_tim.h
index 31b42fe..aee9f74 100644
--- a/Inc/stm32h7xx_hal_tim.h
+++ b/Inc/stm32h7xx_hal_tim.h
@@ -305,6 +305,26 @@
} HAL_TIM_StateTypeDef;
/**
+ * @brief TIM Channel States definition
+ */
+typedef enum
+{
+ HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
+ HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
+ HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+ * @brief DMA Burst States definition
+ */
+typedef enum
+{
+ HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
+ HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
+ HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
* @brief HAL Active channel structures definition
*/
typedef enum
@@ -327,13 +347,16 @@
typedef struct
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
+ __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
+ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
@@ -1116,25 +1139,49 @@
* @retval None
*/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->Base_MspInitCallback = NULL; \
- (__HANDLE__)->Base_MspDeInitCallback = NULL; \
- (__HANDLE__)->IC_MspInitCallback = NULL; \
- (__HANDLE__)->IC_MspDeInitCallback = NULL; \
- (__HANDLE__)->OC_MspInitCallback = NULL; \
- (__HANDLE__)->OC_MspDeInitCallback = NULL; \
- (__HANDLE__)->PWM_MspInitCallback = NULL; \
- (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ (__HANDLE__)->Base_MspInitCallback = NULL; \
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \
+ (__HANDLE__)->IC_MspInitCallback = NULL; \
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OC_MspInitCallback = NULL; \
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
} while(0)
#else
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ } while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
@@ -1951,15 +1998,15 @@
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
@@ -2008,6 +2055,50 @@
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
+ (__HANDLE__)->ChannelState[5])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
+ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
+ (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
+ } while(0)
+
+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
+ (__HANDLE__)->ChannelNState[3])
+
+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
+ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
+ (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
+ } while(0)
+
/**
* @}
*/
@@ -2233,6 +2324,11 @@
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/**
* @}
*/
@@ -2252,7 +2348,6 @@
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
diff --git a/Inc/stm32h7xx_hal_tim_ex.h b/Inc/stm32h7xx_hal_tim_ex.h
index dd616a7..6d15c05 100644
--- a/Inc/stm32h7xx_hal_tim_ex.h
+++ b/Inc/stm32h7xx_hal_tim_ex.h
@@ -491,6 +491,7 @@
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_uart.h b/Inc/stm32h7xx_hal_uart.h
index d20657e..a707583 100644
--- a/Inc/stm32h7xx_hal_uart.h
+++ b/Inc/stm32h7xx_hal_uart.h
@@ -1170,13 +1170,14 @@
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
+
/** @brief BRR division operation to set BRR register with LPUART.
* @param __PCLK__ LPUART clock.
* @param __BAUD__ Baud rate set by the user.
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
-#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)\
+ (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
@@ -1185,7 +1186,7 @@
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U)\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
@@ -1194,7 +1195,7 @@
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Check whether or not UART instance is Low Power UART.
@@ -1514,6 +1515,11 @@
#include "stm32h7xx_hal_uart_ex.h"
+/* Prescaler Table used in BRR computation macros.
+ Declared as extern here to allow use of private UART macros, outside of HAL UART fonctions */
+extern const uint16_t UARTPrescTable[12];
+
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions UART Exported Functions
* @{
diff --git a/Inc/stm32h7xx_ll_adc.h b/Inc/stm32h7xx_ll_adc.h
index 92045d3..f7e8c9c 100644
--- a/Inc/stm32h7xx_ll_adc.h
+++ b/Inc/stm32h7xx_ll_adc.h
@@ -160,10 +160,10 @@
/* Mask containing trigger source masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
- ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
- ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
- ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
+#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
/* Mask containing trigger edge masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
@@ -328,6 +328,11 @@
#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
+#if defined(ADC_VER_V5_V90)
+#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
+#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
+#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
+#endif /* ADC_VER_V5_V90 */
/* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
/* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
@@ -353,6 +358,9 @@
#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
+#if defined(ADC_VER_V5_V90)
+#define ADC_CFGR_RES_BITOFFSET_POS_ADC3 (ADC3_CFGR_RES_Pos)
+#endif /* ADC_VER_V5_V90 */
/* ADC registers bits groups */
@@ -361,16 +369,27 @@
/* ADC internal channels related definitions */
/* Internal voltage reference VrefInt */
+#if defined(ADC_VER_V5_3)
+#define VREFINT_CAL_ADDR ((uint16_t*) (0x8fff810UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+ /* Adress related to STM32H7A3 */
+#else /* ADC_VER_V5_90 || ADC_VER_V5_X */
#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#endif /* ADC_VER_V5_3 */
#define VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/* Temperature sensor */
+#if defined(ADC_VER_V5_3)
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x8fff814UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x8fff818UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+ /* Adresses related to STM32H7A3 */
+#else /* ADC_VER_V5_90 || ADC_VER_V5_X */
#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#endif /* ADC_VER_V5_3 */
+
#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
-
/* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */
#define ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))
#define ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))
@@ -398,7 +417,7 @@
* @retval Pointer to register address
*/
#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
@@ -752,19 +771,43 @@
/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
* @{
*/
-#define LL_ADC_RESOLUTION_16B (0x00000000UL) /*!< ADC resolution 16 bits */
-#define LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0) /*!< ADC resolution 12 bits */
-#define LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 ) /*!< ADC resolution 12 bits */
-#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
-#if defined (ADC_VER_V5_3)
+#define LL_ADC_RESOLUTION_16B (0x00000000UL) /*!< ADC resolution 16 bits */
+#define LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0) /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 ) /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
+
+#if defined (ADC_VER_V5_X)
+#define LL_ADC_RESOLUTION_14B_OPT (ADC_CFGR_RES_2 | ADC_CFGR_RES_0) /*!< ADC resolution 14 bits optimized for power consumption, available on for devices revision V only */
+#define LL_ADC_RESOLUTION_12B_OPT (ADC_CFGR_RES_2 | ADC_CFGR_RES_1 ) /*!< ADC resolution 12 bits optimized for power consumption, available on for devices revision V only */
+#endif
+
+#if defined (ADC_VER_V5_3) || defined(ADC_VER_V5_V90)
#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 8 bits */
#else
#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2 ) /*!< ADC resolution 8 bits */
+ /*!< The resolution setting is managed internaly in the driver:
+ "LL_ADC_RESOLUTION_8B" definition: keep using the "100b" value (corresponding to STM32H74x/5x rev Y).
+ Rev.V value "111b" is handled through functions "LL_ADC_SetResolution/LL_ADC_GetResolution" with a dedicated check on DBGMCU IDCODE register */
#endif
+#if defined(ADC_VER_V5_V90)
+#define LL_ADC_RESOLUTION_6B (ADC3_CFGR_RES_1 | ADC3_CFGR_RES_0) /*!< ADC resolution 6 bits. Value available for ADC3 on STM32H72xx/3xx devices only*/
+#endif /* ADC_VER_V5_V90 */
/**
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
+ * @{
+ */
+#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC3_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+#endif /* ADC_VER_V5_V90 */
+
/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
* @{
*/
@@ -825,6 +868,37 @@
/**
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
+ * @{
+ */
+#define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
+#define LL_ADC_OFFSET_SATURATION_ENABLE (ADC3_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
+ * @{
+ */
+#define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_ENABLE (ADC3_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+ * @}
+ */
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
+ * @{
+ */
+#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
+#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
+/**
+ * @}
+ */
+#endif
+
+#endif /* ADC_VER_V5_V90 */
+
/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
* @{
*/
@@ -859,10 +933,15 @@
#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
#if defined(ADC3)
-/*!< ADC3 is defined only in the case of STM32H7XX */
+#if defined(ADC_VER_V5_V90)
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */
+#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */
+#else
#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */
#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */
#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */
+#endif
#else
/*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */
#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC2. */
@@ -902,8 +981,14 @@
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
+#if defined (TIM23)
+#define LL_ADC_REG_TRIG_EXT_TIM23_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM23 TRGO event. Trigger edge set to rising edge (default setting). */
+#endif /* TIM23 */
+#if defined (TIM24)
+#define LL_ADC_REG_TRIG_EXT_TIM24_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM24 TRGO event. Trigger edge set to rising edge (default setting). */
+#endif /* TIM24 */
/**
* @}
*/
@@ -917,10 +1002,24 @@
/**
* @}
*/
-
-/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
+#if defined(ADC_VER_V5_V90)
+ /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
* @{
*/
+#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME. On devices STM32H72xx and STM32H73xx */
+#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC3_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
+ Note: First conversion is using minimal sampling time (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME). On devices STM32H72xx and STM32H73xx */
+#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC3_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events:
+ Trigger rising edge = start sampling
+ Trigger falling edge = stop sampling and start conversion. On devices STM32H72xx and STM32H73xx */
+/**
+ * @}
+ */
+#endif /* ADC_VER_V5_V90 */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
+* @{
+*/
#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
/**
@@ -938,9 +1037,22 @@
* @}
*/
-/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
* @{
*/
+
+#define LL_ADC3_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC3_REG_DMA_TRANSFER_LIMITED ( ADC3_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC3_REG_DMA_TRANSFER_UNLIMITED (ADC3_CFGR_DMACFG | ADC3_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. On ADC3 of devices STM32H72xx and STM32H73xx*/
+/**
+ * @}
+ */
+#endif
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
+* @{
+*/
#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
/**
@@ -1034,6 +1146,8 @@
#define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM23_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM23 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM24_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM24 TRGO event. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
@@ -1049,8 +1163,8 @@
*/
/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
- * @{
- */
+* @{
+*/
#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
/**
@@ -1112,6 +1226,22 @@
/**
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_SAMPLINGTIME_ADC3_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_SAMPLINGTIME_ADC3_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_SAMPLINGTIME_ADC3_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_SAMPLINGTIME_ADC3_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_SAMPLINGTIME_ADC3_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_SAMPLINGTIME_ADC3_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_SAMPLINGTIME_ADC3_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
+/**
+ * @}
+ */
+#endif /* ADC_VER_V5_V90 */
/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
* @{
@@ -1227,6 +1357,22 @@
/**
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
+ * @{
+ */
+#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC3_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC3_TR1_AWDFILT_2 ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+/**
+ * @}
+ */
+#endif /* ADC_VER_V5_V90 */
/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
* @{
@@ -1248,6 +1394,22 @@
/**
* @}
*/
+#if defined(ADC_VER_V5_V90)
+/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
+ * @{
+ */
+#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_4 ( ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_8 ( ADC3_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_16 ( ADC3_CFGR2_OVSR_1 | ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_32 (ADC3_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_64 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_128 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_256 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_1 | ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+/**
+ * @}
+ */
+#endif /* ADC_VER_V5_V90 */
/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
* @{
@@ -1430,6 +1592,41 @@
* @{
*/
+#if defined(ADC_VER_V5_V90)
+/**
+ * @brief Helper macro to convert the resolution defines to STM32H73x/2x ADC3 registers values
+ * value corresponding to the ADC3 resolution according to the STM32H73x/2x RefMan.
+ * @note The input can be a value from ADC3 resolution (12b, 10b, 8b,6b)
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Returned value can be one of the following values:
+ * @arg 0x00000000UL (value correspodning to ADC3 12 bits)
+ * @arg ADC_CFGR_RES_0 = 0x00000004 (value corresponding to ADC3 10 bits)
+ * @arg ADC_CFGR_RES_1 = 0x00000008 (value corresponding to ADC3 8 bits)
+ * @arg 0x0000001C (value corresponding to ADC3 6 bits)
+ * @note This helper macro is applicable for STM32H73x/2x devices only
+ */
+#define __LL_ADC12_RESOLUTION_TO_ADC3(__ADC_RESOLUTION__) \
+ ( \
+ ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
+ ?(0x00000000UL) \
+ : \
+ ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
+ ?(ADC_CFGR_RES_0) \
+ : \
+ ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
+ ?(ADC_CFGR_RES_1) \
+ : \
+ ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
+ ?((ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) \
+ :(0x00000000UL) \
+ )
+
+#endif /* ADC_VER_V5_V90 */
+
/**
* @brief Helper macro to get ADC channel number in decimal format
* from literals LL_ADC_CHANNEL_x.
@@ -1474,13 +1671,13 @@
*/
#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
- ? ( \
+ ? ( \
((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
- ) \
- : \
- ( \
+ ) \
+ : \
+ ( \
(uint32_t)POSITION_VAL((__CHANNEL__)) \
- ) \
+ ) \
)
/**
@@ -1527,17 +1724,17 @@
*/
#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
(((__DECIMAL_NB__) <= 9UL) \
- ? ( \
+ ? ( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
(ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
- ) \
- : \
- ( \
+ ) \
+ : \
+ ( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
(ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
- ) \
+ ) \
)
/**
@@ -1854,12 +2051,12 @@
*/
#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
(((__GROUP__) == LL_ADC_GROUP_REGULAR) \
- ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
- : \
- ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
- ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
- : \
- (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
+ : \
+ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
+ : \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
)
/**
@@ -2036,6 +2233,23 @@
#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
(0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
+#if defined(ADC_VER_V5_V90)
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: digital value of ADC conversion bitfield)
+ */
+#define __LL_ADC3_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL)))
+#endif /* ADC_VER_V5_V90 */
/**
* @brief Helper macro to convert the ADC conversion data from
* a resolution to another resolution.
@@ -2056,14 +2270,90 @@
* @arg @ref LL_ADC_RESOLUTION_8B
* @retval ADC conversion data to the requested resolution
*/
+#if defined(ADC_VER_V5_X) || defined(ADC_VER_V5_V90)
#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+( (__ADC_RESOLUTION_CURRENT__ == LL_ADC_RESOLUTION_8B) \
+ ?( \
+ ((__DATA__) \
+ << (((__ADC_RESOLUTION_CURRENT__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+ ) \
+ : \
+ ( \
+ (__ADC_RESOLUTION_TARGET__ == LL_ADC_RESOLUTION_8B) \
+ ? ( \
+ ((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> (((__ADC_RESOLUTION_TARGET__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+ ) \
+ :\
+ (\
+ ((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+ ) \
+ )\
+ )
+
+
+#else /* defined(ADC_VER_V5_3) */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+( (__ADC_RESOLUTION_CURRENT__ == LL_ADC_RESOLUTION_8B) \
+ ?( \
+ ((__DATA__) \
+ << (((__ADC_RESOLUTION_CURRENT__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+ ) \
+ : \
+ ( \
+ (__ADC_RESOLUTION_TARGET__ == LL_ADC_RESOLUTION_8B) \
+ ? ( \
+ ((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> (((__ADC_RESOLUTION_TARGET__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+ ) \
+ :\
+ (\
+ ((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+ ) \
+ )\
+ )
+
+#endif
+
+#if defined(ADC_VER_V5_V90)
+/**
+* @brief Helper macro to convert the ADC conversion data from
+* a resolution to another resolution.
+* @param __DATA__ ADC conversion data to be converted
+* @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
+* This parameter can be one of the following values:
+* @arg @ref LL_ADC_RESOLUTION_12B
+* @arg @ref LL_ADC_RESOLUTION_10B
+* @arg @ref LL_ADC_RESOLUTION_8B
+* @arg @ref LL_ADC_RESOLUTION_6B
+* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+* This parameter can be one of the following values:
+* @arg @ref LL_ADC_RESOLUTION_12B
+* @arg @ref LL_ADC_RESOLUTION_10B
+* @arg @ref LL_ADC_RESOLUTION_8B
+* @arg @ref LL_ADC_RESOLUTION_6B
+* @retval ADC conversion data to the requested resolution
+*/
+#define __LL_ADC_CONVERT_DATA_RESOLUTION_ADC3(__DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
__ADC_RESOLUTION_TARGET__) \
(((__DATA__) \
- << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
- >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL)) \
)
-
+#endif /* ADC_VER_V5_V90 */
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
* corresponding to a ADC conversion data (unit: digital value).
@@ -2117,9 +2407,10 @@
#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
__ADC_RESOLUTION__) \
(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
- / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
- (__ADC_RESOLUTION__), \
- LL_ADC_RESOLUTION_16B))
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_16B) \
+ )
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -2294,17 +2585,17 @@
*/
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
{
- register uint32_t data_reg_addr;
+ uint32_t data_reg_addr;
if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
{
/* Retrieve address of register DR */
- data_reg_addr = (uint32_t) &(ADCx->DR);
+ data_reg_addr = (uint32_t) & (ADCx->DR);
}
else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
{
/* Retrieve address of register CDR */
- data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+ data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
}
return data_reg_addr;
@@ -2491,9 +2782,15 @@
*/
__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
{
+#if defined(ADC_VER_V5_V90)
+ MODIFY_REG(ADCx->CALFACT_RES13,
+ SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+ CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
+#else
MODIFY_REG(ADCx->CALFACT,
SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
+#endif
}
/**
@@ -2520,7 +2817,11 @@
/* "SingleDiff". */
/* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
/* containing other bits reserved for other purpose. */
+#if defined(ADC_VER_V5_V90)
+ return (uint32_t)(READ_BIT(ADCx->CALFACT_RES13, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
+#else
return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
+#endif
}
/**
@@ -2547,13 +2848,26 @@
*/
__STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)
{
- register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
+#if defined(ADC_VER_V5_V90)
+ if (ADCx != ADC3)
+ {
+ uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
+ MODIFY_REG(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
+ MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
+ while ((READ_BIT(ADCx->CR, LinearityWord) == 0UL) && (timeout_cpu_cycles > 0UL))
+ {
+ timeout_cpu_cycles--;
+ }
+ }
+#else /* ADC_VER_V5_V90 */
+ uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
- while ((READ_BIT(ADCx->CR, LinearityWord)==0UL) && (timeout_cpu_cycles > 0UL))
+ while ((READ_BIT(ADCx->CR, LinearityWord) == 0UL) && (timeout_cpu_cycles > 0UL))
{
timeout_cpu_cycles--;
}
+#endif
}
/**
@@ -2574,13 +2888,17 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
{
- register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
+ uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
CLEAR_BIT(ADCx->CR, LinearityWord);
- while ((READ_BIT(ADCx->CR, LinearityWord)!=0UL) && (timeout_cpu_cycles > 0UL))
+ while ((READ_BIT(ADCx->CR, LinearityWord) != 0UL) && (timeout_cpu_cycles > 0UL))
{
timeout_cpu_cycles--;
}
+#if defined(ADC_VER_V5_V90)
+ return (uint32_t)(READ_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT));
+#else
return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));
+#endif
}
/**
* @brief Set ADC resolution.
@@ -2602,16 +2920,41 @@
*/
__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
{
-#if defined (ADC_VER_V5_3)
+#if defined(ADC_VER_V5_3)
+
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
-#else
- if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
+
+#elif defined(ADC_VER_V5_V90)
+ if (ADCx == ADC3)
+ {
+ MODIFY_REG(ADCx->CFGR, ADC3_CFGR_RES, (((Resolution & 0x10UL) | 0x08UL | (Resolution & 0x04UL)) & 0x00000018UL));
+ }
+ else
+ {
+ if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
+ {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+ }
+ else /* Rev.V */
+ {
+ if (LL_ADC_RESOLUTION_8B == Resolution)
+ {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+ }
+ }
+ }
+#else /* ADC_VER_V5_V90 */
+ if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
}
else /* Rev.V */
{
- if(LL_ADC_RESOLUTION_8B == Resolution)
+ if (LL_ADC_RESOLUTION_8B == Resolution)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
}
@@ -2620,7 +2963,8 @@
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
}
}
-#endif /* ADC_VER_V5_3*/
+
+#endif /* ADC_VER_V5_X*/
}
/**
@@ -2635,13 +2979,33 @@
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B **Value available for ADC3 on STM32H72x/3x devices only **
*/
__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
{
#if defined (ADC_VER_V5_3)
- return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
-#else
- if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
+
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+
+#elif defined(ADC_VER_V5_V90)
+ if (ADCx == ADC3)
+ {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC3_CFGR_RES));
+ }
+ else
+ {
+ if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
+ {
+ return (LL_ADC_RESOLUTION_8B);
+ }
+ else
+ {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+ }
+ }
+
+#else /* ADC_VER_V5_V90 */
+ if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
}
@@ -2656,7 +3020,8 @@
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
}
}
-#endif /* ADC_VER_V5_3 */
+
+#endif /* ADC_VER_V5_X */
}
/**
@@ -2761,6 +3126,51 @@
}
/**
+ * @brief Set ADC selected Channel.
+ * @note This function set the pre-selection of channel configuration.
+ * @note Caution: Channel selections is dependent to ADC instance and IP version:
+ * For STM32H72x/3x This is applicable only for ADC1/ADC2
+ * For Rest of STM32H7xxx This is applicable only all the ADCs instances.
+ *
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelPreSelection(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+#if defined(ADC_VER_V5_V90)
+ if (ADCx != ADC3)
+ {
+ /* ADC channels preselection */
+ ADCx->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
+ }
+#else
+ /* ADC channels preselection */
+ ADCx->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
+#endif /* ADC_VER_V5_V90 */
+}
+
+/**
* @brief Set ADC selected offset number 1, 2, 3 or 4.
* @note This function set the 2 items of offset configuration:
* - ADC channel to which the offset programmed will be applied
@@ -2835,11 +3245,21 @@
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
-
- MODIFY_REG(*preg,
- ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
- (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+#if defined(ADC_VER_V5_V90)
+ if (ADCx == ADC3)
+ {
+ MODIFY_REG(*preg,
+ ADC3_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+ }
+ else
+#endif /* ADC_VER_V5_V90 */
+ {
+ MODIFY_REG(*preg,
+ ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+ }
}
/**
@@ -2907,7 +3327,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
}
@@ -2933,7 +3353,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
}
@@ -2975,7 +3395,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)
{
- return (uint32_t) ((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));
+ return (uint32_t)((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));
}
/**
@@ -2998,8 +3418,17 @@
*/
__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
- MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
+#if defined(ADC_VER_V5_V90)
+ if (ADCx == ADC3)
+ {
+ /* Function not available on this instance */
+ }
+ else
+#endif /* ADC_VER_V5_V90 */
+ {
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
+ }
}
/**
@@ -3021,10 +3450,225 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
- return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
+#if defined(ADC_VER_V5_V90)
+ if (ADCx == ADC3)
+ {
+ /* Function not available on this instance */
+ return 0UL;
+ }
+ else
+#endif /* ADC_VER_V5_V90 */
+ {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
+ }
}
+#if defined(ADC_VER_V5_V90)
+/**
+ * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
+ * choose offset saturation mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n
+ * OFR2 SATEN LL_ADC_SetOffsetSaturation\n
+ * OFR3 SATEN LL_ADC_SetOffsetSaturation\n
+ * OFR4 SATEN LL_ADC_SetOffsetSaturation
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetSaturation This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+ * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
+{
+ if (ADCx == ADC3)
+ {
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ MODIFY_REG(*preg,
+ ADC3_OFR1_SATEN,
+ OffsetSaturation);
+ }
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * offset saturation if enabled or disabled.
+ * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n
+ * OFR2 SATEN LL_ADC_GetOffsetSaturation\n
+ * OFR3 SATEN LL_ADC_GetOffsetSaturation\n
+ * OFR4 SATEN LL_ADC_GetOffsetSaturation
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+ * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ if (ADCx == ADC3)
+ {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC3_OFR1_SATEN);
+ }else
+ {
+ return 0UL;
+ }
+}
+
+/**
+ * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
+ * choose offset sign.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
+ * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
+ * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
+ * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetSign This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+ * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
+{
+ if (ADCx == ADC3)
+ {
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ MODIFY_REG(*preg,
+ ADC3_OFR1_OFFSETPOS,
+ OffsetSign);
+ }
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * offset sign if positive or negative.
+ * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
+ * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
+ * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
+ * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+ * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ if (ADCx == ADC3)
+ {
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC3_OFR1_OFFSETPOS);
+ }
+ else
+ {
+ return 0UL;
+ }
+}
+
+/**
+ * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
+ * force offset state disable or enable
+ * without modifying offset channel or offset value.
+ * @note This function should be needed only in case of offset to be
+ * enabled-disabled dynamically, and should not be needed in other cases:
+ * function LL_ADC_SetOffset() automatically enables the offset.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
+ * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
+ * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
+ * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetState This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_DISABLE
+ * @arg @ref LL_ADC_OFFSET_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
+{
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ if (ADCx == ADC3)
+ {
+ MODIFY_REG(*preg,
+ ADC3_OFR1_OFFSET1_EN,
+ OffsetState);
+ }
+ else
+ {
+ MODIFY_REG(*preg,
+ ADC_OFR1_SSATE,
+ OffsetState);
+ }
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * offset state disabled or enabled.
+ * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
+ * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
+ * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
+ * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_DISABLE
+ * @arg @ref LL_ADC_OFFSET_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ if (ADCx == ADC3)
+ {
+ return (uint32_t) READ_BIT(*preg, ADC3_OFR1_OFFSET1_EN);
+ }
+ else
+ {
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
+ }
+}
+
+#endif /* ADC_VER_V5_V90 */
+
/**
* @}
*/
@@ -3123,11 +3767,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
{
- register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+ __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
- register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+ uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
/* to match with triggers literals definition. */
@@ -3188,6 +3832,38 @@
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
}
+#if defined(ADC_VER_V5_V90)
+/**
+ * @brief Set ADC sampling mode.
+ * @note This function set the ADC conversion sampling mode
+ * @note This mode applies to regular group only.
+ * @note Set sampling mode is appied to all conversion of regular group.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
+ * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
+ * @param ADCx ADC instance
+ * @param SamplingMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+ * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
+{
+ if (ADCx != ADC3)
+ {
+ /* Function not available on this instance */
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CFGR2, ADC3_CFGR2_BULB | ADC3_CFGR2_SMPTRIG, SamplingMode);
+ }
+}
+#endif /* ADC_VER_V5_V90 */
+
/**
* @brief Set ADC group regular sequencer length and scan direction.
* @note Description of ADC group regular sequencer features:
@@ -3449,7 +4125,7 @@
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
@@ -3547,7 +4223,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
return (uint32_t)((READ_BIT(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
@@ -3604,11 +4280,7 @@
* - Transfered to DFSDM data register
* @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode
* @param ADCx ADC instance
- * @param DataTransferMode This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_DR_TRANSFER
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
- * @arg @ref LL_ADC_REG_DFSDM_TRANSFER
+ * @param DataTransferMode Select Data Management configuration
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
@@ -3616,6 +4288,113 @@
MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);
}
+#if defined(ADC_VER_V5_V90)
+/**
+ * @brief Enable DMA requests for ADC3.
+ * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableDMAReq (ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN);
+}
+
+__STATIC_INLINE void LL_ADC_DisableDMAReq(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT (ADCx->CFGR, ADC3_CFGR_DMAEN);
+}
+
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN) == (ADC3_CFGR_DMAEN)) ? 1UL : 0UL);
+}
+/**
+ * @brief Set ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note For devices with several ADC instances: ADC multimode DMA
+ * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransferMode\n
+ * CFGR DMACFG LL_ADC_REG_SetDMATransferMode
+ * @param ADCx ADC instance
+ * @param DMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC3_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC3_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC3_REG_DMA_TRANSFER_UNLIMITED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransferMode(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+ if (ADCx == ADC3)
+ {
+ MODIFY_REG(ADCx->CFGR, ADC3_CFGR_DMAEN | ADC3_CFGR_DMACFG, DMATransfer);
+ }
+}
+
+/**
+ * @brief Get ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note For devices with several ADC instances: ADC multimode DMA
+ * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
+ * CFGR DMACFG LL_ADC_REG_GetDMATransfer
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC3_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC3_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC3_REG_DMA_TRANSFER_UNLIMITED
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx)
+{
+ if (ADCx == ADC3)
+ {
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN | ADC3_CFGR_DMACFG));
+ }
+ else
+ {
+ return 0UL;
+ }
+}
+
+#endif /* ADC_VER_V5_V90 */
/**
* @brief Get ADC data transfer mode
@@ -3775,11 +4554,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
{
- register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+ __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
- register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+ uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
/* to match with triggers literals definition. */
@@ -4053,8 +4832,8 @@
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
return (uint32_t)((READ_BIT(ADCx->JSQR,
- (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
- >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+ (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+ >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
);
}
@@ -4379,7 +5158,7 @@
/* because containing other bits reserved for other purpose. */
/* If parameter "TriggerSource" is set to SW start, then parameter */
/* "ExternalTriggerEdge" is discarded. */
- register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
+ uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
MODIFY_REG(ADCx->JSQR,
ADC_JSQR_JEXTSEL |
ADC_JSQR_JEXTEN |
@@ -4388,7 +5167,7 @@
ADC_JSQR_JSQ2 |
ADC_JSQR_JSQ1 |
ADC_JSQR_JL,
- (TriggerSource & ADC_JSQR_JEXTSEL) |
+ (TriggerSource & ADC_JSQR_JEXTSEL) |
(ExternalTriggerEdge * (is_trigger_not_sw)) |
(((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
(((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
@@ -4500,7 +5279,7 @@
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
@@ -4581,7 +5360,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
@@ -4642,12 +5421,30 @@
*/
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
+#if defined(ADC_VER_V5_V90)
+ /* Bits of channels in single or differential mode are set only for */
+ /* differential mode (for single mode, mask of bits allowed to be set is */
+ /* shifted out of range of bits of channels in single or differential mode. */
+ if (ADCx == ADC3)
+ {
+ MODIFY_REG(ADCx->LTR2_DIFSEL,
+ Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
+ (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+ }
+ else
+ {
+ MODIFY_REG(ADCx->DIFSEL_RES12,
+ Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
+ (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+ }
+#else /* ADC_VER_V5_V90 */
/* Bits of channels in single or differential mode are set only for */
/* differential mode (for single mode, mask of bits allowed to be set is */
/* shifted out of range of bits of channels in single or differential mode. */
MODIFY_REG(ADCx->DIFSEL,
Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
(Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+#endif
}
/**
@@ -4695,7 +5492,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
{
+#if defined(ADC_VER_V5_V90)
+ return (uint32_t)(READ_BIT(ADCx->DIFSEL_RES12, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+#else
return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+#endif
}
/**
@@ -4843,7 +5644,7 @@
/* in register and register position depending on parameter "AWDy". */
/* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
/* containing other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
MODIFY_REG(*preg,
@@ -4978,10 +5779,10 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
- register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
+ uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
/* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
/* (parameter value LL_ADC_AWD_DISABLE). */
@@ -5085,19 +5886,47 @@
* @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
-__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
- uint32_t AWDThresholdValue)
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
{
+#if defined(ADC_VER_V5_V90)
+ if (ADCx == ADC3)
+ {
+ /* Set bits with content of parameter "AWDThresholdValue" with bits */
+ /* position in register and register position depending on parameters */
+ /* "AWDThresholdsHighLow" and "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+
+ MODIFY_REG(*preg,
+ AWDThresholdsHighLow,
+ AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
+ }
+ else
+ {
+ /* Set bits with content of parameter "AWDThresholdValue" with bits */
+ /* position in register and register position depending on parameters */
+ /* "AWDThresholdsHighLow" and "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ + (AWDThresholdsHighLow));
+
+ MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
+ }
+#else
/* Set bits with content of parameter "AWDThresholdValue" with bits */
/* position in register and register position depending on parameters */
/* "AWDThresholdsHighLow" and "AWDy". */
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
- + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
- + (AWDThresholdsHighLow));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ + (AWDThresholdsHighLow));
MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
+#endif /* ADC_VER_V5_V90 */
}
/**
@@ -5122,16 +5951,168 @@
* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
* @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
- */
+*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+#if defined(ADC_VER_V5_V90)
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ + (AWDThresholdsHighLow));
+
+ return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
+#else
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ (AWDThresholdsHighLow));
return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
+#endif
}
+#if defined(ADC_VER_V5_V90)
+
+/**
+ * @brief Set ADC analog watchdog thresholds value of both thresholds
+ * high and low. Applicable for devices STM32H72xx and STM32H73xx.
+ * @note If value of only one threshold high or low must be set,
+ * use function @ref LL_ADC_SetAnalogWDThresholds().
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
+{
+ /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
+ /* position in register and register position depending on parameter */
+ /* "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ if (ADCx == ADC3)
+ {
+ uint32_t __IO *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+
+ MODIFY_REG(*preg,
+ ADC3_TR1_HT1 | ADC3_TR1_LT1,
+ (AWDThresholdHighValue << ADC3_TR1_HT1_Pos) | AWDThresholdLowValue);
+ }
+ else
+ {
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ + (LL_ADC_AWD_THRESHOLD_LOW));
+ __IO uint32_t *preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ + (LL_ADC_AWD_THRESHOLD_HIGH));
+
+ MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdLowValue);
+ MODIFY_REG(*preg2, ADC_HTR_HT, AWDThresholdHighValue);
+ }
+}
+
+
+/**
+ * @brief Set ADC analog watchdog filtering configuration
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * Applicable on ADC3 of devices STM32H72xx and STM32H73xx.
+ * @note On this STM32 serie, this feature is only available on first
+ * analog watchdog (AWD1)
+ * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @param FilteringConfig This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_FILTERING_NONE
+ * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
+{
+ if (ADCx == ADC3)
+ {
+ /* Prevent unused argument(s) compilation warning */
+ (void)(AWDy);
+ MODIFY_REG(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT, FilteringConfig);
+ }
+}
+
+/**
+ * @brief Get ADC analog watchdog filtering configuration
+ * @note On this STM32 serie, this feature is only available on first
+ * analog watchdog (AWD1)
+ * Applicable on ADC3 of devices STM32H72xx and STM32H73xx.
+ * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @retval Returned value can be:
+ * @arg @ref LL_ADC_AWD_FILTERING_NONE
+ * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+ * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+ if (ADCx == ADC3)
+ {
+ /* Prevent unused argument(s) compilation warning */
+ (void)(AWDy);
+ return (uint32_t)(READ_BIT(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT));
+ }
+ else
+ {
+ /* Function not available on this instance, return 0 */
+ return 0UL;
+ }
+}
+#endif /* ADC_VER_V5_V90 */
/**
* @}
*/
@@ -5281,10 +6262,10 @@
* @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
* @param ADCx ADC instance
* @retval Ratio This parameter can be in the from 1 to 1024.
- */
+*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
{
- return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR))+(1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
+ return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
}
/**
@@ -5305,7 +6286,7 @@
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11
- */
+*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
@@ -5336,7 +6317,13 @@
*/
__STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)
{
- if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
+#if defined(ADC_VER_V5_V90)
+ if (ADCx != ADC3)
+ {
+ MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
+ }
+#else /* ADC_VER_V5_V90 */
+ if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
{
MODIFY_REG(ADCx->CR, ADC_CR_BOOST_0, (BoostMode >> 2UL));
}
@@ -5344,8 +6331,10 @@
{
MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
}
+#endif
}
+
/**
* @brief Get ADC boost mode.
* @note On this STM32 serie, setting of this feature is conditioned to
@@ -5358,7 +6347,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)
{
- if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
+ if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
{
return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_BOOST_0);
}
@@ -6120,7 +7109,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6147,7 +7136,7 @@
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6174,7 +7163,7 @@
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6201,7 +7190,7 @@
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6228,7 +7217,7 @@
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6255,7 +7244,7 @@
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
diff --git a/Inc/stm32h7xx_ll_bdma.h b/Inc/stm32h7xx_ll_bdma.h
index 0748b35..9faa900 100644
--- a/Inc/stm32h7xx_ll_bdma.h
+++ b/Inc/stm32h7xx_ll_bdma.h
@@ -128,7 +128,7 @@
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */
uint32_t PeriphRequest; /*!< Specifies the peripheral request.
- This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
+ This parameter can be a value of @ref DMAMUX2_Request_selection
This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */
@@ -484,7 +484,7 @@
*/
__STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
}
@@ -506,7 +506,7 @@
*/
__STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
}
@@ -528,7 +528,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (BDMA_CCR_EN)) ? 1UL : 0UL);
}
@@ -565,7 +565,7 @@
*/
__STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL,
@@ -594,7 +594,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
BDMA_CCR_DIR | BDMA_CCR_MEM2MEM, Direction);
@@ -621,7 +621,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
BDMA_CCR_DIR | BDMA_CCR_MEM2MEM));
@@ -649,7 +649,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CIRC,
Mode);
@@ -674,7 +674,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
BDMA_CCR_CIRC));
@@ -700,7 +700,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PINC,
PeriphOrM2MSrcIncMode);
@@ -725,7 +725,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
BDMA_CCR_PINC));
@@ -751,7 +751,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MINC,
MemoryOrM2MDstIncMode);
@@ -776,7 +776,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
BDMA_CCR_MINC));
@@ -803,7 +803,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PSIZE,
PeriphOrM2MSrcDataSize);
@@ -829,7 +829,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
BDMA_CCR_PSIZE));
@@ -856,7 +856,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MSIZE,
MemoryOrM2MDstDataSize);
@@ -882,7 +882,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
BDMA_CCR_MSIZE));
@@ -910,7 +910,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PL,
Priority);
@@ -937,7 +937,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
BDMA_CCR_PL));
@@ -963,7 +963,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
BDMA_CNDTR_NDT, NbData);
@@ -988,7 +988,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
BDMA_CNDTR_NDT));
@@ -1014,7 +1014,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT, CurrentMemory);
}
@@ -1038,7 +1038,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT));
}
@@ -1060,7 +1060,7 @@
*/
__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
}
@@ -1082,7 +1082,7 @@
*/
__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
}
@@ -1114,7 +1114,7 @@
__STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress,
uint32_t DstAddress, uint32_t Direction)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
/* Direction Memory to Periph */
if (Direction == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH)
@@ -1150,7 +1150,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
}
@@ -1175,7 +1175,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
}
@@ -1198,7 +1198,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
}
@@ -1221,7 +1221,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
}
@@ -1246,7 +1246,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
}
@@ -1271,7 +1271,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
}
@@ -1294,7 +1294,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
}
@@ -1317,7 +1317,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
}
@@ -1340,7 +1340,7 @@
*/
__STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR, BDMA_CM1AR_MA, Address);
}
@@ -1362,7 +1362,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return (((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR);
}
@@ -1400,8 +1400,9 @@
* @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
* @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
* @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
- * @arg @ref LL_DMAMUX2_REQ_DAC3 (*)
+ * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
* @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
+ *
* @note (*) Availability depends on devices.
* @retval None
*/
@@ -1444,8 +1445,9 @@
* @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
* @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
* @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
- * @arg @ref LL_DMAMUX2_REQ_DAC3 (*)
+ * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
* @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
+ *
* @note (*) Availability depends on devices.
*/
__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel)
@@ -2189,7 +2191,7 @@
*/
__STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
}
@@ -2211,7 +2213,7 @@
*/
__STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
}
@@ -2233,7 +2235,7 @@
*/
__STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
}
@@ -2255,7 +2257,7 @@
*/
__STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
}
@@ -2277,7 +2279,7 @@
*/
__STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
}
@@ -2299,7 +2301,7 @@
*/
__STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
}
@@ -2321,7 +2323,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE) == (BDMA_CCR_TCIE)) ? 1UL : 0UL);
}
@@ -2343,7 +2345,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE) == (BDMA_CCR_HTIE)) ? 1UL : 0UL);
}
@@ -2365,7 +2367,7 @@
*/
__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
{
- register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+ uint32_t bdma_base_addr = (uint32_t)BDMAx;
return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE) == (BDMA_CCR_TEIE)) ? 1UL : 0UL);
}
@@ -2397,6 +2399,9 @@
*/
#endif /* BDMA || BDMA1 || BDMA2 */
+/**
+ * @}
+ */
/**
* @}
diff --git a/Inc/stm32h7xx_ll_bus.h b/Inc/stm32h7xx_ll_bus.h
index a7b739e..022cf6d 100644
--- a/Inc/stm32h7xx_ll_bus.h
+++ b/Inc/stm32h7xx_ll_bus.h
@@ -163,6 +163,12 @@
#endif /* HASH */
#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
#define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN
+#if defined(FMAC)
+#define LL_AHB2_GRP1_PERIPH_FMAC RCC_AHB2ENR_FMACEN
+#endif /* FMAC */
+#if defined(CORDIC)
+#define LL_AHB2_GRP1_PERIPH_CORDIC RCC_AHB2ENR_CORDICEN
+#endif /* CORDIC */
#if defined(BDMA1)
#define LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN
#endif /* BDMA1 */
@@ -197,7 +203,9 @@
#define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN
#define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN
#define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN
+#if defined(GPIOI)
#define LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN
+#endif /* GPIOI */
#define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN
#define LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN
#if defined(RCC_AHB4ENR_CRCEN)
@@ -232,7 +240,9 @@
/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
* @{
*/
+#if defined(LTDC)
#define LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN
+#endif /* LTDC */
#if defined(DSI)
#define LL_APB3_GRP1_PERIPH_DSI RCC_APB3ENR_DSIEN
#endif /* DSI */
@@ -271,7 +281,15 @@
#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN
#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN
#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN
+#if defined(I2C5)
+#define LL_APB1_GRP1_PERIPH_I2C5 RCC_APB1LENR_I2C5EN
+#endif /* I2C5 */
+#if defined(RCC_APB1LENR_CECEN)
#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN
+#else
+#define LL_APB1_GRP1_PERIPH_HDMICEC RCC_APB1LENR_HDMICECEN
+#define LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_HDMICEC /* for backward compatibility*/
+#endif /* RCC_APB1LENR_CECEN */
#define LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN
#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN
#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN
@@ -288,6 +306,12 @@
#define LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN
#define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN
#define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN
+#if defined(TIM23)
+#define LL_APB1_GRP2_PERIPH_TIM23 RCC_APB1HENR_TIM23EN
+#endif /* TIM23 */
+#if defined(TIM24)
+#define LL_APB1_GRP2_PERIPH_TIM24 RCC_APB1HENR_TIM24EN
+#endif /* TIM24 */
/**
* @}
*/
@@ -313,7 +337,9 @@
#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
+#if defined(SAI2)
#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
+#endif /* SAI2 */
#if defined(SAI3)
#define LL_APB2_GRP1_PERIPH_SAI3 RCC_APB2ENR_SAI3EN
#endif /* SAI3 */
@@ -367,7 +393,7 @@
#define LL_CLKAM_PERIPH_BDMA RCC_D3AMR_BDMAAMEN
#else
#define LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN
-#define LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
+#define LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
#endif /* RCC_D3AMR_BDMAAMEN */
#if defined(RCC_SRDAMR_GPIOAMEN)
#define LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN
@@ -430,9 +456,12 @@
#if defined(ADC3)
#define LL_CLKAM_PERIPH_ADC3 RCC_D3AMR_ADC3AMEN
#endif /* ADC3 */
-#if defined(DTS)
+#if defined(RCC_SRDAMR_DTSAMEN)
#define LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN
-#endif /* DTS */
+#endif /* RCC_SRDAMR_DTSAMEN */
+#if defined(RCC_D3AMR_DTSAMEN)
+#define LL_CLKAM_PERIPH_DTS RCC_D3AMR_DTSAMEN
+#endif /* RCC_D3AMR_DTSAMEN */
#if defined(DFSDM2_BASE)
#define LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN
#endif /* DFSDM2_BASE */
@@ -481,6 +510,10 @@
*/
#endif /* RCC_CKGAENR_AXICKG */
+/**
+ * @}
+ */
+
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
@@ -529,7 +562,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
*
* (*) value not defined in all devices.
* @retval None
@@ -570,7 +603,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
@@ -579,7 +612,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
*
* (*) value not defined in all devices.
* @retval uint32_t
@@ -613,10 +646,10 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
* @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
@@ -625,7 +658,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
*
* (*) value not defined in all devices.
* @retval None
@@ -640,7 +673,7 @@
* @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ForceReset\n
* AHB3RSTR DMA2DRST LL_AHB3_GRP1_ForceReset\n
* AHB3RSTR JPGDECRST LL_AHB3_GRP1_ForceReset\n
- * AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
+ * AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
* AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n (*)
* AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n (*)
* AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset\n (*)
@@ -654,13 +687,13 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
* @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
*
* (*) value not defined in all devices.
@@ -690,13 +723,13 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
* @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
*
* (*) value not defined in all devices.
@@ -734,9 +767,9 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
@@ -783,9 +816,9 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
@@ -1067,6 +1100,8 @@
* AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR BDMA1EN LL_AHB2_GRP1_EnableClock\n (*)
+ * AHB2ENR FMACEN LL_AHB2_GRP1_EnableClock\n
+ * AHB2ENR CORDICEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock (*)
@@ -1077,7 +1112,9 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
@@ -1103,17 +1140,21 @@
* AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR BDMA1EN LL_AHB2_GRP1_IsEnabledClock\n (*)
+ * AHB2ENR FMACEN LL_AHB2_GRP1_IsEnabledClock\n
+ * AHB2ENR CORDICEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
- * @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
@@ -1135,17 +1176,21 @@
* AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR BDMA1EN LL_AHB2_GRP1_DisableClock\n (*)
+ * AHB2ENR FMACEN LL_AHB2_GRP1_DisableClock\n
+ * AHB2ENR CORDICEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
- * @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
@@ -1167,6 +1212,8 @@
* AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset (*)
+ * AHB2RSTR FMACRST LL_AHB2_GRP1_ForceReset\n
+ * AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
* @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
@@ -1174,7 +1221,9 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
*
* (*) value not defined in all devices.
* @retval None
@@ -1193,13 +1242,18 @@
* AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset (*)
+ * AHB2RSTR FMACRST LL_AHB2_GRP1_ReleaseReset\n
+ * AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset
* @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
* @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
*
* (*) value not defined in all devices.
* @retval None
@@ -1212,21 +1266,25 @@
/**
* @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode.
* @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep\n
- * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
- * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
+ * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
+ * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
* AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n
* AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n
* AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
+ * AHB2LPENR FMACLPEN LL_AHB2_GRP1_EnableClockSleep\n
+ * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_EnableClockSleep\n
* AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n
* AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n
- * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*)
+ * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
@@ -1260,7 +1318,9 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
@@ -1291,7 +1351,7 @@
* AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n
* AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n
* AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n
- * AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock\n
+ * AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock\n (*)
* AHB4ENR GPIOJEN LL_AHB4_GRP1_EnableClock\n
* AHB4ENR GPIOKEN LL_AHB4_GRP1_EnableClock\n
* AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n (*)
@@ -1309,7 +1369,7 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
* @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
@@ -1341,7 +1401,7 @@
* AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n
* AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n
* AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n
- * AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock\n
+ * AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock\n (*)
* AHB4ENR GPIOJEN LL_AHB4_GRP1_IsEnabledClock\n
* AHB4ENR GPIOKEN LL_AHB4_GRP1_IsEnabledClock\n
* AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n (*)
@@ -1359,13 +1419,13 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
* @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
*
@@ -1387,7 +1447,7 @@
* AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n
* AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n
* AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n
- * AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock\n
+ * AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock\n (*)
* AHB4ENR GPIOJEN LL_AHB4_GRP1_DisableClock\n
* AHB4ENR GPIOKEN LL_AHB4_GRP1_DisableClock\n
* AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n (*)
@@ -1405,13 +1465,13 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
* @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
*
@@ -1433,7 +1493,7 @@
* AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n
* AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n
* AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n
- * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset\n
+ * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset\n (*)
* AHB4RSTR GPIOJRST LL_AHB4_GRP1_ForceReset\n
* AHB4RSTR GPIOKRST LL_AHB4_GRP1_ForceReset\n
* AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n (*)
@@ -1449,13 +1509,13 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
*
* (*) value not defined in all devices.
* @retval None
@@ -1475,7 +1535,7 @@
* AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n
* AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n
* AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n
- * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset\n
+ * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset\n (*)
* AHB4RSTR GPIOJRST LL_AHB4_GRP1_ReleaseReset\n
* AHB4RSTR GPIOKRST LL_AHB4_GRP1_ReleaseReset\n
* AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset\n (*)
@@ -1491,13 +1551,13 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
*
* (*) value not defined in all devices.
* @retval None
@@ -1517,7 +1577,7 @@
* AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n
* AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n
* AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n
- * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep\n
+ * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep\n (*)
* AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_EnableClockSleep\n
* AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_EnableClockSleep\n
* AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n (*)
@@ -1534,10 +1594,10 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
@@ -1563,7 +1623,7 @@
* AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n
* AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n
* AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n
- * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep\n
+ * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep\n (*)
* AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_DisableClockSleep\n
* AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_DisableClockSleep\n
* AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n (*)
@@ -1580,10 +1640,10 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
@@ -1764,6 +1824,7 @@
* APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n
* APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n
* APB1LENR I2C3EN LL_APB1_GRP1_EnableClock\n
+ * APB1LENR I2C5EN LL_APB1_GRP1_EnableClock\n (*)
* APB1LENR CECEN LL_APB1_GRP1_EnableClock\n
* APB1LENR DAC12EN LL_APB1_GRP1_EnableClock\n
* APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n
@@ -1790,6 +1851,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_CEC
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
@@ -1830,6 +1892,7 @@
* APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
* APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
* APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1LENR I2C5EN LL_APB1_GRP1_IsEnabledClock\n (*)
* APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n
* APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock\n
* APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
@@ -1856,6 +1919,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_CEC
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
@@ -1892,6 +1956,7 @@
* APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n
* APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n
* APB1LENR I2C3EN LL_APB1_GRP1_DisableClock\n
+ * APB1LENR I2C5EN LL_APB1_GRP1_DisableClock\n (*)
* APB1LENR CECEN LL_APB1_GRP1_DisableClock\n
* APB1LENR DAC12EN LL_APB1_GRP1_DisableClock\n
* APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n
@@ -1918,6 +1983,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_CEC
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
@@ -1953,6 +2019,7 @@
* APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n
* APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n
* APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset\n
+ * APB1LRSTR I2C5RST LL_APB1_GRP5_ForceReset\n (*)
* APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n
* APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset\n
* APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n
@@ -1978,10 +2045,13 @@
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_CEC
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
* @arg @ref LL_APB1_GRP1_PERIPH_UART8
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
@@ -2011,6 +2081,7 @@
* APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
* APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
* APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1LRSTR I2C5RST LL_APB1_GRP1_ReleaseReset\n (*)
* APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n
* APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset\n
* APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
@@ -2036,10 +2107,13 @@
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_CEC
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
* @arg @ref LL_APB1_GRP1_PERIPH_UART8
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
@@ -2070,6 +2144,7 @@
* APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
* APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
* APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n
+ * APB1LLPENR I2C5LPEN LL_APB1_GRP1_EnableClockSleep\n (*)
* APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n
* APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n
* APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n
@@ -2096,6 +2171,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_CEC
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
@@ -2136,6 +2212,7 @@
* APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
* APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
* APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n
+ * APB1LLPENR I2C5LPEN LL_APB1_GRP1_DisableClockSleep\n (*)
* APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n
* APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep\n
* APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n
@@ -2162,6 +2239,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_CEC
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
@@ -2188,6 +2266,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
@@ -2212,6 +2294,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval uint32_t
*/
__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
@@ -2232,6 +2318,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
@@ -2252,6 +2342,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
@@ -2272,6 +2366,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
@@ -2292,6 +2390,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
@@ -2316,6 +2418,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
@@ -2364,7 +2470,7 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
@@ -2414,8 +2520,8 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
*
@@ -2460,8 +2566,8 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
*
@@ -2506,10 +2612,10 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
*
* (*) value not defined in all devices.
* @retval None
@@ -2552,10 +2658,10 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
*
* (*) value not defined in all devices.
* @retval None
@@ -2598,10 +2704,12 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
@@ -2646,10 +2754,12 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
@@ -2695,7 +2805,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -2741,7 +2851,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -2783,7 +2893,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -2810,7 +2920,7 @@
* APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n
* APB4RSTR SAI4RST LL_APB4_GRP1_ForceReset\n (*)
* APB4RSTR DTSRST LL_APB4_GRP1_ForceReset\n (*)
- * APB4RSTR DFSDM2RST LL_APB4_GRP1_ForceReset (*)
+ * APB4RSTR DFSDM2RST LL_APB4_GRP1_ForceReset (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
@@ -2823,7 +2933,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -2863,7 +2973,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -2905,7 +3015,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -2951,7 +3061,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -2967,7 +3077,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_CLKAM
+/** @defgroup BUS_LL_EF_CLKAM CLKAM
* @{
*/
@@ -2994,6 +3104,7 @@
* D3AMR / SRDAMR SRAM4 LL_CLKAM_Enable
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_CLKAM_PERIPH_BDMA
+ * @arg @ref LL_CLKAM_PERIPH_GPIO (*)
* @arg @ref LL_CLKAM_PERIPH_LPUART1
* @arg @ref LL_CLKAM_PERIPH_SPI6
* @arg @ref LL_CLKAM_PERIPH_I2C4
@@ -3005,9 +3116,9 @@
* @arg @ref LL_CLKAM_PERIPH_COMP12
* @arg @ref LL_CLKAM_PERIPH_VREF
* @arg @ref LL_CLKAM_PERIPH_RTC
- * @arg @ref LL_CLKAM_PERIPH_CRC
- * @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
- * @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
+ * @arg @ref LL_CLKAM_PERIPH_CRC (*)
+ * @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
+ * @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
* @arg @ref LL_CLKAM_PERIPH_DTS (*)
* @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
* @arg @ref LL_CLKAM_PERIPH_BKPRAM
@@ -3055,6 +3166,7 @@
* D3AMR / SRDAMR SRAM4 LL_CLKAM_Disable
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_CLKAM_PERIPH_BDMA
+ * @arg @ref LL_CLKAM_PERIPH_GPIO (*)
* @arg @ref LL_CLKAM_PERIPH_LPUART1
* @arg @ref LL_CLKAM_PERIPH_SPI6
* @arg @ref LL_CLKAM_PERIPH_I2C4
@@ -3066,10 +3178,10 @@
* @arg @ref LL_CLKAM_PERIPH_COMP12
* @arg @ref LL_CLKAM_PERIPH_VREF
* @arg @ref LL_CLKAM_PERIPH_RTC
- * @arg @ref LL_CLKAM_PERIPH_CRC
+ * @arg @ref LL_CLKAM_PERIPH_CRC (*)
* @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
* @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
- * @arg @ref LL_CLKAM_PERIPH_DTS (*)
+ * @arg @ref LL_CLKAM_PERIPH_DTS (*)
* @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
* @arg @ref LL_CLKAM_PERIPH_BKPRAM
* @arg @ref LL_CLKAM_PERIPH_SRAM4
@@ -3086,11 +3198,17 @@
#endif /* RCC_D3AMR_BDMAAMEN */
}
-#if defined(RCC_CKGAENR_AXICKG)
/**
* @}
*/
+/** @defgroup BUS_LL_EF_CKGA CKGA
+ * @{
+ */
+
+#if defined(RCC_CKGAENR_AXICKG)
+
+
/**
* @brief Enable clock gating for AXI bus peripherals.
* @rmtoll
@@ -3105,15 +3223,10 @@
tmpreg = READ_BIT(RCC->CKGAENR, Periphs);
(void)tmpreg;
}
-/**
- * @}
- */
+
#endif /* RCC_CKGAENR_AXICKG */
#if defined(RCC_CKGAENR_AXICKG)
-/**
- * @}
- */
/**
* @brief Disable clock gating for AXI bus peripherals.
@@ -3125,14 +3238,15 @@
{
CLEAR_BIT(RCC->CKGAENR, Periphs);
}
+
+#endif /* RCC_CKGAENR_AXICKG */
+
/**
* @}
*/
-#endif /* RCC_CKGAENR_AXICKG */
-
#if defined(DUAL_CORE)
-/** @defgroup BUS_LL_EF_AHB3 AHB3
+/** @addtogroup BUS_LL_EF_AHB3 AHB3
* @{
*/
@@ -3158,7 +3272,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
@@ -3198,7 +3312,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
@@ -3229,12 +3343,12 @@
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
- * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+ * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
@@ -3269,15 +3383,15 @@
* AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
- * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+ * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
@@ -3318,15 +3432,15 @@
* AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
- * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+ * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
- * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+ * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
@@ -3346,7 +3460,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_AHB1 AHB1
+/** @addtogroup BUS_LL_EF_AHB1 AHB1
* @{
*/
@@ -3368,8 +3482,8 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
@@ -3408,8 +3522,8 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
@@ -3444,8 +3558,8 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
@@ -3480,8 +3594,8 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
@@ -3520,8 +3634,8 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
@@ -3542,7 +3656,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_AHB2 AHB2
+/** @addtogroup BUS_LL_EF_AHB2 AHB2
* @{
*/
@@ -3564,7 +3678,7 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
@@ -3600,7 +3714,7 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
@@ -3632,7 +3746,7 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
@@ -3653,7 +3767,7 @@
* AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
* AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
* AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
- * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
+ * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
* AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
* AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
* AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_EnableClockSleep (*)
@@ -3663,7 +3777,7 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
@@ -3697,7 +3811,7 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
- * @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)
+ * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
@@ -3714,7 +3828,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_AHB4 AHB4
+/** @addtogroup BUS_LL_EF_AHB4 AHB4
* @{
*/
@@ -3746,13 +3860,13 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
* @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
*
@@ -3796,13 +3910,13 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
* @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
*
@@ -3842,13 +3956,13 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
* @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
*
@@ -3887,10 +4001,10 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
@@ -3933,10 +4047,10 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
@@ -3952,7 +4066,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_APB3 APB3
+/** @addtogroup BUS_LL_EF_APB3 APB3
* @{
*/
@@ -3963,7 +4077,7 @@
* APB3ENR WWDG1EN LL_C1_APB3_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
- * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+ * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
*
* (*) value not defined in all devices.
@@ -3985,7 +4099,7 @@
* APB3ENR WWDG1EN LL_C1_APB3_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
- * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+ * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
*
* (*) value not defined in all devices.
@@ -4003,7 +4117,8 @@
* APB3ENR WWDG1EN LL_C1_APB3_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
- * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+
+ * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
*
* (*) value not defined in all devices.
@@ -4021,7 +4136,7 @@
* APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
- * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+ * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
*
* (*) value not defined in all devices.
@@ -4043,7 +4158,7 @@
* APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
- * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+ * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
*
* (*) value not defined in all devices.
@@ -4058,7 +4173,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_APB1 APB1
+/** @addtogroup BUS_LL_EF_APB1 APB1
* @{
*/
@@ -4393,6 +4508,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)
@@ -4417,6 +4536,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval uint32_t
*/
__STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
@@ -4437,6 +4560,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)
@@ -4457,6 +4584,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
@@ -4481,6 +4612,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
@@ -4492,7 +4627,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_APB2 APB2
+/** @addtogroup BUS_LL_EF_APB2 APB2
* @{
*/
@@ -4529,8 +4664,8 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
*
@@ -4579,8 +4714,8 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
*
@@ -4615,6 +4750,7 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART6
* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
@@ -4624,8 +4760,8 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
*
@@ -4660,6 +4796,7 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART6
* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
@@ -4669,8 +4806,8 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
*
@@ -4709,6 +4846,7 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART6
* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
@@ -4718,8 +4856,8 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
*
@@ -4735,7 +4873,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_APB4 APB4
+/** @addtogroup BUS_LL_EF_APB4 APB4
* @{
*/
@@ -4768,7 +4906,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -4811,8 +4949,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
- * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -4852,7 +4989,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -4877,9 +5014,9 @@
* APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
* APB4LPENR VREFLPEN LL_C1_APB4_GRP1_EnableClockSleep\n
* APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_EnableClockSleep\n
- * APB4ENR SAI4EN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
- * APB4ENR DTSEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
- * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_EnableClockSleep (*)
+ * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+ * APB4ENR DTSLPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+ * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_EnableClockSleep (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
@@ -4892,7 +5029,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -4921,9 +5058,9 @@
* APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
* APB4LPENR VREFLPEN LL_C1_APB4_GRP1_DisableClockSleep\n
* APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_DisableClockSleep\n
- * APB4ENR SAI4EN LL_C1_APB4_GRP1_DisableClockSleep\n (*)
- * APB4ENR DTSEN LL_C1_APB4_GRP1_DisableClockSleep\n (*)
- * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_DisableClockSleep (*)
+ * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*)
+ * APB4ENR DTSLPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*)
+ * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_DisableClockSleep (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
@@ -4936,7 +5073,7 @@
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
* @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
*
@@ -4952,7 +5089,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_AHB3 AHB3
+/** @addtogroup BUS_LL_EF_AHB3 AHB3
* @{
*/
@@ -4972,9 +5109,9 @@
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
- * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+ * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
@@ -5008,9 +5145,9 @@
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
- * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+ * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
@@ -5040,9 +5177,9 @@
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
- * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+ * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
@@ -5071,9 +5208,9 @@
* AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
- * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+ * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
@@ -5106,9 +5243,9 @@
* AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
- * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+ * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
- * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+ * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
@@ -5126,7 +5263,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_AHB1 AHB1
+/** @addtogroup BUS_LL_EF_AHB1 AHB1
* @{
*/
@@ -5147,14 +5284,16 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB1_GRP1_PERIPH_ART
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
- * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
- * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+ * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
@@ -5183,14 +5322,16 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB1_GRP1_PERIPH_ART
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
- * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
- * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+ * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+ *
+ * (*) value not defined in all devices.
* @retval uint32_t
*/
__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
@@ -5215,14 +5356,16 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB1_GRP1_PERIPH_ART
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
- * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
- * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+ * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
@@ -5247,14 +5390,16 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB1_GRP1_PERIPH_ART
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
- * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
- * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+ * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
@@ -5283,14 +5428,16 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
- * @arg @ref LL_AHB1_GRP1_PERIPH_ART
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
- * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
- * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+ * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
@@ -5302,7 +5449,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_AHB2 AHB2
+/** @addtogroup BUS_LL_EF_AHB2 AHB2
* @{
*/
@@ -5394,7 +5541,7 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
- * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
+ * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
*
* (*) value not defined in all devices.
* @retval None
@@ -5426,7 +5573,7 @@
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
- * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
+ * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
*
* (*) value not defined in all devices.
* @retval None
@@ -5440,7 +5587,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_AHB4 AHB4
+/** @addtogroup BUS_LL_EF_AHB4 AHB4
* @{
*/
@@ -5472,13 +5619,13 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
- * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
- * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
* @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
*
@@ -5522,13 +5669,13 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
- * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
- * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
* @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
*
@@ -5568,13 +5715,13 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
- * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
- * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
* @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
*
@@ -5613,12 +5760,12 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
- * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+ * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
* @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
* @retval None
@@ -5659,12 +5806,12 @@
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+ * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
- * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
- * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+ * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
* @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
* @retval None
@@ -5678,7 +5825,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_APB3 APB3
+/** @addtogroup BUS_LL_EF_APB3 APB3
* @{
*/
@@ -5688,7 +5835,7 @@
* APB3ENR DSIEN LL_C2_APB3_GRP1_EnableClock\n
* APB3ENR WWDG1EN LL_C2_APB3_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+ * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
*
@@ -5710,7 +5857,7 @@
* APB3ENR DSIEN LL_C2_APB3_GRP1_IsEnabledClock\n
* APB3ENR WWDG1EN LL_C2_APB3_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+ * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
*
@@ -5728,7 +5875,7 @@
* APB3ENR DSIEN LL_C2_APB3_GRP1_DisableClock\n
* APB3ENR WWDG1EN LL_C2_APB3_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+ * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
*
@@ -5746,7 +5893,7 @@
* APB3LPENR DSILPEN LL_C2_APB3_GRP1_EnableClockSleep\n
* APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_EnableClockSleep
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+ * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
*
@@ -5768,7 +5915,7 @@
* APB3LPENR DSILPEN LL_C2_APB3_GRP1_DisableClockSleep\n
* APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_DisableClockSleep
* @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+ * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
*
@@ -5784,7 +5931,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_APB1 APB1
+/** @addtogroup BUS_LL_EF_APB1 APB1
* @{
*/
@@ -5826,7 +5973,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
@@ -5841,6 +5988,8 @@
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
* @arg @ref LL_APB1_GRP1_PERIPH_UART8
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
@@ -5890,7 +6039,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
@@ -5905,6 +6054,8 @@
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
* @arg @ref LL_APB1_GRP1_PERIPH_UART8
+ *
+ * (*) value not defined in all devices.
* @retval uint32_t
*/
__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
@@ -5950,7 +6101,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
@@ -5965,6 +6116,8 @@
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
* @arg @ref LL_APB1_GRP1_PERIPH_UART8
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
@@ -6010,7 +6163,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
@@ -6025,6 +6178,8 @@
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
* @arg @ref LL_APB1_GRP1_PERIPH_UART8
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
@@ -6074,7 +6229,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
@@ -6089,6 +6244,8 @@
* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
* @arg @ref LL_APB1_GRP1_PERIPH_UART7
* @arg @ref LL_APB1_GRP1_PERIPH_UART8
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
@@ -6109,6 +6266,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
@@ -6133,6 +6294,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval uint32_t
*/
__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
@@ -6153,6 +6318,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
@@ -6173,6 +6342,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
@@ -6197,6 +6370,10 @@
* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
+ * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
@@ -6208,7 +6385,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_APB2 APB2
+/** @addtogroup BUS_LL_EF_APB2 APB2
* @{
*/
@@ -6241,10 +6418,13 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+ *
+ * (*) value not defined in all devices.
+
* @retval None
*/
__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
@@ -6285,10 +6465,12 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+ *
+ * (*) value not defined in all devices.
* @retval uint32_t
*/
__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
@@ -6325,10 +6507,12 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
@@ -6365,10 +6549,12 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
@@ -6409,10 +6595,12 @@
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
- * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
- * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
@@ -6424,7 +6612,7 @@
* @}
*/
-/** @defgroup BUS_LL_EF_APB4 APB4
+/** @addtogroup BUS_LL_EF_APB4 APB4
* @{
*/
@@ -6449,12 +6637,14 @@
* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
- * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
- * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+ * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ *
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)
@@ -6487,12 +6677,14 @@
* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
- * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
- * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+ * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ *
+ * (*) value not defined in all devices
* @retval uint32_t
*/
__STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
@@ -6521,12 +6713,14 @@
* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
- * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
- * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+ * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ *
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)
@@ -6555,12 +6749,14 @@
* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
- * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
- * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+ * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ *
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
@@ -6593,12 +6789,14 @@
* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
- * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
- * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+ * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+ * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
* @arg @ref LL_APB4_GRP1_PERIPH_VREF
* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
- * @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+ * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
+ *
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
diff --git a/Inc/stm32h7xx_ll_comp.h b/Inc/stm32h7xx_ll_comp.h
index 243c89d..e75c0bd 100644
--- a/Inc/stm32h7xx_ll_comp.h
+++ b/Inc/stm32h7xx_ll_comp.h
@@ -417,16 +417,12 @@
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
-#if defined (COMP_CFGRx_INMSEL_3)
* @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1
* @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP
-#endif
* @param InputPlus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
-#if defined (COMP_CFGRx_INP2SEL)
* @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1
-#endif
* @retval None
*/
__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
@@ -455,9 +451,7 @@
* @param InputPlus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
-#if defined (COMP_CFGRx_INP2SEL)
* @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1
-#endif
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
@@ -479,9 +473,7 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
-#if defined (COMP_CFGRx_INP2SEL)
* @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1
-#endif
*/
__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
{
@@ -522,10 +514,8 @@
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
-#if defined (COMP_CFGRx_INMSEL_3)
* @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1
* @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP
-#endif
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
@@ -551,10 +541,8 @@
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
-#if defined (COMP_CFGRx_INMSEL_3)
* @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1
* @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP
-#endif
*/
__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
{
diff --git a/Inc/stm32h7xx_ll_cordic.h b/Inc/stm32h7xx_ll_cordic.h
new file mode 100644
index 0000000..b46705f
--- /dev/null
+++ b/Inc/stm32h7xx_ll_cordic.h
@@ -0,0 +1,777 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_ll_cordic.h
+ * @author MCD Application Team
+ * @brief Header file of CORDIC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_CORDIC_H
+#define STM32H7xx_LL_CORDIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+ * @{
+ */
+
+#if defined(CORDIC)
+
+/** @defgroup CORDIC_LL CORDIC
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORDIC_LL_Exported_Constants CORDIC Exported Constants
+ * @{
+ */
+
+/** @defgroup CORDIC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_CORDIC_ReadReg function.
+ * @{
+ */
+#define LL_CORDIC_FLAG_RRDY CORDIC_CSR_RRDY
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_CORDIC_ReadReg and LL_CORDIC_WriteReg functions.
+ * @{
+ */
+#define LL_CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result Ready interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_FUNCTION FUNCTION
+ * @{
+ */
+#define LL_CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */
+#define LL_CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */
+#define LL_CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */
+#define LL_CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */
+#define LL_CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */
+#define LL_CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */
+#define LL_CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */
+#define LL_CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
+#define LL_CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
+#define LL_CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_PRECISION PRECISION
+ * @{
+ */
+#define LL_CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
+#define LL_CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
+#define LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
+#define LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
+#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
+#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_SCALE SCALE
+ * @{
+ */
+#define LL_CORDIC_SCALE_0 (0x00000000U)
+#define LL_CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
+#define LL_CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
+#define LL_CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
+#define LL_CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
+#define LL_CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
+#define LL_CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
+#define LL_CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE
+ * @{
+ */
+#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
+ 32-bit data input (Q1.31 format), or two 16-bit
+ data input (Q1.15 format) packed in one 32 bits Data */
+#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
+ (Q1.31 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_NBREAD NBREAD
+ * @{
+ */
+#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
+ 32-bit data ouput (Q1.31 format), or two 16-bit
+ data output (Q1.15 format) packed in one 32 bits Data */
+#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
+ (Q1.31 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_INSIZE INSIZE
+ * @{
+ */
+#define LL_CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
+#define LL_CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_OUTSIZE OUTSIZE
+ * @{
+ */
+#define LL_CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
+#define LL_CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EC_DMA_REG_DATA DMA register data
+ * @{
+ */
+#define LL_CORDIC_DMA_REG_DATA_IN (0x00000000U) /*!< Get address of input data register */
+#define LL_CORDIC_DMA_REG_DATA_OUT (0x00000001U) /*!< Get address of output data register */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CORDIC_LL_Exported_Macros CORDIC Exported Macros
+ * @{
+ */
+
+/** @defgroup CORDIC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in CORDIC register.
+ * @param __INSTANCE__ CORDIC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_CORDIC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in CORDIC register.
+ * @param __INSTANCE__ CORDIC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_CORDIC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions
+ * @{
+ */
+
+/** @defgroup CORDIC_LL_EF_Configuration CORDIC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Configure the CORDIC processing.
+ * @note This function set all parameters of CORDIC processing.
+ * These parameters can also be set individually using
+ * dedicated functions:
+ * - @ref LL_CORDIC_SetFunction()
+ * - @ref LL_CORDIC_SetPrecision()
+ * - @ref LL_CORDIC_SetScale()
+ * - @ref LL_CORDIC_SetNbWrite()
+ * - @ref LL_CORDIC_SetNbRead()
+ * - @ref LL_CORDIC_SetInSize()
+ * - @ref LL_CORDIC_SetOutSize()
+ * @rmtoll CSR FUNC LL_CORDIC_Configure\n
+ * CSR PRECISION LL_CORDIC_Configure\n
+ * CSR SCALE LL_CORDIC_Configure\n
+ * CSR NARGS LL_CORDIC_Configure\n
+ * CSR NRES LL_CORDIC_Configure\n
+ * CSR ARGSIZE LL_CORDIC_Configure\n
+ * CSR RESSIZE LL_CORDIC_Configure
+ * @param CORDICx CORDIC instance
+ * @param Function parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_FUNCTION_COSINE
+ * @arg @ref LL_CORDIC_FUNCTION_SINE
+ * @arg @ref LL_CORDIC_FUNCTION_PHASE
+ * @arg @ref LL_CORDIC_FUNCTION_MODULUS
+ * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_HCOSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
+ * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
+ * @param Precision parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_PRECISION_1CYCLE
+ * @arg @ref LL_CORDIC_PRECISION_2CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_3CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_4CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_5CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_6CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_7CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_8CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_9CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_10CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_11CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_12CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_13CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_14CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_15CYCLES
+ * @param Scale parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_SCALE_0
+ * @arg @ref LL_CORDIC_SCALE_1
+ * @arg @ref LL_CORDIC_SCALE_2
+ * @arg @ref LL_CORDIC_SCALE_3
+ * @arg @ref LL_CORDIC_SCALE_4
+ * @arg @ref LL_CORDIC_SCALE_5
+ * @arg @ref LL_CORDIC_SCALE_6
+ * @arg @ref LL_CORDIC_SCALE_7
+ * @param NbWrite parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_NBWRITE_1
+ * @arg @ref LL_CORDIC_NBWRITE_2
+ * @param NbRead parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_NBREAD_1
+ * @arg @ref LL_CORDIC_NBREAD_2
+ * @param InSize parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_INSIZE_32BITS
+ * @arg @ref LL_CORDIC_INSIZE_16BITS
+ * @param OutSize parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_OUTSIZE_32BITS
+ * @arg @ref LL_CORDIC_OUTSIZE_16BITS
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale, uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
+{
+ MODIFY_REG(CORDICx->CSR,
+ CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE |
+ CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE,
+ Function | Precision | Scale |
+ NbWrite | NbRead | InSize | OutSize);
+}
+
+/**
+ * @brief Configure function.
+ * @rmtoll CSR FUNC LL_CORDIC_SetFunction
+ * @param CORDICx CORDIC Instance
+ * @param Function parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_FUNCTION_COSINE
+ * @arg @ref LL_CORDIC_FUNCTION_SINE
+ * @arg @ref LL_CORDIC_FUNCTION_PHASE
+ * @arg @ref LL_CORDIC_FUNCTION_MODULUS
+ * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_HCOSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
+ * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetFunction(CORDIC_TypeDef *CORDICx, uint32_t Function)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_FUNC, Function);
+}
+
+/**
+ * @brief Return function.
+ * @rmtoll CSR FUNC LL_CORDIC_GetFunction
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_FUNCTION_COSINE
+ * @arg @ref LL_CORDIC_FUNCTION_SINE
+ * @arg @ref LL_CORDIC_FUNCTION_PHASE
+ * @arg @ref LL_CORDIC_FUNCTION_MODULUS
+ * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_HCOSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HSINE
+ * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
+ * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
+ * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_FUNC));
+}
+
+/**
+ * @brief Configure precision in cycles number.
+ * @rmtoll CSR PRECISION LL_CORDIC_SetPrecision
+ * @param CORDICx CORDIC Instance
+ * @param Precision parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_PRECISION_1CYCLE
+ * @arg @ref LL_CORDIC_PRECISION_2CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_3CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_4CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_5CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_6CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_7CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_8CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_9CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_10CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_11CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_12CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_13CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_14CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_15CYCLES
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetPrecision(CORDIC_TypeDef *CORDICx, uint32_t Precision)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_PRECISION, Precision);
+}
+
+/**
+ * @brief Return precision in cycles number.
+ * @rmtoll CSR PRECISION LL_CORDIC_GetPrecision
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_PRECISION_1CYCLE
+ * @arg @ref LL_CORDIC_PRECISION_2CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_3CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_4CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_5CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_6CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_7CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_8CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_9CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_10CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_11CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_12CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_13CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_14CYCLES
+ * @arg @ref LL_CORDIC_PRECISION_15CYCLES
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_PRECISION));
+}
+
+/**
+ * @brief Configure scaling factor.
+ * @rmtoll CSR SCALE LL_CORDIC_SetScale
+ * @param CORDICx CORDIC Instance
+ * @param Scale parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_SCALE_0
+ * @arg @ref LL_CORDIC_SCALE_1
+ * @arg @ref LL_CORDIC_SCALE_2
+ * @arg @ref LL_CORDIC_SCALE_3
+ * @arg @ref LL_CORDIC_SCALE_4
+ * @arg @ref LL_CORDIC_SCALE_5
+ * @arg @ref LL_CORDIC_SCALE_6
+ * @arg @ref LL_CORDIC_SCALE_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetScale(CORDIC_TypeDef *CORDICx, uint32_t Scale)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_SCALE, Scale);
+}
+
+/**
+ * @brief Return scaling factor.
+ * @rmtoll CSR SCALE LL_CORDIC_GetScale
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_SCALE_0
+ * @arg @ref LL_CORDIC_SCALE_1
+ * @arg @ref LL_CORDIC_SCALE_2
+ * @arg @ref LL_CORDIC_SCALE_3
+ * @arg @ref LL_CORDIC_SCALE_4
+ * @arg @ref LL_CORDIC_SCALE_5
+ * @arg @ref LL_CORDIC_SCALE_6
+ * @arg @ref LL_CORDIC_SCALE_7
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetScale(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_SCALE));
+}
+
+/**
+ * @brief Configure number of 32-bit write expected for one calculation.
+ * @rmtoll CSR NARGS LL_CORDIC_SetNbWrite
+ * @param CORDICx CORDIC Instance
+ * @param NbWrite parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_NBWRITE_1
+ * @arg @ref LL_CORDIC_NBWRITE_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *CORDICx, uint32_t NbWrite)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NARGS, NbWrite);
+}
+
+/**
+ * @brief Return number of 32-bit write expected for one calculation.
+ * @rmtoll CSR NARGS LL_CORDIC_GetNbWrite
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_NBWRITE_1
+ * @arg @ref LL_CORDIC_NBWRITE_2
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NARGS));
+}
+
+/**
+ * @brief Configure number of 32-bit read expected after one calculation.
+ * @rmtoll CSR NRES LL_CORDIC_SetNbRead
+ * @param CORDICx CORDIC Instance
+ * @param NbRead parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_NBREAD_1
+ * @arg @ref LL_CORDIC_NBREAD_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetNbRead(CORDIC_TypeDef *CORDICx, uint32_t NbRead)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NRES, NbRead);
+}
+
+/**
+ * @brief Return number of 32-bit read expected after one calculation.
+ * @rmtoll CSR NRES LL_CORDIC_GetNbRead
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_NBREAD_1
+ * @arg @ref LL_CORDIC_NBREAD_2
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NRES));
+}
+
+/**
+ * @brief Configure width of input data.
+ * @rmtoll CSR ARGSIZE LL_CORDIC_SetInSize
+ * @param CORDICx CORDIC Instance
+ * @param InSize parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_INSIZE_32BITS
+ * @arg @ref LL_CORDIC_INSIZE_16BITS
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetInSize(CORDIC_TypeDef *CORDICx, uint32_t InSize)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_ARGSIZE, InSize);
+}
+
+/**
+ * @brief Return width of input data.
+ * @rmtoll CSR ARGSIZE LL_CORDIC_GetInSize
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_INSIZE_32BITS
+ * @arg @ref LL_CORDIC_INSIZE_16BITS
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_ARGSIZE));
+}
+
+/**
+ * @brief Configure width of output data.
+ * @rmtoll CSR RESSIZE LL_CORDIC_SetOutSize
+ * @param CORDICx CORDIC Instance
+ * @param OutSize parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_OUTSIZE_32BITS
+ * @arg @ref LL_CORDIC_OUTSIZE_16BITS
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutSize)
+{
+ MODIFY_REG(CORDICx->CSR, CORDIC_CSR_RESSIZE, OutSize);
+}
+
+/**
+ * @brief Return width of output data.
+ * @rmtoll CSR RESSIZE LL_CORDIC_GetOutSize
+ * @param CORDICx CORDIC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CORDIC_OUTSIZE_32BITS
+ * @arg @ref LL_CORDIC_OUTSIZE_16BITS
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_RESSIZE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable CORDIC result ready interrupt
+ * @rmtoll CSR IEN LL_CORDIC_EnableIT
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_EnableIT(CORDIC_TypeDef *CORDICx)
+{
+ SET_BIT(CORDICx->CSR, CORDIC_CSR_IEN);
+}
+
+/**
+ * @brief Disable CORDIC result ready interrupt
+ * @rmtoll CSR IEN LL_CORDIC_DisableIT
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_DisableIT(CORDIC_TypeDef *CORDICx)
+{
+ CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_IEN);
+}
+
+/**
+ * @brief Check CORDIC result ready interrupt state.
+ * @rmtoll CSR IEN LL_CORDIC_IsEnabledIT
+ * @param CORDICx CORDIC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(CORDIC_TypeDef *CORDICx)
+{
+ return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_IEN) == (CORDIC_CSR_IEN)) ? 1U : 0U);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable CORDIC DMA read channel request.
+ * @rmtoll CSR DMAREN LL_CORDIC_EnableDMAReq_RD
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_EnableDMAReq_RD(CORDIC_TypeDef *CORDICx)
+{
+ SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN);
+}
+
+/**
+ * @brief Disable CORDIC DMA read channel request.
+ * @rmtoll CSR DMAREN LL_CORDIC_DisableDMAReq_RD
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *CORDICx)
+{
+ CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN);
+}
+
+/**
+ * @brief Check CORDIC DMA read channel request state.
+ * @rmtoll CSR DMAREN LL_CORDIC_IsEnabledDMAReq_RD
+ * @param CORDICx CORDIC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(CORDIC_TypeDef *CORDICx)
+{
+ return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN) == (CORDIC_CSR_DMAREN)) ? 1U : 0U);
+}
+
+/**
+ * @brief Enable CORDIC DMA write channel request.
+ * @rmtoll CSR DMAWEN LL_CORDIC_EnableDMAReq_WR
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_EnableDMAReq_WR(CORDIC_TypeDef *CORDICx)
+{
+ SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN);
+}
+
+/**
+ * @brief Disable CORDIC DMA write channel request.
+ * @rmtoll CSR DMAWEN LL_CORDIC_DisableDMAReq_WR
+ * @param CORDICx CORDIC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *CORDICx)
+{
+ CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN);
+}
+
+/**
+ * @brief Check CORDIC DMA write channel request state.
+ * @rmtoll CSR DMAWEN LL_CORDIC_IsEnabledDMAReq_WR
+ * @param CORDICx CORDIC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx)
+{
+ return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U);
+}
+
+/**
+ * @brief Get the CORDIC data register address used for DMA transfer.
+ * @rmtoll RDATA RES LL_CORDIC_DMA_GetRegAddr\n
+ * @rmtoll WDATA ARG LL_CORDIC_DMA_GetRegAddr
+ * @param CORDICx CORDIC Instance
+ * @param Direction parameter can be one of the following values:
+ * @arg @ref LL_CORDIC_DMA_REG_DATA_IN
+ * @arg @ref LL_CORDIC_DMA_REG_DATA_OUT
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint32_t Direction)
+{
+ uint32_t data_reg_addr;
+
+ if (Direction == LL_CORDIC_DMA_REG_DATA_OUT)
+ {
+ /* return address of RDATA register */
+ data_reg_addr = (uint32_t) & (CORDICx->RDATA);
+ }
+ else
+ {
+ /* return address of WDATA register */
+ data_reg_addr = (uint32_t) & (CORDICx->WDATA);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check CORDIC result ready flag state.
+ * @rmtoll CSR RRDY LL_CORDIC_IsActiveFlag_RRDY
+ * @param CORDICx CORDIC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(CORDIC_TypeDef *CORDICx)
+{
+ return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_RRDY) == (CORDIC_CSR_RRDY)) ? 1U : 0U);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Write 32-bit input data for the CORDIC processing.
+ * @rmtoll WDATA ARG LL_CORDIC_WriteData
+ * @param CORDICx CORDIC Instance
+ * @param InData 0 .. 0xFFFFFFFF : 32-bit value to be provided as input data for CORDIC processing.
+ * @retval None
+ */
+__STATIC_INLINE void LL_CORDIC_WriteData(CORDIC_TypeDef *CORDICx, uint32_t InData)
+{
+ WRITE_REG(CORDICx->WDATA, InData);
+}
+
+/**
+ * @brief Return 32-bit output data of CORDIC processing.
+ * @rmtoll RDATA RES LL_CORDIC_ReadData
+ * @param CORDICx CORDIC Instance
+ * @retval 32-bit output data of CORDIC processing.
+ */
+__STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx)
+{
+ return (uint32_t)(READ_REG(CORDICx->RDATA));
+}
+
+/**
+ * @}
+ */
+
+
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CORDIC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_CORDIC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_dma.h b/Inc/stm32h7xx_ll_dma.h
index 095202d..5dae9e1 100644
--- a/Inc/stm32h7xx_ll_dma.h
+++ b/Inc/stm32h7xx_ll_dma.h
@@ -136,7 +136,7 @@
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
uint32_t PeriphRequest; /*!< Specifies the peripheral request.
- This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
+ This parameter can be a value of @ref DMAMUX1_Request_selection
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
@@ -475,7 +475,7 @@
*/
__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
}
@@ -497,7 +497,7 @@
*/
__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
}
@@ -519,7 +519,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
}
@@ -556,7 +556,7 @@
*/
__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
@@ -584,7 +584,7 @@
*/
__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
}
@@ -609,7 +609,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
}
@@ -636,7 +636,7 @@
*/
__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
}
@@ -662,7 +662,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
}
@@ -687,7 +687,7 @@
*/
__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
}
@@ -711,7 +711,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
}
@@ -736,7 +736,7 @@
*/
__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
}
@@ -760,7 +760,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
}
@@ -786,7 +786,7 @@
*/
__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
}
@@ -811,7 +811,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
}
@@ -837,7 +837,7 @@
*/
__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
}
@@ -862,7 +862,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
}
@@ -887,7 +887,7 @@
*/
__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
}
@@ -911,7 +911,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
}
@@ -938,7 +938,7 @@
*/
__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
}
@@ -964,7 +964,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
}
@@ -986,7 +986,7 @@
*/
__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
}
@@ -1008,7 +1008,7 @@
*/
__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
}
@@ -1033,7 +1033,7 @@
*/
__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
}
@@ -1057,7 +1057,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
}
@@ -1151,7 +1151,7 @@
* @arg @ref LL_DMAMUX1_REQ_USART6_TX
* @arg @ref LL_DMAMUX1_REQ_I2C3_RX
* @arg @ref LL_DMAMUX1_REQ_I2C3_TX
- * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+ * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
* @arg @ref LL_DMAMUX1_REQ_CRYP_IN
* @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
* @arg @ref LL_DMAMUX1_REQ_HASH_IN
@@ -1165,8 +1165,8 @@
* @arg @ref LL_DMAMUX1_REQ_SPI5_TX
* @arg @ref LL_DMAMUX1_REQ_SAI1_A
* @arg @ref LL_DMAMUX1_REQ_SAI1_B
- * @arg @ref LL_DMAMUX1_REQ_SAI2_A
- * @arg @ref LL_DMAMUX1_REQ_SAI2_B
+ * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
+ * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
* @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
* @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
* @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
@@ -1193,9 +1193,28 @@
* @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
* @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
* @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
- * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+ * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
* @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
- * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+ * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+ * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
+ * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
+ * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
+ * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
+ * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
+ * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
+ *
* @note (*) Availability depends on devices.
* @retval None
*/
@@ -1294,7 +1313,7 @@
* @arg @ref LL_DMAMUX1_REQ_USART6_TX
* @arg @ref LL_DMAMUX1_REQ_I2C3_RX
* @arg @ref LL_DMAMUX1_REQ_I2C3_TX
- * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+ * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
* @arg @ref LL_DMAMUX1_REQ_CRYP_IN
* @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
* @arg @ref LL_DMAMUX1_REQ_HASH_IN
@@ -1308,8 +1327,8 @@
* @arg @ref LL_DMAMUX1_REQ_SPI5_TX
* @arg @ref LL_DMAMUX1_REQ_SAI1_A
* @arg @ref LL_DMAMUX1_REQ_SAI1_B
- * @arg @ref LL_DMAMUX1_REQ_SAI2_A
- * @arg @ref LL_DMAMUX1_REQ_SAI2_B
+ * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
+ * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
* @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
* @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
* @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
@@ -1336,9 +1355,28 @@
* @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
* @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
* @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
- * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+ * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
* @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
- * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+ * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+ * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
+ * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
+ * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
+ * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
+ * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
+ * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
+ *
* @note (*) Availability depends on devices.
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream)
@@ -1368,7 +1406,7 @@
*/
__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
}
@@ -1394,7 +1432,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
}
@@ -1421,7 +1459,7 @@
*/
__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
}
@@ -1447,7 +1485,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
}
@@ -1472,7 +1510,7 @@
*/
__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
}
@@ -1496,7 +1534,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
}
@@ -1518,7 +1556,7 @@
*/
__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
}
@@ -1540,7 +1578,7 @@
*/
__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
}
@@ -1568,7 +1606,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
}
@@ -1590,7 +1628,7 @@
*/
__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
}
@@ -1612,7 +1650,7 @@
*/
__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
}
@@ -1639,7 +1677,7 @@
*/
__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
}
@@ -1665,7 +1703,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
}
@@ -1696,7 +1734,7 @@
*/
__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);
}
@@ -1726,7 +1764,7 @@
*/
__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
/* Direction Memory to Periph */
if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
@@ -1762,7 +1800,7 @@
*/
__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
}
@@ -1787,7 +1825,7 @@
*/
__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
}
@@ -1810,7 +1848,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
}
@@ -1833,7 +1871,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
}
@@ -1858,7 +1896,7 @@
*/
__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
}
@@ -1883,7 +1921,7 @@
*/
__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
}
@@ -1906,7 +1944,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
}
@@ -1929,7 +1967,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
}
@@ -1952,7 +1990,7 @@
*/
__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
}
@@ -1974,7 +2012,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR);
}
@@ -2892,7 +2930,7 @@
*/
__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
}
@@ -2914,7 +2952,7 @@
*/
__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
}
@@ -2936,7 +2974,7 @@
*/
__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
}
@@ -2958,7 +2996,7 @@
*/
__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
}
@@ -2980,7 +3018,7 @@
*/
__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
}
@@ -3002,7 +3040,7 @@
*/
__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
}
@@ -3024,7 +3062,7 @@
*/
__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
}
@@ -3046,7 +3084,7 @@
*/
__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
}
@@ -3068,7 +3106,7 @@
*/
__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
}
@@ -3090,7 +3128,7 @@
*/
__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
}
@@ -3112,7 +3150,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
}
@@ -3134,7 +3172,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
}
@@ -3156,7 +3194,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
}
@@ -3178,7 +3216,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
}
@@ -3200,7 +3238,7 @@
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
}
diff --git a/Inc/stm32h7xx_ll_dma2d.h b/Inc/stm32h7xx_ll_dma2d.h
index 68b687b..6bfc467 100644
--- a/Inc/stm32h7xx_ll_dma2d.h
+++ b/Inc/stm32h7xx_ll_dma2d.h
@@ -783,7 +783,6 @@
* @rmtoll OOR LO LL_DMA2D_GetLineOffset
* @param DMA2Dx DMA2D Instance
* @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
- @endif
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
{
diff --git a/Inc/stm32h7xx_ll_dmamux.h b/Inc/stm32h7xx_ll_dmamux.h
index f84f0e6..24cb555 100644
--- a/Inc/stm32h7xx_ll_dmamux.h
+++ b/Inc/stm32h7xx_ll_dmamux.h
@@ -141,8 +141,8 @@
* @}
*/
-/** @defgroup DMAMUX_Request_selection DMAMUX Request selection
- * @brief DMA Request selection
+/** @defgroup DMAMUX1_Request_selection DMAMUX1 Request selection
+ * @brief DMAMUX1 Request selection
* @{
*/
/* DMAMUX1 requests */
@@ -239,8 +239,10 @@
#define LL_DMAMUX1_REQ_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */
#define LL_DMAMUX1_REQ_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */
#define LL_DMAMUX1_REQ_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */
+#if defined(SAI2)
#define LL_DMAMUX1_REQ_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */
#define LL_DMAMUX1_REQ_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */
+#endif /* SAI2 */
#define LL_DMAMUX1_REQ_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */
#define LL_DMAMUX1_REQ_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */
#define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request */
@@ -280,7 +282,42 @@
#define LL_DMAMUX1_REQ_USART10_RX 118U /*!< DMAMUX1 USART10 RX request */
#define LL_DMAMUX1_REQ_USART10_TX 119U /*!< DMAMUX1 USART10 TX request */
#endif /* USART10 */
+#if defined(FMAC)
+#define LL_DMAMUX1_REQ_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */
+#define LL_DMAMUX1_REQ_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */
+#endif /* FMAC */
+#if defined(CORDIC)
+#define LL_DMAMUX1_REQ_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */
+#define LL_DMAMUX1_REQ_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */
+#endif /* CORDIC */
+#if defined(I2C5)
+#define LL_DMAMUX1_REQ_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */
+#define LL_DMAMUX1_REQ_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */
+#endif /* I2C5 */
+#if defined(TIM23)
+#define LL_DMAMUX1_REQ_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */
+#define LL_DMAMUX1_REQ_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */
+#define LL_DMAMUX1_REQ_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */
+#define LL_DMAMUX1_REQ_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */
+#define LL_DMAMUX1_REQ_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */
+#define LL_DMAMUX1_REQ_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */
+#endif /* TIM23 */
+#if defined(TIM24)
+#define LL_DMAMUX1_REQ_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */
+#define LL_DMAMUX1_REQ_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */
+#define LL_DMAMUX1_REQ_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */
+#define LL_DMAMUX1_REQ_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */
+#define LL_DMAMUX1_REQ_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */
+#define LL_DMAMUX1_REQ_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */
+#endif /* TIM24 */
+/**
+ * @}
+ */
+/** @defgroup DMAMUX2_Request_selection DMAMUX2 Request selection
+ * @brief DMAMUX2 Request selection
+ * @{
+ */
/* DMAMUX2 requests */
#define LL_DMAMUX2_REQ_MEM2MEM 0U /*!< memory to memory transfer */
#define LL_DMAMUX2_REQ_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */
@@ -603,7 +640,7 @@
* @arg @ref LL_DMAMUX1_REQ_USART6_TX
* @arg @ref LL_DMAMUX1_REQ_I2C3_RX
* @arg @ref LL_DMAMUX1_REQ_I2C3_TX
- * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+ * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
* @arg @ref LL_DMAMUX1_REQ_CRYP_IN
* @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
* @arg @ref LL_DMAMUX1_REQ_HASH_IN
@@ -617,8 +654,8 @@
* @arg @ref LL_DMAMUX1_REQ_SPI5_TX
* @arg @ref LL_DMAMUX1_REQ_SAI1_A
* @arg @ref LL_DMAMUX1_REQ_SAI1_B
- * @arg @ref LL_DMAMUX1_REQ_SAI2_A
- * @arg @ref LL_DMAMUX1_REQ_SAI2_B
+ * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
+ * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
* @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
* @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
* @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
@@ -648,6 +685,24 @@
* @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
* @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
* @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+ * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
+ * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
+ * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
+ * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
+ * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
+ * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
* @arg @ref LL_DMAMUX2_REQ_MEM2MEM
* @arg @ref LL_DMAMUX2_REQ_GENERATOR0
* @arg @ref LL_DMAMUX2_REQ_GENERATOR1
@@ -668,12 +723,13 @@
* @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
* @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
* @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
+ *
* @note (*) Availability depends on devices.
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
}
@@ -777,7 +833,7 @@
* @arg @ref LL_DMAMUX1_REQ_USART6_TX
* @arg @ref LL_DMAMUX1_REQ_I2C3_RX
* @arg @ref LL_DMAMUX1_REQ_I2C3_TX
- * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+ * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
* @arg @ref LL_DMAMUX1_REQ_CRYP_IN
* @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
* @arg @ref LL_DMAMUX1_REQ_HASH_IN
@@ -791,8 +847,8 @@
* @arg @ref LL_DMAMUX1_REQ_SPI5_TX
* @arg @ref LL_DMAMUX1_REQ_SAI1_A
* @arg @ref LL_DMAMUX1_REQ_SAI1_B
- * @arg @ref LL_DMAMUX1_REQ_SAI2_A
- * @arg @ref LL_DMAMUX1_REQ_SAI2_B
+ * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
+ * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
* @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
* @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
* @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
@@ -822,6 +878,24 @@
* @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
* @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
* @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+ * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
+ * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
+ * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
+ * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
+ * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
+ * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
+ * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
* @arg @ref LL_DMAMUX2_REQ_MEM2MEM
* @arg @ref LL_DMAMUX2_REQ_GENERATOR0
* @arg @ref LL_DMAMUX2_REQ_GENERATOR1
@@ -842,12 +916,13 @@
* @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
* @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
* @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
+ *
* @note (*) Availability depends on devices.
* @retval None
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
}
@@ -878,7 +953,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);
}
@@ -908,7 +983,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
}
@@ -943,7 +1018,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);
}
@@ -977,7 +1052,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));
}
@@ -1007,7 +1082,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
}
@@ -1037,7 +1112,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
}
@@ -1067,7 +1142,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
}
@@ -1097,7 +1172,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
}
@@ -1127,7 +1202,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
}
@@ -1157,7 +1232,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
}
@@ -1212,7 +1287,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
}
@@ -1266,7 +1341,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));
}
@@ -1288,7 +1363,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
}
@@ -1306,7 +1381,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
}
@@ -1328,7 +1403,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
}
@@ -1355,7 +1430,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
}
@@ -1381,7 +1456,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));
}
@@ -1405,7 +1480,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
}
@@ -1427,7 +1502,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
}
@@ -1489,7 +1564,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
}
@@ -1535,7 +1610,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));
}
@@ -1556,7 +1631,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
}
@@ -1569,7 +1644,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
}
@@ -1582,7 +1657,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
}
@@ -1595,7 +1670,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
}
@@ -1608,7 +1683,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
}
@@ -1621,7 +1696,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
}
@@ -1634,7 +1709,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
}
@@ -1647,7 +1722,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
}
@@ -1660,7 +1735,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
}
@@ -1673,7 +1748,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
}
@@ -1686,7 +1761,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
}
@@ -1699,7 +1774,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
}
@@ -1712,7 +1787,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
}
@@ -1725,7 +1800,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
}
@@ -1738,7 +1813,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
}
@@ -1751,7 +1826,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
}
@@ -1764,7 +1839,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
}
@@ -1777,7 +1852,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
}
@@ -1790,7 +1865,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
}
@@ -1803,7 +1878,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
}
@@ -1816,7 +1891,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);
}
@@ -1829,7 +1904,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);
}
@@ -1842,7 +1917,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);
}
@@ -1855,7 +1930,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);
}
@@ -1868,7 +1943,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);
}
@@ -1881,7 +1956,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);
}
@@ -1894,7 +1969,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);
}
@@ -1907,7 +1982,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);
}
@@ -1920,7 +1995,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);
}
@@ -1933,7 +2008,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);
}
@@ -1946,7 +2021,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);
}
@@ -1959,7 +2034,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);
}
@@ -1972,7 +2047,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);
}
@@ -1985,7 +2060,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);
}
@@ -1998,7 +2073,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);
}
@@ -2011,7 +2086,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);
}
@@ -2024,7 +2099,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);
}
@@ -2037,7 +2112,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);
}
@@ -2050,7 +2125,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);
}
@@ -2063,7 +2138,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);
}
@@ -2076,7 +2151,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);
}
@@ -2089,7 +2164,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);
}
@@ -2102,7 +2177,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);
}
@@ -2115,7 +2190,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);
}
@@ -2128,7 +2203,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);
}
@@ -2141,7 +2216,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);
}
@@ -2154,7 +2229,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);
}
@@ -2167,7 +2242,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);
}
@@ -2205,7 +2280,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
}
@@ -2235,7 +2310,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
}
@@ -2265,7 +2340,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));
}
@@ -2287,7 +2362,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
}
@@ -2309,7 +2384,7 @@
*/
__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
}
@@ -2331,7 +2406,7 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+ uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
}
diff --git a/Inc/stm32h7xx_ll_exti.h b/Inc/stm32h7xx_ll_exti.h
index be46b24..1e25e01 100644
--- a/Inc/stm32h7xx_ll_exti.h
+++ b/Inc/stm32h7xx_ll_exti.h
@@ -152,9 +152,13 @@
#define LL_EXTI_LINE_54 EXTI_IMR2_IM54 /*!< Extended line 54 */
#define LL_EXTI_LINE_55 EXTI_IMR2_IM55 /*!< Extended line 55 */
#define LL_EXTI_LINE_56 EXTI_IMR2_IM56 /*!< Extended line 56 */
+#if defined(EXTI_IMR2_IM57)
#define LL_EXTI_LINE_57 EXTI_IMR2_IM57 /*!< Extended line 57 */
+#endif /*EXTI_IMR2_IM57*/
#define LL_EXTI_LINE_58 EXTI_IMR2_IM58 /*!< Extended line 58 */
+#if defined(EXTI_IMR2_IM59)
#define LL_EXTI_LINE_59 EXTI_IMR2_IM59 /*!< Extended line 59 */
+#endif /*EXTI_IMR2_IM59*/
#define LL_EXTI_LINE_60 EXTI_IMR2_IM60 /*!< Extended line 60 */
#define LL_EXTI_LINE_61 EXTI_IMR2_IM61 /*!< Extended line 61 */
#define LL_EXTI_LINE_62 EXTI_IMR2_IM62 /*!< Extended line 62 */
@@ -192,8 +196,17 @@
#endif /* ETH */
#define LL_EXTI_LINE_87 EXTI_IMR3_IM87 /*!< Extended line 87 */
#if defined(DTS)
-#define LL_EXTI_LINE_88 EXTI_IMR3_IM88 /*!< Extended line 87 */
+#define LL_EXTI_LINE_88 EXTI_IMR3_IM88 /*!< Extended line 88 */
#endif /* DTS */
+#if defined(EXTI_IMR3_IM89)
+#define LL_EXTI_LINE_89 EXTI_IMR3_IM89 /*!< Extended line 89 */
+#endif /* EXTI_IMR3_IM89 */
+#if defined(EXTI_IMR3_IM90)
+#define LL_EXTI_LINE_90 EXTI_IMR3_IM90 /*!< Extended line 90 */
+#endif /* EXTI_IMR3_IM90 */
+#if defined(I2C5)
+#define LL_EXTI_LINE_91 EXTI_IMR3_IM91 /*!< Extended line 91 */
+#endif /* I2C5 */
#define LL_EXTI_LINE_ALL_64_95 EXTI_IMR3_IM /*!< All Extended line not reserved*/
@@ -371,8 +384,8 @@
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
- * @arg @ref LL_EXTI_LINE_44
- * @arg @ref LL_EXTI_LINE_46
+ * @arg @ref LL_EXTI_LINE_44 (*)
+ * @arg @ref LL_EXTI_LINE_46 (*)
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
@@ -383,14 +396,16 @@
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
- * @arg @ref LL_EXTI_LINE_57
+ * @arg @ref LL_EXTI_LINE_57 (*)
* @arg @ref LL_EXTI_LINE_58
- * @arg @ref LL_EXTI_LINE_59
+ * @arg @ref LL_EXTI_LINE_59 (*)
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
@@ -414,18 +429,25 @@
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
- * @arg @ref LL_EXTI_LINE_75
- * @arg @ref LL_EXTI_LINE_76
- * @arg @ref LL_EXTI_LINE_77
- * @arg @ref LL_EXTI_LINE_78
- * @arg @ref LL_EXTI_LINE_79
- * @arg @ref LL_EXTI_LINE_80
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_75 (*)
+ * @arg @ref LL_EXTI_LINE_76 (*)
+ * @arg @ref LL_EXTI_LINE_77 (**)
+ * @arg @ref LL_EXTI_LINE_78 (**)
+ * @arg @ref LL_EXTI_LINE_79 (**)
+ * @arg @ref LL_EXTI_LINE_80 (**)
+ * @arg @ref LL_EXTI_LINE_82 (**)
+ * @arg @ref LL_EXTI_LINE_84 (**)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (*)
* @arg @ref LL_EXTI_LINE_87
+ * @arg @ref LL_EXTI_LINE_88 (*)
+ * @arg @ref LL_EXTI_LINE_89 (*)
+ * @arg @ref LL_EXTI_LINE_90 (*)
+ * @arg @ref LL_EXTI_LINE_91 (*)
* @arg @ref LL_EXTI_LINE_ALL_64_95
+ *
+ * (*) value not defined in all devices.
+ * (**) value only defined in dual core devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine)
@@ -495,8 +517,8 @@
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
- * @arg @ref LL_EXTI_LINE_44
- * @arg @ref LL_EXTI_LINE_46
+ * @arg @ref LL_EXTI_LINE_44 (*)
+ * @arg @ref LL_EXTI_LINE_46 (*)
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
@@ -507,14 +529,16 @@
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
- * @arg @ref LL_EXTI_LINE_57
+ * @arg @ref LL_EXTI_LINE_57 (*)
* @arg @ref LL_EXTI_LINE_58
- * @arg @ref LL_EXTI_LINE_59
+ * @arg @ref LL_EXTI_LINE_59 (*)
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
@@ -537,18 +561,25 @@
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
- * @arg @ref LL_EXTI_LINE_75
- * @arg @ref LL_EXTI_LINE_76
- * @arg @ref LL_EXTI_LINE_77
- * @arg @ref LL_EXTI_LINE_78
- * @arg @ref LL_EXTI_LINE_79
- * @arg @ref LL_EXTI_LINE_80
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_75 (*)
+ * @arg @ref LL_EXTI_LINE_76 (*)
+ * @arg @ref LL_EXTI_LINE_77 (**)
+ * @arg @ref LL_EXTI_LINE_78 (**)
+ * @arg @ref LL_EXTI_LINE_79 (**)
+ * @arg @ref LL_EXTI_LINE_80 (**)
+ * @arg @ref LL_EXTI_LINE_82 (**)
+ * @arg @ref LL_EXTI_LINE_84 (**)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (*)
* @arg @ref LL_EXTI_LINE_87
+ * @arg @ref LL_EXTI_LINE_88 (*)
+ * @arg @ref LL_EXTI_LINE_89 (*)
+ * @arg @ref LL_EXTI_LINE_90 (*)
+ * @arg @ref LL_EXTI_LINE_91 (*)
* @arg @ref LL_EXTI_LINE_ALL_64_95
+ *
+ * (*) value not defined in all devices.
+ * (**) value only defined in dual core devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine)
@@ -618,8 +649,8 @@
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
- * @arg @ref LL_EXTI_LINE_44
- * @arg @ref LL_EXTI_LINE_46
+ * @arg @ref LL_EXTI_LINE_44 (*)
+ * @arg @ref LL_EXTI_LINE_46 (*)
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
@@ -630,14 +661,16 @@
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
- * @arg @ref LL_EXTI_LINE_57
+ * @arg @ref LL_EXTI_LINE_57 (*)
* @arg @ref LL_EXTI_LINE_58
- * @arg @ref LL_EXTI_LINE_59
+ * @arg @ref LL_EXTI_LINE_59 (*)
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
+ *
+ * (*) value not defined in all devices.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
@@ -661,18 +694,25 @@
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
- * @arg @ref LL_EXTI_LINE_75
- * @arg @ref LL_EXTI_LINE_76
- * @arg @ref LL_EXTI_LINE_77
- * @arg @ref LL_EXTI_LINE_78
- * @arg @ref LL_EXTI_LINE_79
- * @arg @ref LL_EXTI_LINE_80
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_75 (*)
+ * @arg @ref LL_EXTI_LINE_76 (*)
+ * @arg @ref LL_EXTI_LINE_77 (**)
+ * @arg @ref LL_EXTI_LINE_78 (**)
+ * @arg @ref LL_EXTI_LINE_79 (**)
+ * @arg @ref LL_EXTI_LINE_80 (**)
+ * @arg @ref LL_EXTI_LINE_82 (**)
+ * @arg @ref LL_EXTI_LINE_84 (**)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (*)
* @arg @ref LL_EXTI_LINE_87
+ * @arg @ref LL_EXTI_LINE_88 (*)
+ * @arg @ref LL_EXTI_LINE_89 (*)
+ * @arg @ref LL_EXTI_LINE_90 (*)
+ * @arg @ref LL_EXTI_LINE_91 (*)
* @arg @ref LL_EXTI_LINE_ALL_64_95
+ *
+ * (*) value not defined in all devices.
+ * (**) value only defined in dual core devices.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
@@ -1124,8 +1164,8 @@
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
- * @arg @ref LL_EXTI_LINE_44
- * @arg @ref LL_EXTI_LINE_46
+ * @arg @ref LL_EXTI_LINE_44 (*)
+ * @arg @ref LL_EXTI_LINE_46 (*)
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
@@ -1136,14 +1176,16 @@
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
- * @arg @ref LL_EXTI_LINE_57
+ * @arg @ref LL_EXTI_LINE_57 (*)
* @arg @ref LL_EXTI_LINE_58
- * @arg @ref LL_EXTI_LINE_59
+ * @arg @ref LL_EXTI_LINE_59 (*)
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
@@ -1166,18 +1208,25 @@
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
- * @arg @ref LL_EXTI_LINE_75
- * @arg @ref LL_EXTI_LINE_76
- * @arg @ref LL_EXTI_LINE_77
- * @arg @ref LL_EXTI_LINE_78
- * @arg @ref LL_EXTI_LINE_79
- * @arg @ref LL_EXTI_LINE_80
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_75 (*)
+ * @arg @ref LL_EXTI_LINE_76 (*)
+ * @arg @ref LL_EXTI_LINE_77 (**)
+ * @arg @ref LL_EXTI_LINE_78 (**)
+ * @arg @ref LL_EXTI_LINE_79 (**)
+ * @arg @ref LL_EXTI_LINE_80 (**)
+ * @arg @ref LL_EXTI_LINE_82 (**)
+ * @arg @ref LL_EXTI_LINE_84 (**)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (*)
* @arg @ref LL_EXTI_LINE_87
+ * @arg @ref LL_EXTI_LINE_88 (*)
+ * @arg @ref LL_EXTI_LINE_89 (*)
+ * @arg @ref LL_EXTI_LINE_90 (*)
+ * @arg @ref LL_EXTI_LINE_91 (*)
* @arg @ref LL_EXTI_LINE_ALL_64_95
+ *
+ * (*) value not defined in all devices.
+ * (**) value only defined in dual core devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
@@ -1245,8 +1294,8 @@
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
- * @arg @ref LL_EXTI_LINE_44
- * @arg @ref LL_EXTI_LINE_46
+ * @arg @ref LL_EXTI_LINE_44 (*)
+ * @arg @ref LL_EXTI_LINE_46 (*)
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
@@ -1257,14 +1306,16 @@
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
- * @arg @ref LL_EXTI_LINE_57
+ * @arg @ref LL_EXTI_LINE_57 (*)
* @arg @ref LL_EXTI_LINE_58
- * @arg @ref LL_EXTI_LINE_59
+ * @arg @ref LL_EXTI_LINE_59 (*)
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
@@ -1287,18 +1338,25 @@
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
- * @arg @ref LL_EXTI_LINE_75
- * @arg @ref LL_EXTI_LINE_76
- * @arg @ref LL_EXTI_LINE_77
- * @arg @ref LL_EXTI_LINE_78
- * @arg @ref LL_EXTI_LINE_79
- * @arg @ref LL_EXTI_LINE_80
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_75 (*)
+ * @arg @ref LL_EXTI_LINE_76 (*)
+ * @arg @ref LL_EXTI_LINE_77 (**)
+ * @arg @ref LL_EXTI_LINE_78 (**)
+ * @arg @ref LL_EXTI_LINE_79 (**)
+ * @arg @ref LL_EXTI_LINE_80 (**)
+ * @arg @ref LL_EXTI_LINE_82 (**)
+ * @arg @ref LL_EXTI_LINE_84 (**)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (*)
* @arg @ref LL_EXTI_LINE_87
+ * @arg @ref LL_EXTI_LINE_88 (*)
+ * @arg @ref LL_EXTI_LINE_89 (*)
+ * @arg @ref LL_EXTI_LINE_90 (*)
+ * @arg @ref LL_EXTI_LINE_91 (*)
* @arg @ref LL_EXTI_LINE_ALL_64_95
+ *
+ * (*) value not defined in all devices.
+ * (**) value only defined in dual core devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
@@ -1367,8 +1425,8 @@
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
- * @arg @ref LL_EXTI_LINE_44
- * @arg @ref LL_EXTI_LINE_46
+ * @arg @ref LL_EXTI_LINE_44 (*)
+ * @arg @ref LL_EXTI_LINE_46 (*)
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
@@ -1379,14 +1437,16 @@
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
- * @arg @ref LL_EXTI_LINE_57
+ * @arg @ref LL_EXTI_LINE_57 (*)
* @arg @ref LL_EXTI_LINE_58
- * @arg @ref LL_EXTI_LINE_59
+ * @arg @ref LL_EXTI_LINE_59 (*)
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
+ *
+ * (*) value not defined in all devices.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
@@ -1409,18 +1469,25 @@
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
- * @arg @ref LL_EXTI_LINE_75
- * @arg @ref LL_EXTI_LINE_76
- * @arg @ref LL_EXTI_LINE_77
- * @arg @ref LL_EXTI_LINE_78
- * @arg @ref LL_EXTI_LINE_79
- * @arg @ref LL_EXTI_LINE_80
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_75 (*)
+ * @arg @ref LL_EXTI_LINE_76 (*)
+ * @arg @ref LL_EXTI_LINE_77 (**)
+ * @arg @ref LL_EXTI_LINE_78 (**)
+ * @arg @ref LL_EXTI_LINE_79 (**)
+ * @arg @ref LL_EXTI_LINE_80 (**)
+ * @arg @ref LL_EXTI_LINE_82 (**)
+ * @arg @ref LL_EXTI_LINE_84 (**)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (*)
* @arg @ref LL_EXTI_LINE_87
+ * @arg @ref LL_EXTI_LINE_88 (*)
+ * @arg @ref LL_EXTI_LINE_89 (*)
+ * @arg @ref LL_EXTI_LINE_90 (*)
+ * @arg @ref LL_EXTI_LINE_91 (*)
* @arg @ref LL_EXTI_LINE_ALL_64_95
+ *
+ * (*) value not defined in all devices.
+ * (**) value only defined in dual core devices.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
@@ -1882,10 +1949,13 @@
* condition.
* @rmtoll RTSR3 RTx LL_EXTI_EnableRisingTrig_64_95
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_82 (*)
+ * @arg @ref LL_EXTI_LINE_84 (*)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (**)
+ *
+ * (*) value only defined in dual core devices.
+ * (**) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine)
@@ -1965,10 +2035,13 @@
* condition.
* @rmtoll RTSR3 RTx LL_EXTI_DisableRisingTrig_64_95
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_82 (*)
+ * @arg @ref LL_EXTI_LINE_84 (*)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (**)
+ *
+ * (*) value only defined in dual core devices.
+ * (**) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine)
@@ -2027,10 +2100,13 @@
* @brief Check if rising edge trigger is enabled for Lines in range 64 to 95
* @rmtoll RTSR3 RTx LL_EXTI_IsEnabledRisingTrig_64_95
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_82 (*)
+ * @arg @ref LL_EXTI_LINE_84 (*)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (**)
+ *
+ * (*) value only defined in dual core devices.
+ * (**) value not defined in all devices.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine)
@@ -2117,10 +2193,13 @@
* condition.
* @rmtoll FTSR3 FTx LL_EXTI_EnableFallingTrig_64_95
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_82 (*)
+ * @arg @ref LL_EXTI_LINE_84 (*)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (**)
+ *
+ * (*) value only defined in dual core devices.
+ * (**) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine)
@@ -2197,10 +2276,13 @@
* In this case, both generate a trigger condition.
* @rmtoll FTSR3 FTx LL_EXTI_DisableFallingTrig_64_95
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_82 (*)
+ * @arg @ref LL_EXTI_LINE_84 (*)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (**)
+ *
+ * (*) value only defined in dual core devices.
+ * (**) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine)
@@ -2259,10 +2341,13 @@
* @brief Check if falling edge trigger is enabled for Lines in range 64 to 95
* @rmtoll FTSR3 FTx LL_EXTI_IsEnabledFallingTrig_64_95
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_82 (*)
+ * @arg @ref LL_EXTI_LINE_84 (*)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (**)
+ *
+ * (*) value only defined in dual core devices.
+ * (**) value not defined in all devices.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine)
@@ -2344,10 +2429,13 @@
* register (by writing a 1 into the bit)
* @rmtoll SWIER3 SWIx LL_EXTI_GenerateSWI_64_95
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_82 (*)
+ * @arg @ref LL_EXTI_LINE_84 (*)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (**)
+ *
+ * (*) value only defined in dual core devices.
+ * (**) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine)
@@ -2422,11 +2510,13 @@
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR3 PIFx LL_EXTI_IsActiveFlag_64_95
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_82 (*)
+ * @arg @ref LL_EXTI_LINE_84 (*)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
- * @arg @ref LL_EXTI_LINE_ALL_64_95
+ * @arg @ref LL_EXTI_LINE_86 (**)
+ *
+ * (*) value only defined in dual core devices.
+ * (**) value not defined in all devices.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
@@ -2493,10 +2583,13 @@
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR3 PIFx LL_EXTI_ReadFlag_64_95
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_82 (*)
+ * @arg @ref LL_EXTI_LINE_84 (*)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (**)
+ *
+ * (*) value only defined in dual core devices.
+ * (**) value not defined in all devices.
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
@@ -2560,10 +2653,13 @@
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR3 PIFx LL_EXTI_ClearFlag_64_95
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_82
- * @arg @ref LL_EXTI_LINE_84
+ * @arg @ref LL_EXTI_LINE_82 (*)
+ * @arg @ref LL_EXTI_LINE_84 (*)
* @arg @ref LL_EXTI_LINE_85
- * @arg @ref LL_EXTI_LINE_86
+ * @arg @ref LL_EXTI_LINE_86 (**)
+ *
+ * (*) value only defined in dual core devices.
+ * (**) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
@@ -2955,8 +3051,12 @@
* @param ClrSrc This parameter can be one of the following values:
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_0_15(uint32_t ExtiLine, uint32_t ClrSrc)
@@ -2975,8 +3075,12 @@
* @param ClrSrc This parameter can be one of the following values:
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_16_31(uint32_t ExtiLine, uint32_t ClrSrc)
@@ -2995,8 +3099,12 @@
* @param ClrSrc This parameter can be one of the following values:
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_32_47(uint32_t ExtiLine, uint32_t ClrSrc)
@@ -3017,8 +3125,12 @@
* @param ClrSrc This parameter can be one of the following values:
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+ *
+ * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_48_63(uint32_t ExtiLine, uint32_t ClrSrc)
@@ -3049,8 +3161,12 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+ *
+ * (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_0_15(uint32_t ExtiLine)
{
@@ -3068,8 +3184,12 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+ *
+ * (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_16_31(uint32_t ExtiLine)
{
@@ -3086,8 +3206,12 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+ *
+ * (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_32_47(uint32_t ExtiLine)
{
@@ -3107,8 +3231,12 @@
* @retval Returned value can be one of the following values:
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
* @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
- * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*)
+ * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*)
+ *
+ * (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_48_63(uint32_t ExtiLine)
{
diff --git a/Inc/stm32h7xx_ll_fmac.h b/Inc/stm32h7xx_ll_fmac.h
new file mode 100644
index 0000000..4bc018c
--- /dev/null
+++ b/Inc/stm32h7xx_ll_fmac.h
@@ -0,0 +1,1049 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_ll_fmac.h
+ * @author MCD Application Team
+ * @brief Header file of FMAC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_FMAC_H
+#define STM32H7xx_LL_FMAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+ * @{
+ */
+
+#if defined(FMAC)
+
+/** @defgroup FMAC_LL FMAC
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMAC_LL_Private_Macros FMAC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants
+ * @{
+ */
+
+/** @defgroup FMAC_LL_EC_GET_FLAG Get Flag Defines
+ * @brief Flag defines which can be used with LL_FMAC_ReadReg function
+ * @{
+ */
+#define LL_FMAC_SR_SAT FMAC_SR_SAT
+#define LL_FMAC_SR_UNFL FMAC_SR_UNFL
+#define LL_FMAC_SR_OVFL FMAC_SR_OVFL
+#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL
+#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions
+ * @{
+ */
+#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN
+#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN
+#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN
+#define LL_FMAC_CR_WIEN FMAC_CR_WIEN
+#define LL_FMAC_CR_RIEN FMAC_CR_RIEN
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EC_WM FMAC watermarks
+ * @brief Watermark defines that can be used for buffer full (input) or buffer empty (output)
+ * @{
+ */
+#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000UL /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */
+#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000UL /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */
+#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000UL /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */
+#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000UL /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EC_FUNC FMAC functions
+ * @{
+ */
+#define LL_FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */
+#define LL_FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */
+#define LL_FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */
+#define LL_FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */
+#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FMAC_LL_Exported_Macros FMAC Exported Macros
+ * @{
+ */
+
+/** @defgroup FMAC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in FMAC register
+ * @param __INSTANCE__ FMAC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_FMAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in FMAC register
+ * @param __INSTANCE__ FMAC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_FMAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions
+ * @{
+ */
+
+/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Configure X1 full watermark.
+ * @rmtoll X1BUFCFG FULL_WM LL_FMAC_SetX1FullWatermark
+ * @param FMACx FMAC instance
+ * @param Watermark This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetX1FullWatermark(FMAC_TypeDef *FMACx, uint32_t Watermark)
+{
+ MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM, Watermark);
+}
+
+/**
+ * @brief Return X1 full watermark.
+ * @rmtoll X1BUFCFG FULL_WM LL_FMAC_GetX1FullWatermark
+ * @param FMACx FMAC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ */
+__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx)
+{
+ return (uint32_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM));
+}
+
+/**
+ * @brief Configure X1 buffer size.
+ * @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_SetX1BufferSize
+ * @param FMACx FMAC instance
+ * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Return X1 buffer size.
+ * @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_GetX1BufferSize
+ * @param FMACx FMAC instance
+ * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE) >> FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Configure X1 base.
+ * @rmtoll X1BUFCFG X1_BASE LL_FMAC_SetX1Base
+ * @param FMACx FMAC instance
+ * @param Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base)
+{
+ MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE, ((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos);
+}
+
+/**
+ * @brief Return X1 base.
+ * @rmtoll X1BUFCFG X1_BASE LL_FMAC_GetX1Base
+ * @param FMACx FMAC instance
+ * @retval 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE) >> FMAC_X1BUFCFG_X1_BASE_Pos);
+}
+
+/**
+ * @brief Configure X2 buffer size.
+ * @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_SetX2BufferSize
+ * @param FMACx FMAC instance
+ * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Return X2 buffer size.
+ * @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_GetX2BufferSize
+ * @param FMACx FMAC instance
+ * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE) >> FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Configure X2 base.
+ * @rmtoll X2BUFCFG X2_BASE LL_FMAC_SetX2Base
+ * @param FMACx FMAC instance
+ * @param Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base)
+{
+ MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE, ((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos);
+}
+
+/**
+ * @brief Return X2 base.
+ * @rmtoll X2BUFCFG X2_BASE LL_FMAC_GetX2Base
+ * @param FMACx FMAC instance
+ * @retval 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE) >> FMAC_X2BUFCFG_X2_BASE_Pos);
+}
+
+/**
+ * @brief Configure Y empty watermark.
+ * @rmtoll YBUFCFG EMPTY_WM LL_FMAC_SetYEmptyWatermark
+ * @param FMACx FMAC instance
+ * @param Watermark This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetYEmptyWatermark(FMAC_TypeDef *FMACx, uint32_t Watermark)
+{
+ MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM, Watermark);
+}
+
+/**
+ * @brief Return Y empty watermark.
+ * @rmtoll YBUFCFG EMPTY_WM LL_FMAC_GetYEmptyWatermark
+ * @param FMACx FMAC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ */
+__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx)
+{
+ return (uint32_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM));
+}
+
+/**
+ * @brief Configure Y buffer size.
+ * @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_SetYBufferSize
+ * @param FMACx FMAC instance
+ * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Return Y buffer size.
+ * @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_GetYBufferSize
+ * @param FMACx FMAC instance
+ * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE) >> FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
+}
+
+/**
+ * @brief Configure Y base.
+ * @rmtoll YBUFCFG Y_BASE LL_FMAC_SetYBase
+ * @param FMACx FMAC instance
+ * @param Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base)
+{
+ MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE, ((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos);
+}
+
+/**
+ * @brief Return Y base.
+ * @rmtoll YBUFCFG Y_BASE LL_FMAC_GetYBase
+ * @param FMACx FMAC instance
+ * @retval 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE) >> FMAC_YBUFCFG_Y_BASE_Pos);
+}
+
+/**
+ * @brief Start FMAC processing.
+ * @rmtoll PARAM START LL_FMAC_EnableStart
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableStart(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->PARAM, FMAC_PARAM_START);
+}
+
+/**
+ * @brief Stop FMAC processing.
+ * @rmtoll PARAM START LL_FMAC_DisableStart
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableStart(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->PARAM, FMAC_PARAM_START);
+}
+
+/**
+ * @brief Check the state of FMAC processing.
+ * @rmtoll PARAM START LL_FMAC_IsEnabledStart
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure function.
+ * @rmtoll PARAM FUNC LL_FMAC_SetFunction
+ * @param FMACx FMAC instance
+ * @param Function This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_FUNC_LOAD_X1
+ * @arg @ref LL_FMAC_FUNC_LOAD_X2
+ * @arg @ref LL_FMAC_FUNC_LOAD_Y
+ * @arg @ref LL_FMAC_FUNC_CONVO_FIR
+ * @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetFunction(FMAC_TypeDef *FMACx, uint32_t Function)
+{
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_FUNC, Function);
+}
+
+/**
+ * @brief Return function.
+ * @rmtoll PARAM FUNC LL_FMAC_GetFunction
+ * @param FMACx FMAC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMAC_FUNC_LOAD_X1
+ * @arg @ref LL_FMAC_FUNC_LOAD_X2
+ * @arg @ref LL_FMAC_FUNC_LOAD_Y
+ * @arg @ref LL_FMAC_FUNC_CONVO_FIR
+ * @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
+ */
+__STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx)
+{
+ return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC));
+}
+
+/**
+ * @brief Configure input parameter R.
+ * @rmtoll PARAM R LL_FMAC_SetParamR
+ * @param FMACx FMAC instance
+ * @param Param 0x00 .. 0xFF: Parameter R (gain, etc.).
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param)
+{
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_R, ((uint32_t)Param) << FMAC_PARAM_R_Pos);
+}
+
+/**
+ * @brief Return input parameter R.
+ * @rmtoll PARAM R LL_FMAC_GetParamR
+ * @param FMACx FMAC instance
+ * @retval 0x00 .. 0xFF: Parameter R (gain, etc.).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos);
+}
+
+/**
+ * @brief Configure input parameter Q.
+ * @rmtoll PARAM Q LL_FMAC_SetParamQ
+ * @param FMACx FMAC instance
+ * @param Param 0x00 .. 0xFF: Parameter Q (vector length, etc.).
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param)
+{
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_Q, ((uint32_t)Param) << FMAC_PARAM_Q_Pos);
+}
+
+/**
+ * @brief Return input parameter Q.
+ * @rmtoll PARAM Q LL_FMAC_GetParamQ
+ * @param FMACx FMAC instance
+ * @retval 0x00 .. 0xFF: Parameter Q (vector length, etc.).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos);
+}
+
+/**
+ * @brief Configure input parameter P.
+ * @rmtoll PARAM P LL_FMAC_SetParamP
+ * @param FMACx FMAC instance
+ * @param Param 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param)
+{
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param) << FMAC_PARAM_P_Pos);
+}
+
+/**
+ * @brief Return input parameter P.
+ * @rmtoll PARAM P LL_FMAC_GetParamP
+ * @param FMACx FMAC instance
+ * @retval 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
+ */
+__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx)
+{
+ return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P) >> FMAC_PARAM_P_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_Reset_Management Reset_Management
+ * @{
+ */
+
+/**
+ * @brief Start the FMAC reset.
+ * @rmtoll CR RESET LL_FMAC_EnableReset
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableReset(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_RESET);
+}
+
+/**
+ * @brief Interrupt the FMAC reset.
+ * @rmtoll CR RESET LL_FMAC_DisableReset
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableReset(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_RESET);
+}
+
+/**
+ * @brief Check the state of the FMAC reset.
+ * @rmtoll CR RESET LL_FMAC_IsEnabledReset
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_RESET) == (FMAC_CR_RESET)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Enable Clipping.
+ * @rmtoll CR CLIPEN LL_FMAC_EnableClipping
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableClipping(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_CLIPEN);
+}
+
+/**
+ * @brief Disable Clipping.
+ * @rmtoll CR CLIPEN LL_FMAC_DisableClipping
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableClipping(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_CLIPEN);
+}
+
+/**
+ * @brief Check Clipping State.
+ * @rmtoll CR CLIPEN LL_FMAC_IsEnabledClipping
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_CLIPEN) == (FMAC_CR_CLIPEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable FMAC DMA write channel request.
+ * @rmtoll CR DMAWEN LL_FMAC_EnableDMAReq_WRITE
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableDMAReq_WRITE(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_DMAWEN);
+}
+
+/**
+ * @brief Disable FMAC DMA write channel request.
+ * @rmtoll CR DMAWEN LL_FMAC_DisableDMAReq_WRITE
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_DMAWEN);
+}
+
+/**
+ * @brief Check FMAC DMA write channel request state.
+ * @rmtoll CR DMAWEN LL_FMAC_IsEnabledDMAReq_WRITE
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_DMAWEN) == (FMAC_CR_DMAWEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable FMAC DMA read channel request.
+ * @rmtoll CR DMAREN LL_FMAC_EnableDMAReq_READ
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableDMAReq_READ(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_DMAREN);
+}
+
+/**
+ * @brief Disable FMAC DMA read channel request.
+ * @rmtoll CR DMAREN LL_FMAC_DisableDMAReq_READ
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableDMAReq_READ(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_DMAREN);
+}
+
+/**
+ * @brief Check FMAC DMA read channel request state.
+ * @rmtoll CR DMAREN LL_FMAC_IsEnabledDMAReq_READ
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_DMAREN) == (FMAC_CR_DMAREN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable FMAC saturation error interrupt.
+ * @rmtoll CR SATIEN LL_FMAC_EnableIT_SAT
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableIT_SAT(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_SATIEN);
+}
+
+/**
+ * @brief Disable FMAC saturation error interrupt.
+ * @rmtoll CR SATIEN LL_FMAC_DisableIT_SAT
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableIT_SAT(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_SATIEN);
+}
+
+/**
+ * @brief Check FMAC saturation error interrupt state.
+ * @rmtoll CR SATIEN LL_FMAC_IsEnabledIT_SAT
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_SATIEN) == (FMAC_CR_SATIEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable FMAC underflow error interrupt.
+ * @rmtoll CR UNFLIEN LL_FMAC_EnableIT_UNFL
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableIT_UNFL(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_UNFLIEN);
+}
+
+/**
+ * @brief Disable FMAC underflow error interrupt.
+ * @rmtoll CR UNFLIEN LL_FMAC_DisableIT_UNFL
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableIT_UNFL(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_UNFLIEN);
+}
+
+/**
+ * @brief Check FMAC underflow error interrupt state.
+ * @rmtoll CR UNFLIEN LL_FMAC_IsEnabledIT_UNFL
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_UNFLIEN) == (FMAC_CR_UNFLIEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable FMAC overflow error interrupt.
+ * @rmtoll CR OVFLIEN LL_FMAC_EnableIT_OVFL
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableIT_OVFL(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_OVFLIEN);
+}
+
+/**
+ * @brief Disable FMAC overflow error interrupt.
+ * @rmtoll CR OVFLIEN LL_FMAC_DisableIT_OVFL
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableIT_OVFL(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_OVFLIEN);
+}
+
+/**
+ * @brief Check FMAC overflow error interrupt state.
+ * @rmtoll CR OVFLIEN LL_FMAC_IsEnabledIT_OVFL
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_OVFLIEN) == (FMAC_CR_OVFLIEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable FMAC write interrupt.
+ * @rmtoll CR WIEN LL_FMAC_EnableIT_WR
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableIT_WR(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_WIEN);
+}
+
+/**
+ * @brief Disable FMAC write interrupt.
+ * @rmtoll CR WIEN LL_FMAC_DisableIT_WR
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableIT_WR(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_WIEN);
+}
+
+/**
+ * @brief Check FMAC write interrupt state.
+ * @rmtoll CR WIEN LL_FMAC_IsEnabledIT_WR
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_WIEN) == (FMAC_CR_WIEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable FMAC read interrupt.
+ * @rmtoll CR RIEN LL_FMAC_EnableIT_RD
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_EnableIT_RD(FMAC_TypeDef *FMACx)
+{
+ SET_BIT(FMACx->CR, FMAC_CR_RIEN);
+}
+
+/**
+ * @brief Disable FMAC read interrupt.
+ * @rmtoll CR RIEN LL_FMAC_DisableIT_RD
+ * @param FMACx FMAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_DisableIT_RD(FMAC_TypeDef *FMACx)
+{
+ CLEAR_BIT(FMACx->CR, FMAC_CR_RIEN);
+}
+
+/**
+ * @brief Check FMAC read interrupt state.
+ * @rmtoll CR RIEN LL_FMAC_IsEnabledIT_RD
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->CR, FMAC_CR_RIEN) == (FMAC_CR_RIEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check FMAC saturation error flag state.
+ * @rmtoll SR SAT LL_FMAC_IsActiveFlag_SAT
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->SR, FMAC_SR_SAT) == (FMAC_SR_SAT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check FMAC underflow error flag state.
+ * @rmtoll SR UNFL LL_FMAC_IsActiveFlag_UNFL
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->SR, FMAC_SR_UNFL) == (FMAC_SR_UNFL)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check FMAC overflow error flag state.
+ * @rmtoll SR OVFL LL_FMAC_IsActiveFlag_OVFL
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->SR, FMAC_SR_OVFL) == (FMAC_SR_OVFL)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check FMAC X1 buffer full flag state.
+ * @rmtoll SR X1FULL LL_FMAC_IsActiveFlag_X1FULL
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->SR, FMAC_SR_X1FULL) == (FMAC_SR_X1FULL)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Check FMAC Y buffer empty flag state.
+ * @rmtoll SR YEMPTY LL_FMAC_IsActiveFlag_YEMPTY
+ * @param FMACx FMAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx)
+{
+ return ((READ_BIT(FMACx->SR, FMAC_SR_YEMPTY) == (FMAC_SR_YEMPTY)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Write 16-bit input data for the FMAC processing.
+ * @rmtoll WDATA WDATA LL_FMAC_WriteData
+ * @param FMACx FMAC instance
+ * @param InData 0x0000 .. 0xFFFF: 16-bit value to be provided as input data for FMAC processing.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData)
+{
+ WRITE_REG(FMACx->WDATA, InData);
+}
+
+/**
+ * @brief Return 16-bit output data of FMAC processing.
+ * @rmtoll RDATA RDATA LL_FMAC_ReadData
+ * @param FMACx FMAC instance
+ * @retval 0x0000 .. 0xFFFF: 16-bit output data of FMAC processing.
+ */
+__STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx)
+{
+ return (uint16_t)(READ_REG(FMACx->RDATA));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Configure memory for X1 buffer.
+ * @rmtoll X1BUFCFG FULL_WM LL_FMAC_ConfigX1\n
+ * X1BUFCFG X1_BASE LL_FMAC_ConfigX1\n
+ * X1BUFCFG X1_BUF_SIZE LL_FMAC_ConfigX1
+ * @param FMACx FMAC instance
+ * @param Watermark This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ * @param Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
+ * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM | FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE,
+ Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos));
+}
+
+/**
+ * @brief Configure memory for X2 buffer.
+ * @rmtoll X2BUFCFG X2_BASE LL_FMAC_ConfigX2\n
+ * X2BUFCFG X2_BUF_SIZE LL_FMAC_ConfigX2
+ * @param FMACx FMAC instance
+ * @param Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
+ * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE,
+ (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos));
+}
+
+/**
+ * @brief Configure memory for Y buffer.
+ * @rmtoll YBUFCFG EMPTY_WM LL_FMAC_ConfigY\n
+ * YBUFCFG Y_BASE LL_FMAC_ConfigY\n
+ * YBUFCFG Y_BUF_SIZE LL_FMAC_ConfigY
+ * @param FMACx FMAC instance
+ * @param Watermark This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_WM_0_THRESHOLD_1
+ * @arg @ref LL_FMAC_WM_1_THRESHOLD_2
+ * @arg @ref LL_FMAC_WM_2_THRESHOLD_4
+ * @arg @ref LL_FMAC_WM_3_THRESHOLD_8
+ * @param Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
+ * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
+{
+ MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM | FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE,
+ Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos));
+}
+
+/**
+ * @brief Configure the FMAC processing.
+ * @rmtoll PARAM START LL_FMAC_ConfigFunc\n
+ * PARAM FUNC LL_FMAC_ConfigFunc\n
+ * PARAM P LL_FMAC_ConfigFunc\n
+ * PARAM Q LL_FMAC_ConfigFunc\n
+ * PARAM R LL_FMAC_ConfigFunc
+ * @param FMACx FMAC instance
+ * @param Start 0x00 .. 0x01: Enable or disable FMAC processing.
+ * @param Function This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_FUNC_LOAD_X1
+ * @arg @ref LL_FMAC_FUNC_LOAD_X2
+ * @arg @ref LL_FMAC_FUNC_LOAD_Y
+ * @arg @ref LL_FMAC_FUNC_CONVO_FIR
+ * @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
+ * @param ParamP 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
+ * @param ParamQ 0x00 .. 0xFF: Parameter Q (vector length, etc.).
+ * @param ParamR 0x00 .. 0xFF: Parameter R (gain, etc.).
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP,
+ uint8_t ParamQ, uint8_t ParamR)
+{
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_START | FMAC_PARAM_FUNC | FMAC_PARAM_P | FMAC_PARAM_Q | FMAC_PARAM_R,
+ (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) | (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos));
+}
+
+/**
+ * @}
+ */
+
+
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx);
+ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(FMAC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_FMAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_hrtim.h b/Inc/stm32h7xx_ll_hrtim.h
index a16dd28..69d00fc 100644
--- a/Inc/stm32h7xx_ll_hrtim.h
+++ b/Inc/stm32h7xx_ll_hrtim.h
@@ -1971,8 +1971,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
{
- register uint32_t shift = ((3U * ADCTrig) & 0x1FU);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+ uint32_t shift = ((3U * ADCTrig) & 0x1FU);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
REG_OFFSET_TAB_ADCxR[ADCTrig]));
MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
WRITE_REG(*pReg, Src);
@@ -2004,7 +2004,7 @@
*/
__STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
{
- register uint32_t shift = ((3U * ADCTrig) & 0x1FU);
+ uint32_t shift = ((3U * ADCTrig) & 0x1FU);
MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
}
@@ -2030,7 +2030,7 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
{
- register const uint32_t shift = ((3U * ADCTrig) & 0x1FU);
+ const uint32_t shift = ((3U * ADCTrig) & 0x1FU);
return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift);
}
@@ -2247,7 +2247,7 @@
*/
__STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
{
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
REG_OFFSET_TAB_ADCxR[ADCTrig]));
WRITE_REG(*pReg, Src);
}
@@ -2464,7 +2464,7 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
{
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
REG_OFFSET_TAB_ADCxR[ADCTrig]));
return (*pReg);
@@ -2570,8 +2570,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
}
@@ -2594,8 +2594,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
}
@@ -2621,8 +2621,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
}
@@ -2647,8 +2647,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
}
@@ -2671,8 +2671,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MCR_HALF);
}
@@ -2692,8 +2692,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
}
@@ -2713,8 +2713,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL);
}
@@ -2734,8 +2734,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
}
@@ -2755,8 +2755,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
}
@@ -2776,8 +2776,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL);
}
@@ -2798,8 +2798,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
}
@@ -2819,8 +2819,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
}
@@ -2840,8 +2840,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL);
}
@@ -2867,8 +2867,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
}
@@ -2892,8 +2892,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
}
@@ -2916,8 +2916,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MCR_PREEN);
}
@@ -2937,8 +2937,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
}
@@ -2958,8 +2958,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL);
}
@@ -3002,8 +3002,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
}
@@ -3043,8 +3043,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]);
}
@@ -3081,8 +3081,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
}
@@ -3118,8 +3118,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
}
@@ -3137,8 +3137,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
}
@@ -3157,8 +3157,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
}
@@ -3177,8 +3177,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL);
}
@@ -3208,10 +3208,10 @@
__STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
uint32_t Mode)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
- register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
+ uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
}
@@ -3237,10 +3237,10 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
- register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
+ uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift);
}
@@ -3267,8 +3267,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
}
@@ -3289,8 +3289,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
}
@@ -3312,8 +3312,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
}
@@ -3334,8 +3334,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MPER_MPER));
}
@@ -3357,8 +3357,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
}
@@ -3379,8 +3379,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MREP_MREP));
}
@@ -3404,8 +3404,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
}
@@ -3428,8 +3428,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
}
@@ -3453,8 +3453,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
}
@@ -3477,8 +3477,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
}
@@ -3502,8 +3502,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
}
@@ -3526,8 +3526,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
}
@@ -3551,8 +3551,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
}
@@ -3575,8 +3575,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
}
@@ -3662,8 +3662,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
WRITE_REG(*pReg, ResetTrig);
}
@@ -3742,8 +3742,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_REG(*pReg));
}
@@ -3762,8 +3762,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_REG(*pReg));
}
@@ -3782,8 +3782,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_REG(*pReg));
}
@@ -3870,8 +3870,8 @@
__STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
uint32_t CaptureTrig)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
WRITE_REG(*pReg, CaptureTrig);
}
@@ -3956,8 +3956,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
return (READ_REG(*pReg));
}
@@ -3976,8 +3976,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_OUTR_DTEN);
}
@@ -3996,8 +3996,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
}
@@ -4016,8 +4016,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL);
@@ -4061,8 +4061,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
}
@@ -4102,8 +4102,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
}
@@ -4123,8 +4123,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
}
@@ -4144,8 +4144,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
}
@@ -4164,8 +4164,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL);
}
@@ -4194,8 +4194,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, Faults);
}
@@ -4224,8 +4224,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, Faults);
}
@@ -4254,8 +4254,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL);
@@ -4276,8 +4276,8 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
}
@@ -4306,7 +4306,7 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
{
- register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
+ uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
}
@@ -4332,7 +4332,7 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
+ uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
}
@@ -4419,8 +4419,8 @@
__STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + (4U * iTimer)));
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + (4U * iTimer)));
WRITE_REG(*pReg, Registers);
}
@@ -4441,8 +4441,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
}
@@ -4463,8 +4463,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
}
@@ -4522,9 +4522,9 @@
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
}
@@ -4579,9 +4579,9 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
}
@@ -4625,9 +4625,9 @@
__STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
uint32_t LatchStatus)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
}
@@ -4668,9 +4668,9 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
}
@@ -4703,8 +4703,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
}
@@ -4732,8 +4732,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
}
@@ -4760,8 +4760,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
}
@@ -4781,8 +4781,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
}
@@ -4801,8 +4801,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_DTR_DTR));
}
@@ -4824,8 +4824,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
}
@@ -4846,8 +4846,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
}
@@ -4867,8 +4867,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
}
@@ -4887,8 +4887,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
}
@@ -4910,8 +4910,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
}
@@ -4932,8 +4932,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
}
@@ -4952,8 +4952,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_DTR_DTRLK);
}
@@ -4972,8 +4972,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
}
@@ -4992,8 +4992,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_DTR_DTFLK);
}
@@ -5012,8 +5012,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
}
@@ -5048,8 +5048,8 @@
*/
__STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
}
@@ -5088,8 +5088,8 @@
*/
__STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
}
@@ -5124,8 +5124,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
}
@@ -5156,8 +5156,8 @@
*/
__STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
}
@@ -5184,8 +5184,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
}
@@ -5223,8 +5223,8 @@
*/
__STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
}
@@ -5259,8 +5259,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
}
@@ -5388,8 +5388,8 @@
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
REG_OFFSET_TAB_SETxR[iOutput]));
WRITE_REG(*pReg, SetSrc);
}
@@ -5508,8 +5508,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
REG_OFFSET_TAB_SETxR[iOutput]));
return (uint32_t) READ_REG(*pReg);
}
@@ -5629,8 +5629,8 @@
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
REG_OFFSET_TAB_SETxR[iOutput]));
WRITE_REG(*pReg, ResetSrc);
}
@@ -5749,8 +5749,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
REG_OFFSET_TAB_SETxR[iOutput]));
return (uint32_t) READ_REG(*pReg);
}
@@ -5792,8 +5792,8 @@
*/
__STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
(Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
@@ -5822,8 +5822,8 @@
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
}
@@ -5850,8 +5850,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
@@ -5880,8 +5880,8 @@
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
}
@@ -5908,8 +5908,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
@@ -5939,8 +5939,8 @@
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
}
@@ -5967,8 +5967,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
@@ -6000,8 +6000,8 @@
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
}
@@ -6030,8 +6030,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
@@ -6060,8 +6060,8 @@
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
}
@@ -6088,8 +6088,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
@@ -6118,8 +6118,8 @@
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
}
@@ -6146,8 +6146,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
@@ -6175,8 +6175,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
HRTIM_TIMISR_O1STAT_Pos);
@@ -6213,8 +6213,8 @@
0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */
};
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
SET_BIT(*pReg, HRTIM_SET1R_SST);
}
@@ -6241,8 +6241,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
- register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
+ uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
HRTIM_TIMISR_O1CPY_Pos);
@@ -6322,8 +6322,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
{
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
(Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
@@ -6362,8 +6362,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
{
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
}
@@ -6400,8 +6400,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)
{
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
}
@@ -6439,8 +6439,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
{
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
}
@@ -6475,8 +6475,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
{
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
}
@@ -6515,8 +6515,8 @@
__STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
{
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
}
@@ -6553,8 +6553,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
{
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
}
@@ -6586,8 +6586,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
{
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
}
@@ -6617,8 +6617,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event)
{
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
}
@@ -6658,7 +6658,7 @@
*/
__STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
{
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
(Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
}
@@ -6697,7 +6697,7 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event)
{
- register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
+ uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
(uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
}
@@ -6769,8 +6769,8 @@
*/
__STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
{
- register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]),
(Configuration << REG_SHIFT_TAB_FLTxE[iFault]));
@@ -6798,8 +6798,8 @@
*/
__STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
{
- register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault]));
}
@@ -6824,8 +6824,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
- register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
}
@@ -6852,8 +6852,8 @@
*/
__STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
{
- register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault]));
}
@@ -6878,8 +6878,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
- register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
}
@@ -6920,8 +6920,8 @@
*/
__STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
{
- register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault]));
}
@@ -6960,8 +6960,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
- register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
@@ -7016,8 +7016,8 @@
*/
__STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
- register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
}
@@ -7040,8 +7040,8 @@
*/
__STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
- register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
}
@@ -7064,8 +7064,8 @@
*/
__STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
- register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
}
@@ -7088,8 +7088,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
- register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
(HRTIM_IER_FLT1)) ? 1UL : 0UL);
@@ -7764,8 +7764,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MUPD);
}
@@ -7786,8 +7786,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL);
@@ -7809,8 +7809,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MREP);
@@ -7832,8 +7832,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL);
@@ -7855,8 +7855,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MCMP1);
}
@@ -7877,8 +7877,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL);
@@ -7900,8 +7900,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MCMP2);
}
@@ -7922,8 +7922,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL);
@@ -7945,8 +7945,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MCMP3);
}
@@ -7967,8 +7967,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL);
@@ -7990,8 +7990,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MCMP4);
}
@@ -8012,8 +8012,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL);
@@ -8033,8 +8033,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
}
@@ -8053,8 +8053,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL);
@@ -8074,8 +8074,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
}
@@ -8094,8 +8094,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL);
@@ -8115,8 +8115,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
}
@@ -8135,8 +8135,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL);
@@ -8156,8 +8156,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
}
@@ -8176,8 +8176,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL);
@@ -8197,8 +8197,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
}
@@ -8217,8 +8217,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL);
@@ -8238,8 +8238,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
}
@@ -8258,8 +8258,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL);
@@ -8279,8 +8279,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
}
@@ -8299,8 +8299,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL);
@@ -8320,8 +8320,8 @@
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC);
}
@@ -8340,8 +8340,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL);
@@ -8635,8 +8635,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
}
@@ -8657,8 +8657,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
}
@@ -8679,8 +8679,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL);
@@ -8702,8 +8702,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
}
@@ -8724,8 +8724,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
}
@@ -8746,8 +8746,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL);
@@ -8769,8 +8769,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
}
@@ -8791,8 +8791,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
}
@@ -8813,8 +8813,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL);
@@ -8836,8 +8836,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
}
@@ -8858,8 +8858,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
}
@@ -8880,8 +8880,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL);
@@ -8903,8 +8903,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
}
@@ -8925,8 +8925,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
}
@@ -8947,8 +8947,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL);
@@ -8970,8 +8970,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
}
@@ -8992,8 +8992,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
}
@@ -9014,8 +9014,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL);
@@ -9035,8 +9035,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
}
@@ -9055,8 +9055,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
}
@@ -9075,8 +9075,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL);
@@ -9096,8 +9096,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
}
@@ -9116,8 +9116,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
}
@@ -9136,8 +9136,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL);
@@ -9157,8 +9157,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
}
@@ -9177,8 +9177,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
}
@@ -9197,8 +9197,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL);
@@ -9218,8 +9218,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
}
@@ -9238,8 +9238,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
}
@@ -9258,8 +9258,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL);
@@ -9279,8 +9279,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
}
@@ -9299,8 +9299,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
}
@@ -9319,8 +9319,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL);
@@ -9340,8 +9340,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
}
@@ -9360,8 +9360,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
}
@@ -9380,8 +9380,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL);
@@ -9401,8 +9401,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
}
@@ -9421,8 +9421,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
}
@@ -9441,8 +9441,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL);
@@ -9462,8 +9462,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
}
@@ -9482,8 +9482,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
}
@@ -9502,8 +9502,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL);
@@ -9566,8 +9566,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
}
@@ -9588,8 +9588,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
}
@@ -9610,8 +9610,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL);
@@ -9633,8 +9633,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
}
@@ -9655,8 +9655,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
}
@@ -9677,8 +9677,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL);
@@ -9700,8 +9700,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
}
@@ -9722,8 +9722,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
}
@@ -9744,8 +9744,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL);
@@ -9767,8 +9767,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
}
@@ -9789,8 +9789,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
}
@@ -9811,8 +9811,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL);
@@ -9834,8 +9834,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
}
@@ -9856,8 +9856,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
}
@@ -9878,8 +9878,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL);
@@ -9901,8 +9901,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
}
@@ -9923,8 +9923,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
}
@@ -9945,8 +9945,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL);
@@ -9966,8 +9966,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
}
@@ -9986,8 +9986,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
}
@@ -10006,8 +10006,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL);
@@ -10027,8 +10027,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
}
@@ -10047,8 +10047,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
}
@@ -10067,8 +10067,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL);
@@ -10088,8 +10088,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
}
@@ -10108,8 +10108,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
}
@@ -10128,8 +10128,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL);
@@ -10149,8 +10149,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
}
@@ -10169,8 +10169,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
}
@@ -10189,8 +10189,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL);
@@ -10210,8 +10210,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
}
@@ -10230,8 +10230,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
}
@@ -10250,8 +10250,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL);
@@ -10271,8 +10271,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
}
@@ -10291,8 +10291,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
}
@@ -10311,8 +10311,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL);
@@ -10332,8 +10332,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
}
@@ -10352,8 +10352,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
}
@@ -10372,8 +10372,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL);
@@ -10393,8 +10393,8 @@
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
}
@@ -10413,8 +10413,8 @@
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
}
@@ -10433,8 +10433,8 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
- register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL);
diff --git a/Inc/stm32h7xx_ll_hsem.h b/Inc/stm32h7xx_ll_hsem.h
index b1d8758..1e5953c 100644
--- a/Inc/stm32h7xx_ll_hsem.h
+++ b/Inc/stm32h7xx_ll_hsem.h
@@ -589,6 +589,7 @@
return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
}
#endif /* DUAL_CORE */
+
/**
* @}
*/
diff --git a/Inc/stm32h7xx_ll_i2c.h b/Inc/stm32h7xx_ll_i2c.h
index 5acff4c..d91b7c2 100644
--- a/Inc/stm32h7xx_ll_i2c.h
+++ b/Inc/stm32h7xx_ll_i2c.h
@@ -32,7 +32,7 @@
* @{
*/
-#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
+#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) || defined (I2C5)
/** @defgroup I2C_LL I2C
* @{
@@ -67,38 +67,38 @@
typedef struct
{
uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
- This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
+ This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
This parameter must be set by referring to the STM32CubeMX Tool and
- the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
+ the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
- This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
+ This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
uint32_t DigitalFilter; /*!< Configures the digital noise filter.
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
uint32_t OwnAddress1; /*!< Specifies the device own address 1.
- This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
+ This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
- This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
+ This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
- This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
+ This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
} LL_I2C_InitTypeDef;
@@ -578,7 +578,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
{
- register uint32_t data_reg_addr;
+ uint32_t data_reg_addr;
if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
{
@@ -664,7 +664,7 @@
/**
* @brief Enable Wakeup from STOP.
- * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when Digital Filter is disabled.
* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
@@ -678,7 +678,7 @@
/**
* @brief Disable Wakeup from STOP.
- * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
* @param I2Cx I2C Instance.
@@ -691,7 +691,7 @@
/**
* @brief Check if Wakeup from STOP is enabled or disabled.
- * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
* @param I2Cx I2C Instance.
@@ -941,7 +941,7 @@
/**
* @brief Configure peripheral mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
* CR1 SMBDEN LL_I2C_SetMode
@@ -960,7 +960,7 @@
/**
* @brief Get peripheral mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
* CR1 SMBDEN LL_I2C_GetMode
@@ -978,7 +978,7 @@
/**
* @brief Enable SMBus alert (Host or Device mode)
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is drived low and
@@ -996,7 +996,7 @@
/**
* @brief Disable SMBus alert (Host or Device mode)
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
@@ -1014,7 +1014,7 @@
/**
* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
* @param I2Cx I2C Instance.
@@ -1027,7 +1027,7 @@
/**
* @brief Enable SMBus Packet Error Calculation (PEC).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
* @param I2Cx I2C Instance.
@@ -1040,7 +1040,7 @@
/**
* @brief Disable SMBus Packet Error Calculation (PEC).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
* @param I2Cx I2C Instance.
@@ -1053,7 +1053,7 @@
/**
* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
* @param I2Cx I2C Instance.
@@ -1066,7 +1066,7 @@
/**
* @brief Configure the SMBus Clock Timeout.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
@@ -1089,7 +1089,7 @@
/**
* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
@@ -1104,7 +1104,7 @@
/**
* @brief Get the SMBus Clock TimeoutA setting.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
* @param I2Cx I2C Instance.
@@ -1117,7 +1117,7 @@
/**
* @brief Set the SMBus Clock TimeoutA mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
@@ -1134,7 +1134,7 @@
/**
* @brief Get the SMBus Clock TimeoutA mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
* @param I2Cx I2C Instance.
@@ -1149,7 +1149,7 @@
/**
* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutB is disabled.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
@@ -1164,7 +1164,7 @@
/**
* @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
* @param I2Cx I2C Instance.
@@ -1177,7 +1177,7 @@
/**
* @brief Enable the SMBus Clock Timeout.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
@@ -1195,7 +1195,7 @@
/**
* @brief Disable the SMBus Clock Timeout.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
@@ -1213,7 +1213,7 @@
/**
* @brief Check if the SMBus Clock Timeout is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
@@ -1443,7 +1443,7 @@
/**
* @brief Enable Error interrupts.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
@@ -1463,7 +1463,7 @@
/**
* @brief Disable Error interrupts.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
@@ -1645,7 +1645,7 @@
/**
* @brief Indicate the status of SMBus PEC error flag in reception.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When the received PEC does not match with the PEC register content.
@@ -1660,7 +1660,7 @@
/**
* @brief Indicate the status of SMBus Timeout detection flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When a timeout or extended clock timeout occurs.
@@ -1675,7 +1675,7 @@
/**
* @brief Indicate the status of SMBus alert flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When SMBus host configuration, SMBus alert enabled and
@@ -1782,7 +1782,7 @@
/**
* @brief Clear SMBus PEC error flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
* @param I2Cx I2C Instance.
@@ -1795,7 +1795,7 @@
/**
* @brief Clear SMBus Timeout detection flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
* @param I2Cx I2C Instance.
@@ -1808,7 +1808,7 @@
/**
* @brief Clear SMBus Alert flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
* @param I2Cx I2C Instance.
@@ -2123,7 +2123,7 @@
/**
* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
* This bit has no effect when RELOAD bit is set.
@@ -2139,7 +2139,7 @@
/**
* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
* @param I2Cx I2C Instance.
@@ -2152,7 +2152,7 @@
/**
* @brief Get the SMBus Packet Error byte calculated.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
* @param I2Cx I2C Instance.
@@ -2213,7 +2213,7 @@
* @}
*/
-#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
+#endif /* I2C1 || I2C2 || I2C3 || I2C4 || I2C5 */
/**
* @}
diff --git a/Inc/stm32h7xx_ll_lpuart.h b/Inc/stm32h7xx_ll_lpuart.h
index a7ce8bc..1471bdd 100644
--- a/Inc/stm32h7xx_ll_lpuart.h
+++ b/Inc/stm32h7xx_ll_lpuart.h
@@ -1372,9 +1372,9 @@
*/
__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
{
- register uint32_t lpuartdiv;
- register uint32_t brrresult;
- register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
+ uint32_t lpuartdiv;
+ uint32_t brrresult;
+ uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
@@ -2482,7 +2482,7 @@
*/
__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
{
- register uint32_t data_reg_addr;
+ uint32_t data_reg_addr;
if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
{
diff --git a/Inc/stm32h7xx_ll_mdma.h b/Inc/stm32h7xx_ll_mdma.h
index cf645c6..18609ad 100644
--- a/Inc/stm32h7xx_ll_mdma.h
+++ b/Inc/stm32h7xx_ll_mdma.h
@@ -691,7 +691,7 @@
*/
__STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN);
}
@@ -721,7 +721,7 @@
*/
__STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN);
}
@@ -751,7 +751,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN) == (MDMA_CCR_EN)) ? 1UL : 0UL);
}
@@ -781,7 +781,7 @@
*/
__STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_SWRQ);
}
@@ -817,7 +817,7 @@
*/
__STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR,
MDMA_CCR_WEX | MDMA_CCR_HEX | MDMA_CCR_BEX, Configuration);
@@ -851,7 +851,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_WEX, Endianness);
}
@@ -884,7 +884,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_WEX));
}
@@ -917,7 +917,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_HEX, Endianness);
}
@@ -950,7 +950,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_HEX));
}
@@ -983,7 +983,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_BEX, Endianness);
}
@@ -1016,7 +1016,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_BEX));
}
@@ -1051,7 +1051,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_PL, Priority);
}
@@ -1086,7 +1086,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_PL));
}
@@ -1146,7 +1146,7 @@
*/
__STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR,
Configuration | ((BufferXferLength << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk));
@@ -1177,7 +1177,7 @@
*/
__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM);
}
@@ -1207,7 +1207,7 @@
*/
__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM);
}
@@ -1237,7 +1237,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM) == (MDMA_CTCR_BWM)) ? 1UL : 0UL);
}
@@ -1270,7 +1270,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SWRM, RequestMode);
}
@@ -1303,7 +1303,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SWRM));
}
@@ -1338,7 +1338,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TRGM, TriggerMode);
}
@@ -1373,7 +1373,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TRGM));
}
@@ -1407,7 +1407,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PAM, PaddingAlignment);
}
@@ -1441,7 +1441,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PAM));
}
@@ -1472,7 +1472,7 @@
*/
__STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE);
}
@@ -1502,7 +1502,7 @@
*/
__STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE);
}
@@ -1532,7 +1532,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE) == (MDMA_CTCR_PKE)) ? 1UL : 0UL);
}
@@ -1563,7 +1563,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TLEN,
(Length << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk);
@@ -1595,7 +1595,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TLEN) >> MDMA_CTCR_TLEN_Pos);
}
@@ -1634,7 +1634,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DBURST, Dburst);
}
@@ -1673,7 +1673,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DBURST));
}
@@ -1712,7 +1712,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SBURST, Sburst);
}
@@ -1751,7 +1751,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SBURST));
}
@@ -1786,7 +1786,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINCOS, IncSize);
}
@@ -1821,7 +1821,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINCOS));
}
@@ -1856,7 +1856,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINCOS, IncSize);
}
@@ -1891,7 +1891,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINCOS));
}
@@ -1926,7 +1926,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DSIZE, DestDataSize);
}
@@ -1961,7 +1961,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DSIZE));
}
@@ -1996,7 +1996,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SSIZE, SrcDataSize);
}
@@ -2031,7 +2031,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SSIZE));
}
@@ -2065,7 +2065,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINC, DestIncMode);
}
@@ -2099,7 +2099,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINC));
}
@@ -2133,7 +2133,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINC, SrcIncMode);
}
@@ -2167,7 +2167,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINC));
}
@@ -2200,7 +2200,7 @@
*/
__STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR,
MDMA_CBNDTR_BRC | MDMA_CBNDTR_BNDT,
@@ -2233,7 +2233,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BNDT, (BlkDataLength & MDMA_CBNDTR_BNDT_Msk));
}
@@ -2264,7 +2264,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BNDT));
}
@@ -2295,7 +2295,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRC,
(BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk);
@@ -2327,7 +2327,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRC) >> MDMA_CBNDTR_BRC_Pos);
}
@@ -2361,7 +2361,7 @@
*/
__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR,
MDMA_CBNDTR_BRDUM | MDMA_CBNDTR_BRSUM,
@@ -2396,7 +2396,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRDUM, DestAdrUpdateMode);
}
@@ -2429,7 +2429,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRDUM));
}
@@ -2462,7 +2462,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRSUM, SrcAdrUpdateMode);
}
@@ -2495,7 +2495,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRSUM));
}
@@ -2529,7 +2529,7 @@
*/
__STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR, DstAddress);
@@ -2560,7 +2560,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
}
@@ -2591,7 +2591,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR));
}
@@ -2622,7 +2622,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
}
@@ -2653,7 +2653,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR));
}
@@ -2687,7 +2687,7 @@
*/
__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR,
(SrctAdrUpdateValue & MDMA_CBRUR_SUV_Msk) | ((DestAdrUpdateValue << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk));
@@ -2719,7 +2719,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_DUV,
((DestAdrUpdateValue << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk));
@@ -2751,7 +2751,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_DUV) >> MDMA_CBRUR_DUV_Pos);
}
@@ -2782,7 +2782,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_SUV, SrcAdrUpdateValue);
}
@@ -2813,7 +2813,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_SUV));
}
@@ -2844,7 +2844,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CLAR, LinkAddress);
}
@@ -2875,7 +2875,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CLAR));
}
@@ -2909,7 +2909,7 @@
*/
__STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR,
MDMA_CTBR_DBUS | MDMA_CTBR_SBUS,
@@ -2944,7 +2944,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_DBUS, DestBus);
}
@@ -2977,7 +2977,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_DBUS));
}
@@ -3010,7 +3010,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_SBUS, SrcBus);
}
@@ -3043,7 +3043,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_SBUS));
}
@@ -3111,7 +3111,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_TSEL, HWRequest);
}
@@ -3179,7 +3179,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_TSEL));
}
@@ -3210,7 +3210,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMAR, MaskAddress);
}
@@ -3241,7 +3241,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMAR));
}
@@ -3272,7 +3272,7 @@
*/
__STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMDR, MaskData);
}
@@ -3303,7 +3303,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMDR));
}
@@ -3336,7 +3336,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TED));
}
@@ -3367,7 +3367,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TEA));
}
@@ -3433,7 +3433,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_TEIF) == (MDMA_CISR_TEIF)) ? 1UL : 0UL);
}
@@ -3463,7 +3463,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_CTCIF) == (MDMA_CISR_CTCIF)) ? 1UL : 0UL);
}
@@ -3493,7 +3493,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_BRTIF) == (MDMA_CISR_BRTIF)) ? 1UL : 0UL);
}
@@ -3523,7 +3523,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_BTIF) == (MDMA_CISR_BTIF)) ? 1UL : 0UL);
}
@@ -3553,7 +3553,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_TCIF) == (MDMA_CISR_TCIF)) ? 1UL : 0UL);
}
@@ -3583,7 +3583,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_CRQA) == (MDMA_CISR_CRQA)) ? 1UL : 0UL);
}
@@ -3613,7 +3613,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_BSE) == (MDMA_CESR_BSE)) ? 1UL : 0UL);
}
@@ -3643,7 +3643,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_ASE) == (MDMA_CESR_ASE)) ? 1UL : 0UL);
}
@@ -3673,7 +3673,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TEMD) == (MDMA_CESR_TEMD)) ? 1UL : 0UL);
}
@@ -3703,7 +3703,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TELD) == (MDMA_CESR_TELD)) ? 1UL : 0UL);
}
@@ -3733,7 +3733,7 @@
*/
__STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CTEIF);
}
@@ -3763,7 +3763,7 @@
*/
__STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CCTCIF);
}
@@ -3793,7 +3793,7 @@
*/
__STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CBRTIF);
}
@@ -3823,7 +3823,7 @@
*/
__STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CBTIF);
}
@@ -3853,7 +3853,7 @@
*/
__STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CLTCIF);
}
@@ -3891,7 +3891,7 @@
*/
__STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE);
}
@@ -3921,7 +3921,7 @@
*/
__STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE);
}
@@ -3951,7 +3951,7 @@
*/
__STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE);
}
@@ -3981,7 +3981,7 @@
*/
__STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE);
}
@@ -4011,7 +4011,7 @@
*/
__STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE);
}
@@ -4041,7 +4041,7 @@
*/
__STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE);
}
@@ -4071,7 +4071,7 @@
*/
__STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE);
}
@@ -4101,7 +4101,7 @@
*/
__STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE);
}
@@ -4131,7 +4131,7 @@
*/
__STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE);
}
@@ -4161,7 +4161,7 @@
*/
__STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE);
}
@@ -4191,7 +4191,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE) == MDMA_CCR_TEIE) ? 1UL : 0UL);
}
@@ -4221,7 +4221,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE) == MDMA_CCR_CTCIE) ? 1UL : 0UL);
}
@@ -4251,7 +4251,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE) == MDMA_CCR_BRTIE) ? 1UL : 0UL);
}
@@ -4281,7 +4281,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE) == MDMA_CCR_BTIE) ? 1UL : 0UL);
}
@@ -4311,7 +4311,7 @@
*/
__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)
{
- register uint32_t mdma_base_addr = (uint32_t)MDMAx;
+ uint32_t mdma_base_addr = (uint32_t)MDMAx;
return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE) == MDMA_CCR_TCIE) ? 1UL : 0UL);
}
diff --git a/Inc/stm32h7xx_ll_opamp.h b/Inc/stm32h7xx_ll_opamp.h
index f415522..9808ab1 100644
--- a/Inc/stm32h7xx_ll_opamp.h
+++ b/Inc/stm32h7xx_ll_opamp.h
@@ -501,7 +501,7 @@
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
{
- register uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAHSM));
+ uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAHSM));
return (uint32_t)(power_mode | (power_mode >> (OPAMP_CSR_OPAHSM_Pos)));
}
@@ -575,7 +575,7 @@
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
{
- register uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
+ uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
/* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting */
/* input not connected. */
@@ -661,7 +661,7 @@
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
{
- register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
+ uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
return (uint32_t)((CalibrationSelection << 4)|
(((CalibrationSelection & OPAMP_CSR_CALSEL_1) == 0UL) ? OPAMP_OTR_TRIMOFFSETN : OPAMP_OTR_TRIMOFFSETP));
@@ -701,7 +701,7 @@
*/
__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
{
- register __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
+ __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
/* Set bits with position in register depending on parameter */
/* "TransistorsDiffPair". */
@@ -731,7 +731,7 @@
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)
{
- register const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
+ const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
/* Retrieve bits with position in register depending on parameter */
/* "TransistorsDiffPair". */
diff --git a/Inc/stm32h7xx_ll_pwr.h b/Inc/stm32h7xx_ll_pwr.h
index 1e0d0cd..98602e2 100644
--- a/Inc/stm32h7xx_ll_pwr.h
+++ b/Inc/stm32h7xx_ll_pwr.h
@@ -74,9 +74,13 @@
#define LL_PWR_FLAG_CPU2_CSSF PWR_CPU2CR_CSSF /*!< Clear flags for CPU2 */
#endif /* DUAL_CORE */
#define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /*!< Clear PC1 WKUP flag */
+#if defined (PWR_WKUPCR_WKUPC5)
#define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /*!< Clear PI11 WKUP flag */
+#endif /* defined (PWR_WKUPCR_WKUPC5) */
#define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear PC13 WKUP flag */
+#if defined (PWR_WKUPCR_WKUPC3)
#define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear PI8 WKUP flag */
+#endif /* defined (PWR_WKUPCR_WKUPC3) */
#define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear PA2 WKUP flag */
#define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear PA0 WKUP flag */
/**
@@ -131,9 +135,13 @@
#endif /* PWR_CPUCR_PDDS_D2 */
#define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */
+#if defined (PWR_WKUPFR_WKUPF5)
#define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
+#endif /* defined (PWR_WKUPFR_WKUPF5) */
#define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
+#if defined (PWR_WKUPFR_WKUPF3)
#define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */
+#endif /* defined (PWR_WKUPFR_WKUPF3) */
#define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */
#define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */
/**
@@ -186,8 +194,12 @@
#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_D3CR_VOS_0 /*!< Select voltage scale 3 */
#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_1 /*!< Select voltage scale 2 */
#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */
+#if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
#define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
#else
+#define LL_PWR_REGU_VOLTAGE_SCALE0 0x00000000U /*!< Select voltage scale 0 */
+#endif /* defined (SYSCFG_PWRCR_ODEN) */
+#else
#define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Select voltage scale 3 */
#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0 /*!< Select voltage scale 2 */
#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1 /*!< Select voltage scale 1 */
@@ -257,9 +269,13 @@
*/
#define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */
#define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */
+#if defined (PWR_WKUPEPR_WKUPEN3)
#define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PI8 */
+#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
#define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PC13 */
+#if defined (PWR_WKUPEPR_WKUPEN5)
#define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 /*!< Wake-Up pin 5 : PI11 */
+#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
#define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 /*!< Wake-Up pin 6 : PC1 */
/**
* @}
@@ -279,7 +295,7 @@
* @{
*/
#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */
-#if defined (SMPS)
+#if defined (SMPS)
#define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS */
#define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
#define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */
@@ -1341,7 +1357,7 @@
}
#endif /* DUAL_CORE */
-#if defined (PWR_CPUCR_PDDS_D3)
+#if defined (PWR_CPUCR_PDDS_D2)
/**
* @brief Get the D3 Domain Power Down mode when the CPU enters deepsleep
* @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode
@@ -1365,7 +1381,7 @@
{
return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));
}
-#endif /* PWR_CPUCR_PDDS_D3 */
+#endif /* PWR_CPUCR_PDDS_D2 */
#if defined (DUAL_CORE)
/**
@@ -1553,7 +1569,7 @@
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
- * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0
+ * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0
* is applied when PWR_D3CR_VOS[1:0] = 0b11 and SYSCFG_PWRCR_ODEN = 0b1.
* @retval None
*/
@@ -1569,7 +1585,7 @@
/**
* @brief Get the main internal Regulator output voltage
* @rmtoll D3CR VOS LL_PWR_GetRegulVoltageScaling
- * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking
+ * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking
* VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
@@ -1597,10 +1613,13 @@
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
* @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
* @arg @ref LL_PWR_WAKEUP_PIN6
+ *
+ * (*) value not defined in all devices.
+ *
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
@@ -1619,10 +1638,13 @@
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
* @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
* @arg @ref LL_PWR_WAKEUP_PIN6
+ *
+ * (*) value not defined in all devices.
+ *
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
@@ -1641,10 +1663,13 @@
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
* @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
* @arg @ref LL_PWR_WAKEUP_PIN6
+ *
+ * (*) value not defined in all devices.
+ *
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
@@ -1663,10 +1688,13 @@
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
* @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
* @arg @ref LL_PWR_WAKEUP_PIN6
+ *
+ * (*) value not defined in all devices.
+ *
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
@@ -1685,10 +1713,13 @@
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
* @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
* @arg @ref LL_PWR_WAKEUP_PIN6
+ *
+ * (*) value not defined in all devices.
+ *
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
@@ -1707,10 +1738,13 @@
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
* @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
* @arg @ref LL_PWR_WAKEUP_PIN6
+ *
+ * (*) value not defined in all devices.
+ *
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
@@ -1729,10 +1763,13 @@
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
* @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
* @arg @ref LL_PWR_WAKEUP_PIN6
+ *
+ * (*) value not defined in all devices.
+ *
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
@@ -1753,10 +1790,13 @@
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
* @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
* @arg @ref LL_PWR_WAKEUP_PIN6
+ *
+ * (*) value not defined in all devices.
+ *
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
@@ -1777,10 +1817,13 @@
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
* @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
* @arg @ref LL_PWR_WAKEUP_PIN6
+ *
+ * (*) value not defined in all devices.
+ *
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
@@ -1801,10 +1844,13 @@
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
- * @arg @ref LL_PWR_WAKEUP_PIN3
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
* @arg @ref LL_PWR_WAKEUP_PIN4
- * @arg @ref LL_PWR_WAKEUP_PIN5
+ * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
* @arg @ref LL_PWR_WAKEUP_PIN6
+ *
+ * (*) value not defined in all devices.
+ *
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
* @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
@@ -1812,7 +1858,7 @@
*/
__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
{
- register uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+ uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
}
@@ -2079,6 +2125,7 @@
return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
}
+#if defined (PWR_WKUPFR_WKUPF5)
/**
* @brief Get Wake-up Flag 5
* @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5
@@ -2088,6 +2135,7 @@
{
return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
}
+#endif /* defined (PWR_WKUPFR_WKUPF5) */
/**
* @brief Get Wake-up Flag 4
@@ -2099,6 +2147,7 @@
return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
}
+#if defined (PWR_WKUPFR_WKUPF3)
/**
* @brief Get Wake-up Flag 3
* @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3
@@ -2108,6 +2157,7 @@
{
return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
}
+#endif /* defined (PWR_WKUPFR_WKUPF3) */
/**
* @brief Get Wake-up Flag 2
@@ -2161,6 +2211,7 @@
WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
}
+#if defined (PWR_WKUPCR_WKUPC5)
/**
* @brief Clear Wake-up Flag 5
* @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5
@@ -2170,6 +2221,7 @@
{
WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
}
+#endif /* defined (PWR_WKUPCR_WKUPC5) */
/**
* @brief Clear Wake-up Flag 4
@@ -2181,6 +2233,7 @@
WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
}
+#if defined (PWR_WKUPCR_WKUPC3)
/**
* @brief Clear Wake-up Flag 3
* @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3
@@ -2190,6 +2243,7 @@
{
WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
}
+#endif /* defined (PWR_WKUPCR_WKUPC3) */
/**
* @brief Clear Wake-up Flag 2
diff --git a/Inc/stm32h7xx_ll_rcc.h b/Inc/stm32h7xx_ll_rcc.h
index 3ec127c..ed63ebf 100644
--- a/Inc/stm32h7xx_ll_rcc.h
+++ b/Inc/stm32h7xx_ll_rcc.h
@@ -159,11 +159,11 @@
* @{
*/
#if !defined (HSE_VALUE)
-#if defined(RCC_VER_X)
+#if defined(RCC_VER_X) || defined(RCC_VER_3_0)
#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
#else
#define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */
-#endif /* RCC_VER_X */
+#endif /* RCC_VER_X || RCC_VER_3_0 */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
@@ -528,6 +528,29 @@
#define LL_RCC_USART16_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
#define LL_RCC_USART16_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)
#define LL_RCC_USART16_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
+/* Aliases */
+#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_RCC_USART16_CLKSOURCE_PCLK2
+#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_RCC_USART16_CLKSOURCE_PLL2Q
+#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_RCC_USART16_CLKSOURCE_PLL3Q
+#define LL_RCC_USART16910_CLKSOURCE_HSI LL_RCC_USART16_CLKSOURCE_HSI
+#define LL_RCC_USART16910_CLKSOURCE_CSI LL_RCC_USART16_CLKSOURCE_CSI
+#define LL_RCC_USART16910_CLKSOURCE_LSE LL_RCC_USART16_CLKSOURCE_LSE
+
+#elif defined(RCC_D2CCIP2R_USART16910SEL)
+#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
+#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0)
+#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1)
+#define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)
+#define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2)
+#define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)
+/* Aliases */
+#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2
+#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q
+#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q
+#define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI
+#define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI
+#define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE
+
#else
#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
@@ -592,6 +615,23 @@
#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)
#define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)
#define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
+/* Aliases */
+#define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_RCC_I2C123_CLKSOURCE_PCLK1
+#define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_RCC_I2C123_CLKSOURCE_PLL3R
+#define LL_RCC_I2C1235_CLKSOURCE_HSI LL_RCC_I2C123_CLKSOURCE_HSI
+#define LL_RCC_I2C1235_CLKSOURCE_CSI LL_RCC_I2C123_CLKSOURCE_CSI
+
+#elif defined (RCC_D2CCIP2R_I2C1235SEL)
+#define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
+#define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0)
+#define LL_RCC_I2C1235_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1)
+#define LL_RCC_I2C1235_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)
+/* Aliases */
+#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_RCC_I2C1235_CLKSOURCE_PCLK1
+#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_RCC_I2C1235_CLKSOURCE_PLL3R
+#define LL_RCC_I2C123_CLKSOURCE_HSI LL_RCC_I2C1235_CLKSOURCE_HSI
+#define LL_RCC_I2C123_CLKSOURCE_CSI LL_RCC_I2C1235_CLKSOURCE_CSI
+
#else
#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
@@ -717,6 +757,9 @@
#define LL_RCC_SAI4A_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_1)
#define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
#define LL_RCC_SAI4A_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2)
+#if defined(RCC_VER_3_0)
+#define LL_RCC_SAI4A_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)
+#endif /* RCC_VER_3_0 */
#endif /* SAI4_Block_A */
#if defined(SAI4_Block_B)
#define LL_RCC_SAI4B_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U)
@@ -724,6 +767,9 @@
#define LL_RCC_SAI4B_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_1)
#define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
#define LL_RCC_SAI4B_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2)
+#if defined(RCC_VER_3_0)
+#define LL_RCC_SAI4B_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)
+#endif /* RCC_VER_3_0 */
#endif /* SAI4_Block_B */
/**
* @}
@@ -867,10 +913,17 @@
/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE Peripheral OSPI clock source selection
* @{
*/
+#if defined(RCC_D1CCIPR_OCTOSPISEL)
+#define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U)
+#define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_OCTOSPISEL_0)
+#define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_OCTOSPISEL_1)
+#define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1)
+#else
#define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U)
#define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_CDCCIPR_OCTOSPISEL_0)
#define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_CDCCIPR_OCTOSPISEL_1)
#define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
+#endif /* RCC_D1CCIPR_OCTOSPISEL */
/**
* @}
*/
@@ -1010,11 +1063,15 @@
* @}
*/
-/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART get clock source
+/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
* @{
*/
#if defined (RCC_D2CCIP2R_USART16SEL)
#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
+#elif defined (RCC_D2CCIP2R_USART16910SEL)
+#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
+/* alias*/
+#define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE
#else
#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
/* alias*/
@@ -1029,7 +1086,7 @@
* @}
*/
-/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART get clock source
+/** @defgroup RCC_LL_EC_LPUARTx Peripheral LPUART get clock source
* @{
*/
#if defined(RCC_D3CCIPR_LPUART1SEL)
@@ -1041,13 +1098,21 @@
* @}
*/
-/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C get clock source
+/** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source
* @{
*/
#if defined(RCC_D2CCIP2R_I2C123SEL)
#define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
+/* alias */
+#define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE
+#elif defined(RCC_D2CCIP2R_I2C1235SEL)
+#define LL_RCC_I2C1235_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
+/* alias */
+#define LL_RCC_I2C123_CLKSOURCE LL_RCC_I2C1235_CLKSOURCE
#else
#define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
+/* alias */
+#define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE
#endif /* RCC_D2CCIP2R_I2C123SEL */
#if defined(RCC_D3CCIPR_I2C4SEL)
#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U)
@@ -1058,30 +1123,30 @@
* @}
*/
-/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM get clock source
+/** @defgroup RCC_LL_EC_LPTIMx Peripheral LPTIM get clock source
* @{
*/
#if defined(RCC_D2CCIP2R_LPTIM1SEL)
-#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U)
#else
-#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
#endif /* RCC_D2CCIP2R_LPTIM1SEL) */
#if defined(RCC_D3CCIPR_LPTIM2SEL)
-#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U)
#else
-#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
#endif /* RCC_D3CCIPR_LPTIM2SEL */
#if defined(RCC_D3CCIPR_LPTIM345SEL)
-#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
#else
-#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
#define LL_RCC_LPTIM3_CLKSOURCE LL_RCC_LPTIM345_CLKSOURCE /* alias */
#endif /* RCC_D3CCIPR_LPTIM345SEL */
/**
* @}
*/
-/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI get clock source
+/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
* @{
*/
#if defined(RCC_D2CCIP1R_SAI1SEL)
@@ -1108,7 +1173,7 @@
* @}
*/
-/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC get clock source
+/** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source
* @{
*/
#if defined(RCC_D1CCIPR_SDMMCSEL)
@@ -1120,7 +1185,7 @@
* @}
*/
-/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG get clock source
+/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
* @{
*/
#if (RCC_D2CCIP2R_RNGSEL)
@@ -1132,7 +1197,7 @@
* @}
*/
-/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB get clock source
+/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
* @{
*/
#if (RCC_D2CCIP2R_USBSEL)
@@ -1144,7 +1209,7 @@
* @}
*/
-/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC get clock source
+/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
* @{
*/
#if (RCC_D2CCIP2R_CECSEL)
@@ -1157,7 +1222,7 @@
*/
#if defined(DSI)
-/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI get clock source
+/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
* @{
*/
#define LL_RCC_DSI_CLKSOURCE RCC_D1CCIPR_DSISEL
@@ -1166,7 +1231,7 @@
*/
#endif /* DSI */
-/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM get clock source
+/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
* @{
*/
#if defined(RCC_D2CCIP1R_DFSDM1SEL)
@@ -1179,17 +1244,18 @@
*/
#if defined(DFSDM2_BASE)
-/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE Peripheral DFSDM2 get clock source
+/** @defgroup RCC_LL_EC_DFSDM2 Peripheral DFSDM2 get clock source
* @{
*/
#define LL_RCC_DFSDM2_CLKSOURCE RCC_SRDCCIPR_DFSDM2SEL
/**
* @}
*/
-#endif /* DFSDM2 */
+#endif /* DFSDM2_BASE */
-/** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC get clock source
+
+/** @defgroup RCC_LL_EC_FMC Peripheral FMC get clock source
* @{
*/
#if defined(RCC_D1CCIPR_FMCSEL)
@@ -1202,7 +1268,7 @@
*/
#if defined(QUADSPI)
-/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI get clock source
+/** @defgroup RCC_LL_EC_QSPI Peripheral QSPI get clock source
* @{
*/
#define LL_RCC_QSPI_CLKSOURCE RCC_D1CCIPR_QSPISEL
@@ -1212,16 +1278,20 @@
#endif /* QUADSPI */
#if defined(OCTOSPI1) || defined(OCTOSPI2)
-/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE Peripheral OSPI get clock source
+/** @defgroup RCC_LL_EC_OSPI Peripheral OSPI get clock source
* @{
*/
+#if defined(RCC_CDCCIPR_OCTOSPISEL)
#define LL_RCC_OSPI_CLKSOURCE RCC_CDCCIPR_OCTOSPISEL
+#else
+#define LL_RCC_OSPI_CLKSOURCE RCC_D1CCIPR_OCTOSPISEL
+#endif /* RCC_CDCCIPR_OCTOSPISEL */
/**
* @}
*/
#endif /* OCTOSPI1 || OCTOSPI2 */
-/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP get clock source
+/** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source
* @{
*/
#if defined(RCC_D1CCIPR_CKPERSEL)
@@ -1233,7 +1303,7 @@
* @}
*/
-/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI get clock source
+/** @defgroup RCC_LL_EC_SPIx Peripheral SPI get clock source
* @{
*/
#if defined(RCC_D2CCIP1R_SPI123SEL)
@@ -1255,7 +1325,7 @@
* @}
*/
-/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF get clock source
+/** @defgroup RCC_LL_EC_SPDIF Peripheral SPDIF get clock source
* @{
*/
#if defined(RCC_D2CCIP1R_SPDIFSEL)
@@ -1268,7 +1338,7 @@
*/
#if defined(FDCAN1) || defined(FDCAN2)
-/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN get clock source
+/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
* @{
*/
#if defined(RCC_D2CCIP1R_FDCANSEL)
@@ -1281,7 +1351,7 @@
*/
#endif /*FDCAN1 || FDCAN2*/
-/** @defgroup RCC_LL_EC_SWP_CLKSOURCE Peripheral SWP get clock source
+/** @defgroup RCC_LL_EC_SWP Peripheral SWP get clock source
* @{
*/
#if defined(RCC_D2CCIP1R_SWPSEL)
@@ -1293,7 +1363,7 @@
* @}
*/
-/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC get clock source
+/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
* @{
*/
#if defined(RCC_D3CCIPR_ADCSEL)
@@ -1740,7 +1810,7 @@
* @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,
* should trim the HSI to 64 MHz +/- 1 %
* @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming
- * @param Parameter can be a value between 0 and 127 (63 for Cut1.x)
+ * @param Value can be a value between 0 and 127 (63 for Cut1.x)
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
@@ -2779,15 +2849,16 @@
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
* @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
* @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
- * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
- * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
- * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
- * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
- * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
+ * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
+ * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
+ * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
+ * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
+ * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
* @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
+ * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*)
* @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
* @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
* @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
@@ -2799,6 +2870,7 @@
* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
* @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
* @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+ * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*)
* @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
* @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
* @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
@@ -2830,9 +2902,9 @@
__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
{
#if defined(RCC_D1CCIPR_FMCSEL)
- register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
+ uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
#else
- register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
+ uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
#endif /* */
MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
}
@@ -2945,15 +3017,16 @@
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
* @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
* @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
- * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
- * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
- * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
- * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
- * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
+ * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
+ * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
+ * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
+ * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
+ * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
* @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
* @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
+ * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*)
* @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
* @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
* @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
@@ -2965,6 +3038,7 @@
* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
* @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
* @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+ * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*)
* @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
* @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
* @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
@@ -3079,9 +3153,9 @@
__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
{
#if defined(RCC_D2CCIP1R_DFSDM1SEL)
- MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
+ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
#else
- MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
+ MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
#endif /* RCC_D2CCIP1R_DFSDM1SEL */
}
@@ -3090,7 +3164,7 @@
* @brief Configure DFSDMx Kernel clock source
* @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_SetDFSDM2ClockSource
* @param ClkSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
* @retval None
*/
@@ -3098,11 +3172,11 @@
{
MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
}
-#endif /* DFSDM2 */
+#endif /* DFSDM2_BASE */
/**
* @brief Configure FMCx Kernel clock source
- * @rmtoll D1CCIPR / CDCCIPR FMCSEL LL_RCC_SetFMCClockSource
+ * @rmtoll D1CCIPR / CDCCIPR FMCSEL LL_RCC_SetFMCClockSource
* @param ClkSource This parameter can be one of the following values:
* @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
* @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
@@ -3149,7 +3223,11 @@
*/
__STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)
{
+#if defined(RCC_D1CCIPR_OCTOSPISEL)
+ MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, ClkSource);
+#else
MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);
+#endif /* RCC_D1CCIPR_OCTOSPISEL */
}
#endif /* OCTOSPI1 || OCTOSPI2 */
@@ -3395,9 +3473,9 @@
__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
{
#if defined(RCC_D1CCIPR_FMCSEL)
- register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
+ const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
#else
- register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
+ const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
#endif /* RCC_D1CCIPR_FMCSEL */
return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) );
}
@@ -3478,7 +3556,7 @@
* @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
* D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
* D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_GetLPTIMClockSource
- * @param Perihp This parameter can be one of the following values:
+ * @param Periph This parameter can be one of the following values:
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
* @arg @ref LL_RCC_LPTIM2_CLKSOURCE
* @arg @ref LL_RCC_LPTIM345_CLKSOURCE
@@ -3515,10 +3593,12 @@
* D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_GetSAIClockSource\n
* D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_GetSAIClockSource
* @param Periph This parameter can be one of the following values:
- * @arg @ref LL_RCC_SAI1_CLKSOURCE
- * @arg @ref LL_RCC_SAI23_CLKSOURCE
- * @arg @ref LL_RCC_SAI4A_CLKSOURCE
- * @arg @ref LL_RCC_SAI4B_CLKSOURCE
+ * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
+ * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
+ * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
+ * @arg @ref LL_RCC_SAI23_CLKSOURCE (*)
+ * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
+ * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
@@ -3552,7 +3632,7 @@
* @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
* @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
* @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
- *
+ *
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
@@ -3718,7 +3798,7 @@
#if defined(QUADSPI)
/**
* @brief Get QSPI Kernel clock source
- * @rmtoll D1CCIPR / CDCCIPR QSPISEL LL_RCC_GetQSPIClockSource
+ * @rmtoll D1CCIPR / CDCCIPR QSPISEL LL_RCC_GetQSPIClockSource
* @param Periph This parameter can be one of the following values:
* @arg @ref LL_RCC_QSPI_CLKSOURCE
* @retval Returned value can be one of the following values:
@@ -3749,13 +3829,17 @@
__STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)
{
UNUSED(Periph);
+#if defined(RCC_D1CCIPR_OCTOSPISEL)
+ return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL));
+#else
return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));
+#endif /* RCC_D1CCIPR_OCTOSPISEL */
}
#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
/**
* @brief Get CLKP Kernel clock source
- * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_GetCLKPClockSource
+ * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_GetCLKPClockSource
* @param Periph This parameter can be one of the following values:
* @arg @ref LL_RCC_CLKP_CLKSOURCE
* @retval Returned value can be one of the following values:
@@ -6280,7 +6364,7 @@
uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
#if defined(DFSDM2_BASE)
uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);
-#endif /* DFSDM2 */
+#endif /* DFSDM2_BASE */
#if defined(DSI)
uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
#endif /* DSI */
diff --git a/Inc/stm32h7xx_ll_rng.h b/Inc/stm32h7xx_ll_rng.h
index 3f25df0..ab89a18 100644
--- a/Inc/stm32h7xx_ll_rng.h
+++ b/Inc/stm32h7xx_ll_rng.h
@@ -614,7 +614,7 @@
* @}
*/
-#if defined (RNG_VER_3_1)
+#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
/** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
* @{
*/
@@ -645,7 +645,7 @@
/**
* @}
*/
-#endif /*RNG_VER_3_1*/
+#endif /*End of RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
* @{
diff --git a/Inc/stm32h7xx_ll_rtc.h b/Inc/stm32h7xx_ll_rtc.h
index e9b866a..230b1e3 100644
--- a/Inc/stm32h7xx_ll_rtc.h
+++ b/Inc/stm32h7xx_ll_rtc.h
@@ -456,10 +456,10 @@
* @}
*/
-#if defined(TAMP_CR1_TAMP1E)
/** @defgroup RTC_LL_EC_TAMPER TAMPER
* @{
*/
+#if defined(TAMP_CR1_TAMP1E)
#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */
#endif /* TAMP_CR1_TAMP1E */
#if defined(TAMP_CR1_TAMP2E)
@@ -472,10 +472,10 @@
* @}
*/
-#if defined(TAMP_CR1_TAMP1E)
/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
* @{
*/
+#if defined(TAMP_CR1_TAMP1E)
#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased */
#endif /* TAMP_CR1_TAMP1E */
#if defined(TAMP_CR1_TAMP2E)
@@ -488,10 +488,10 @@
* @}
*/
-#if defined(TAMP_CR1_TAMP1E)
/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
* @{
*/
+#if defined(TAMP_CR1_TAMP1E)
#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
#endif /* TAMP_CR1_TAMP1E */
#if defined(TAMP_CR1_TAMP2E)
@@ -547,10 +547,10 @@
*/
#endif /* TAMP_FLTCR_TAMPFREQ */
-#if defined(TAMP_CR1_TAMP1E)
/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
* @{
*/
+#if defined(TAMP_CR1_TAMP1E)
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#endif /* TAMP_CR1_TAMP1E */
#if defined(TAMP_CR1_TAMP2E)
@@ -563,10 +563,10 @@
* @}
*/
-#if defined (RTC_TAMPCR_TAMP1E)
/** @defgroup RTC_LL_EC_TAMPER TAMPER
* @{
*/
+#if defined (RTC_TAMPCR_TAMP1E)
#define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */
#endif /* RTC_TAMPCR_TAMP1E */
#if defined (RTC_TAMPCR_TAMP2E)
@@ -579,10 +579,10 @@
* @}
*/
-#if defined (RTC_TAMPCR_TAMP1E)
/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
* @{
*/
+#if defined (RTC_TAMPCR_TAMP1E)
#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
#endif /* RTC_TAMPCR_TAMP1E */
#if defined (RTC_TAMPCR_TAMP2E)
@@ -595,10 +595,10 @@
* @}
*/
-#if defined (RTC_TAMPCR_TAMP1E)
/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
* @{
*/
+#if defined (RTC_TAMPCR_TAMP1E)
#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
#endif /* RTC_TAMPCR_TAMP1E */
#if defined (RTC_TAMPCR_TAMP2E)
@@ -654,10 +654,10 @@
*/
#endif /* RTC_TAMPCR_TAMPFREQ */
-#if defined (RTC_TAMPCR_TAMP1E)
/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
* @{
*/
+#if defined (RTC_TAMPCR_TAMP1E)
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
#endif /* RTC_TAMPCR_TAMP1E */
#if defined (RTC_TAMPCR_TAMP2E)
@@ -670,10 +670,10 @@
* @}
*/
-#if defined(TAMP_ATCR1_TAMP1AM)
/** @defgroup RTC_LL_EC_ACTIVE_MODE ACTIVE TAMPER MODE
* @{
*/
+#if defined(TAMP_ATCR1_TAMP1AM)
#define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM /*!< tamper 1 is active */
#endif /* TAMP_ATCR1_TAMP1AM */
#if defined(TAMP_ATCR1_TAMP2AM)
@@ -703,10 +703,10 @@
*/
#endif /* TAMP_ATCR1_ATCKSEL */
-#if defined(TAMP_ATCR1_TAMP1AM)
/** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION ACTIVE TAMPER OUTPUT SELECTION
* @{
*/
+#if defined(TAMP_ATCR1_TAMP1AM)
#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL1_Pos)
#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL1_Pos)
#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL1_Pos)
@@ -1601,7 +1601,7 @@
*/
__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
- register uint32_t temp;
+ uint32_t temp;
temp = Format12_24 | \
(((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
@@ -1629,7 +1629,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
{
- register uint32_t temp;
+ uint32_t temp;
temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
@@ -1931,7 +1931,7 @@
*/
__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
{
- register uint32_t temp;
+ uint32_t temp;
temp = (WeekDay << RTC_DR_WDU_Pos) | \
(((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
@@ -1959,7 +1959,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
{
- register uint32_t temp;
+ uint32_t temp;
temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
@@ -2259,7 +2259,7 @@
*/
__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
- register uint32_t temp;
+ uint32_t temp;
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
@@ -2625,7 +2625,7 @@
*/
__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
- register uint32_t temp;
+ uint32_t temp;
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
@@ -3716,7 +3716,7 @@
*/
__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
{
- register uint32_t tmp;
+ uint32_t tmp;
tmp = (uint32_t)(&(RTCx->BKP0R));
tmp += (BackupRegister * 4U);
@@ -3766,7 +3766,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
{
- register uint32_t tmp;
+ uint32_t tmp;
tmp = (uint32_t)(&(RTCx->BKP0R));
tmp += (BackupRegister * 4U);
@@ -3819,7 +3819,7 @@
*/
__STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data)
{
- register uint32_t tmp = 0U;
+ uint32_t tmp = 0U;
tmp = (uint32_t)(&(TAMPx->BKP0R));
tmp += (BackupRegister * 4U);
@@ -3869,7 +3869,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister)
{
- register uint32_t tmp = 0U;
+ uint32_t tmp = 0U;
tmp = (uint32_t)(&(TAMPx->BKP0R));
tmp += (BackupRegister * 4U);
diff --git a/Inc/stm32h7xx_ll_sdmmc.h b/Inc/stm32h7xx_ll_sdmmc.h
index efa6b0c..8b91c6c 100644
--- a/Inc/stm32h7xx_ll_sdmmc.h
+++ b/Inc/stm32h7xx_ll_sdmmc.h
@@ -1051,7 +1051,7 @@
uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
-uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType);
uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
@@ -1074,6 +1074,7 @@
* @}
*/
+
/**
* @}
*/
diff --git a/Inc/stm32h7xx_ll_spi.h b/Inc/stm32h7xx_ll_spi.h
index f050b17..e611b58 100644
--- a/Inc/stm32h7xx_ll_spi.h
+++ b/Inc/stm32h7xx_ll_spi.h
@@ -1285,8 +1285,8 @@
*/
__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
{
- register uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
- register uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
+ uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
+ uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
return (Hddir | Comm);
}
diff --git a/Inc/stm32h7xx_ll_system.h b/Inc/stm32h7xx_ll_system.h
index cd80788..df3fe3b 100644
--- a/Inc/stm32h7xx_ll_system.h
+++ b/Inc/stm32h7xx_ll_system.h
@@ -105,6 +105,9 @@
#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */
#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */
#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */
+#if defined(I2C5)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus for I2C5 */
+#endif /*I2C5*/
#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
@@ -116,7 +119,9 @@
/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
* @{
*/
+#if defined(SYSCFG_PMCR_BOOSTEN)
#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /*!< I/O analog switch voltage booster enable */
+#endif /*SYSCFG_PMCR_BOOSTEN*/
#define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< PA0 Switch Open */
#define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< PA1 Switch Open */
#define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< PC2 Switch Open */
@@ -147,7 +152,9 @@
#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
#define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
+#if defined(GPIOI)
#define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
+#endif /*GPIOI*/
#define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */
#define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */
/**
@@ -195,8 +202,10 @@
#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L /*!< Enables and locks the SRAM2 double ECC error signal
with Break Input of TIM1/8/15/16/17 and HRTIM */
+#if defined(SYSCFG_CFGR_SRAM3L)
#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L /*!< Enables and locks the SRAM3 double ECC error signal
with Break Input of TIM1/8/15/16/17 and HRTIM */
+#endif /*SYSCFG_CFGR_SRAM3L*/
#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L /*!< Enables and locks the SRAM4 double ECC error signal
with Break Input of TIM1/8/15/16/17 and HRTIM */
@@ -260,19 +269,45 @@
/**
* @}
*/
-#ifdef SYSCFG_PKGR_PKG
+#ifdef SYSCFG_UR17_TCM_AXI_CFG
/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
* @{
*/
+#define LL_SYSCFG_ITCM_AXI_64KB_320KB 0U
+#define LL_SYSCFG_ITCM_AXI_128KB_256KB 1U
+#define LL_SYSCFG_ITCM_AXI_192KB_192KB 2U
+#define LL_SYSCFG_ITCM_AXI_256KB_128KB 3U
+/**
+ * @}
+ */
+#endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */
+#if defined(SYSCFG_PKGR_PKG)
+/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
+ * @{
+ */
+#if (STM32H7_DEV_ID == 0x450UL)
#define LL_SYSCFG_LQFP100_PACKAGE 0U
#define LL_SYSCFG_TQFP144_PACKAGE 2U
#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U
#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U
+#elif (STM32H7_DEV_ID == 0x483UL)
+#define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U
+#define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U
+#define LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U
+#define LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U
+#define LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U
+#define LL_SYSCFG_LQFP144_PACKAGE 5U
+#define LL_SYSCFG_UFBGA144_PACKAGE 6U
+#define LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U
+#define LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U
+#define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U
+#define LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U
+#endif /* STM32H7_DEV_ID == 0x450UL */
/**
* @}
*/
#endif /* SYSCFG_PKGR_PKG */
-
+
/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
* @{
*/
@@ -313,14 +348,26 @@
#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#if defined(I2C5)
+#define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5 /*!< I2C5 SMBUS timeout mode stopped when Core is halted */
+#endif /*I2C5*/
/**
* @}
*/
+
/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
* @{
*/
+#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /*!< FDCAN is frozen while the core is in debug mode */
+#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
+#if defined(TIM23)
+#define LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23 /*!< TIM23 is frozen while the core is in debug mode */
+#endif /*TIM23*/
+#if defined(TIM24)
+#define LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24 /*!< TIM24 is frozen while the core is in debug mode */
+#endif /*TIM24*/
/**
* @}
*/
@@ -333,7 +380,9 @@
#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 /*!< TIM15 counter stopped when core is halted */
#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 /*!< TIM16 counter stopped when core is halted */
#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 /*!< TIM17 counter stopped when core is halted */
+#if defined(HRTIM1)
#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM /*!< HRTIM counter stopped when core is halted */
+#endif /*HRTIM1*/
/**
* @}
*/
@@ -493,6 +542,7 @@
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5(*)
*
* (*) value not defined in all devices
* @retval None
@@ -515,6 +565,8 @@
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*)
+ *
* (*) value not defined in all devices
* @retval None
*/
@@ -538,7 +590,7 @@
* @arg @ref LL_SYSCFG_EXTI_PORTF
* @arg @ref LL_SYSCFG_EXTI_PORTG
* @arg @ref LL_SYSCFG_EXTI_PORTH
- * @arg @ref LL_SYSCFG_EXTI_PORTI
+ * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
* @arg @ref LL_SYSCFG_EXTI_PORTJ
* @arg @ref LL_SYSCFG_EXTI_PORTK
*
@@ -599,7 +651,7 @@
* @arg @ref LL_SYSCFG_EXTI_PORTF
* @arg @ref LL_SYSCFG_EXTI_PORTG
* @arg @ref LL_SYSCFG_EXTI_PORTH
- * @arg @ref LL_SYSCFG_EXTI_PORTI
+ * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
* @arg @ref LL_SYSCFG_EXTI_PORTJ
* @arg @ref LL_SYSCFG_EXTI_PORTK
* (*) value not defined in all devices
@@ -630,7 +682,7 @@
* @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
- * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
* @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
@@ -638,6 +690,7 @@
* @arg @ref LL_SYSCFG_TIMBREAK_PVD
* @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
* @retval None
+ * (*) value not defined in all devices
*/
__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
{
@@ -645,10 +698,14 @@
MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break);
-#elif defined (SYSCFG_CFGR_AXISRAML)
+#elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
SYSCFG_CFGR_PVDL, Break);
+#elif defined(SYSCFG_CFGR_AXISRAML)
+ MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
+ SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\
+ Break);
#else
MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\
SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
@@ -677,13 +734,14 @@
* @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
- * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
* @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
* @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_PVD
* @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
+ * (*) value not defined in all devices
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
{
@@ -692,11 +750,16 @@
SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L));
-#elif defined (SYSCFG_CFGR_AXISRAML)
+#elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
+#elif defined (SYSCFG_CFGR_AXISRAML)
+ return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
+ SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
+ SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
+ SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
#else
return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \
SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
@@ -1074,10 +1137,24 @@
* @brief Get the device package
* @rmtoll PKGR PKG LL_SYSCFG_GetPackage
* @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSCFG_LQFP100_PACKAGE
- * @arg @ref LL_SYSCFG_TQFP144_PACKAGE
- * @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE
- * @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE
+ * @arg @ref LL_SYSCFG_LQFP100_PACKAGE (*)
+ * @arg @ref LL_SYSCFG_TQFP144_PACKAGE (*)
+ * @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE (*)
+ * @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE (*)
+ * @arg @ref LL_SYSCFG_VFQFPN68_INDUS_PACKAGE (*)
+ * @arg @ref LL_SYSCFG_TFBGA100_LQFP100_PACKAGE (*)
+ * @arg @ref LL_SYSCFG_LQFP100_INDUS_PACKAGE (**)
+ * @arg @ref LL_SYSCFG_TFBGA100_INDUS_PACKAGE (**)
+ * @arg @ref LL_SYSCFG_WLCSP115_INDUS_PACKAGE (**)
+ * @arg @ref LL_SYSCFG_LQFP144_PACKAGE (**)
+ * @arg @ref LL_SYSCFG_UFBGA144_PACKAGE (**)
+ * @arg @ref LL_SYSCFG_LQFP144_INDUS_PACKAGE (**)
+ * @arg @ref LL_SYSCFG_UFBGA169_INDUS_PACKAGE (**)
+ * @arg @ref LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE (**)
+ * @arg @ref LL_SYSCFG_LQFP176_INDUS_PACKAGE (**)
+ *
+ * (*) : For stm32h74xxx and stm32h75xxx family lines.
+ * (**): For stm32h72xxx and stm32h73xxx family lines.
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
{
@@ -1098,6 +1175,7 @@
{
return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
}
+#ifdef SYSCFG_UR0_BKS
/**
* @brief Indicate if the Flash memory bank addresses are inverted or not
* @rmtoll UR0 BKS LL_SYSCFG_IsFLashBankAddressesSwaped
@@ -1107,6 +1185,7 @@
{
return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
}
+#endif /*SYSCFG_UR0_BKS*/
/**
* @brief Get the BOR Threshold Reset Level
@@ -1372,6 +1451,7 @@
return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
}
+#ifdef SYSCFG_UR8_MEPAD_BANK2
/**
* @brief Indicates if the flash protected area (Bank 2) is erased by a mass erase
* @rmtoll UR8 MEPAD_BANK2 LL_SYSCFG_IsFlashB2ProtectedAreaErasable
@@ -1391,7 +1471,9 @@
{
return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
}
+#endif /*SYSCFG_UR8_MEPAD_BANK2*/
+#ifdef SYSCFG_UR9_WRPN_BANK2
/**
* @brief Indicates if the sector 0 of the Flash memory bank 2 is write protected
* @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector0WriteProtected
@@ -1481,7 +1563,9 @@
{
return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
}
+#endif /*SYSCFG_UR9_WRPN_BANK2*/
+#ifdef SYSCFG_UR10_PAEND_BANK2
/**
* @brief Get the protected area end address for Flash bank 2
* @rmtoll UR10 PAEND_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress
@@ -1501,7 +1585,9 @@
{
return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
}
+#endif /*SYSCFG_UR10_PAEND_BANK2*/
+#ifdef SYSCFG_UR11_SAEND_BANK2
/**
* @brief Get the secured area end address for Flash bank 2
* @rmtoll UR11 SAEND_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaEndAddress
@@ -1511,6 +1597,7 @@
{
return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
}
+#endif /*SYSCFG_UR11_SAEND_BANK2*/
/**
* @brief Get the Independent Watchdog 1 control mode (Software or Hardware)
@@ -1646,6 +1733,35 @@
{
return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
}
+
+#ifdef SYSCFG_UR17_TCM_AXI_CFG
+/**
+ * @brief Get the size of ITCM-RAM and AXI-SRAM
+ * @rmtoll UR17 TCM_AXI_CFG LL_SYSCFG_Get_ITCM_AXI_RAM_Size
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_ITCM_AXI_64KB_320KB
+ * @arg @ref LL_SYSCFG_ITCM_AXI_128KB_256KB
+ * @arg @ref LL_SYSCFG_ITCM_AXI_192KB_192KB
+ * @arg @ref LL_SYSCFG_ITCM_AXI_256KB_128KB
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG));
+}
+#endif /*SYSCFG_UR17_TCM_AXI_CFG*/
+
+#ifdef SYSCFG_UR18_CPU_FREQ_BOOST
+/**
+ * @brief Indicates if the CPU maximum frequency boost is enabled
+ * @rmtoll UR18 CPU_FREQ_BOOST LL_SYSCFG_IsCpuFreqBoostEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void)
+{
+ return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL);
+}
+#endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/
+
#endif /*SYSCFG_UR0_RDP*/
/**
@@ -1943,6 +2059,7 @@
* DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n (*)
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
@@ -1957,6 +2074,9 @@
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
+ *
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
@@ -1979,6 +2099,7 @@
* DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
@@ -1993,6 +2114,9 @@
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
+ *
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
@@ -2000,6 +2124,7 @@
CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
}
+#ifdef DBGMCU_APB1HFZ1_DBG_FDCAN
/**
* @brief Freeze APB1 group2 peripherals
* @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph\n
@@ -2023,6 +2148,37 @@
{
CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
}
+#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
+
+#if defined(TIM23) || defined(TIM24)
+/**
+ * @brief Freeze APB1 group2 peripherals
+ * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_FreezePeriph\n
+ * DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_FreezePeriph\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 group2 peripherals
+ * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
+ DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+#endif /* TIM23 || TIM24 */
/**
* @brief Freeze APB2 peripherals
@@ -2038,7 +2194,9 @@
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
+ *
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
@@ -2060,7 +2218,9 @@
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
+ *
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
@@ -2105,10 +2265,12 @@
* @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
- * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
- * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
+ * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
* @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
* @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
+ *
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
@@ -2129,10 +2291,12 @@
* @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
- * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
- * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
+ * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
* @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
* @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
+ *
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
diff --git a/Inc/stm32h7xx_ll_tim.h b/Inc/stm32h7xx_ll_tim.h
index 728c423..3bbdaa1 100644
--- a/Inc/stm32h7xx_ll_tim.h
+++ b/Inc/stm32h7xx_ll_tim.h
@@ -32,7 +32,7 @@
* @{
*/
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
/** @defgroup TIM_LL TIM
* @{
@@ -576,8 +576,8 @@
*/
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
-#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
/**
* @}
@@ -1241,6 +1241,9 @@
#define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */
#define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */
#define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */
+/**
+ * @}
+ */
#if defined(TIM_BREAK_INPUT_SUPPORT)
/** Legacy definitions for compatibility purpose
@@ -2016,8 +2019,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
@@ -2061,8 +2064,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
@@ -2100,8 +2103,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@@ -2134,7 +2137,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2166,7 +2169,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}
@@ -2203,7 +2206,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
}
@@ -2235,7 +2238,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}
@@ -2260,8 +2263,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2286,8 +2289,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2312,9 +2315,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2338,8 +2341,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2363,8 +2366,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2388,9 +2391,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2417,8 +2420,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2444,8 +2447,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2473,9 +2476,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2744,8 +2747,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
@@ -2772,8 +2775,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2796,8 +2799,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2822,8 +2825,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2847,8 +2850,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2885,8 +2888,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2922,8 +2925,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2951,7 +2954,7 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2979,7 +2982,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
SHIFT_TAB_CCxP[iChannel]);
}
@@ -3692,7 +3695,7 @@
*/
__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
SET_BIT(*pReg, Source);
}
@@ -3721,7 +3724,7 @@
*/
__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
CLEAR_BIT(*pReg, Source);
}
@@ -3751,7 +3754,7 @@
__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
uint32_t Polarity)
{
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
}
#endif /* TIM_BREAK_INPUT_SUPPORT */
@@ -4915,7 +4918,7 @@
* @}
*/
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 */
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 || TIM23 || TIM24 */
/**
* @}
diff --git a/Inc/stm32h7xx_ll_usart.h b/Inc/stm32h7xx_ll_usart.h
index e090a1e..7b4121e 100644
--- a/Inc/stm32h7xx_ll_usart.h
+++ b/Inc/stm32h7xx_ll_usart.h
@@ -645,7 +645,7 @@
/**
* @brief FIFO Mode Enable
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_EnableFIFO
* @param USARTx USART Instance
@@ -658,7 +658,7 @@
/**
* @brief FIFO Mode Disable
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_DisableFIFO
* @param USARTx USART Instance
@@ -671,7 +671,7 @@
/**
* @brief Indicate if FIFO Mode is enabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO
* @param USARTx USART Instance
@@ -684,7 +684,7 @@
/**
* @brief Configure TX FIFO Threshold
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
* @param USARTx USART Instance
@@ -704,7 +704,7 @@
/**
* @brief Return TX FIFO Threshold Configuration
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
* @param USARTx USART Instance
@@ -723,7 +723,7 @@
/**
* @brief Configure RX FIFO Threshold
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
* @param USARTx USART Instance
@@ -743,7 +743,7 @@
/**
* @brief Return RX FIFO Threshold Configuration
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
* @param USARTx USART Instance
@@ -762,7 +762,7 @@
/**
* @brief Configure TX and RX FIFOs Threshold
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n
* CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
@@ -792,7 +792,7 @@
* @brief USART enabled in STOP Mode.
* @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
* USART clock selection is HSI or LSE in RCC.
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_EnableInStopMode
* @param USARTx USART Instance
@@ -806,7 +806,7 @@
/**
* @brief USART disabled in STOP Mode.
* @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_DisableInStopMode
* @param USARTx USART Instance
@@ -819,7 +819,7 @@
/**
* @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
* @param USARTx USART Instance
@@ -1062,7 +1062,7 @@
/**
* @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
* @param USARTx USART Instance
@@ -1079,7 +1079,7 @@
/**
* @brief Retrieve Clock pulse of the last data bit output configuration
* (Last bit Clock pulse output to the SCLK pin or not)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
* @param USARTx USART Instance
@@ -1094,7 +1094,7 @@
/**
* @brief Select the phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_SetClockPhase
* @param USARTx USART Instance
@@ -1110,7 +1110,7 @@
/**
* @brief Return phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_GetClockPhase
* @param USARTx USART Instance
@@ -1125,7 +1125,7 @@
/**
* @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_SetClockPolarity
* @param USARTx USART Instance
@@ -1141,7 +1141,7 @@
/**
* @brief Return polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_GetClockPolarity
* @param USARTx USART Instance
@@ -1156,7 +1156,7 @@
/**
* @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
@@ -1184,7 +1184,7 @@
/**
* @brief Configure Clock source prescaler for baudrate generator and oversampling
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll PRESC PRESCALER LL_USART_SetPrescaler
* @param USARTx USART Instance
@@ -1210,7 +1210,7 @@
/**
* @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll PRESC PRESCALER LL_USART_GetPrescaler
* @param USARTx USART Instance
@@ -1235,7 +1235,7 @@
/**
* @brief Enable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
* @param USARTx USART Instance
@@ -1248,7 +1248,7 @@
/**
* @brief Disable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
* @param USARTx USART Instance
@@ -1261,7 +1261,7 @@
/**
* @brief Indicate if Clock output on SCLK pin is enabled
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
* @param USARTx USART Instance
@@ -1480,7 +1480,7 @@
/**
* @brief Enable Auto Baud-Rate Detection
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
* @param USARTx USART Instance
@@ -1493,7 +1493,7 @@
/**
* @brief Disable Auto Baud-Rate Detection
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
* @param USARTx USART Instance
@@ -1506,7 +1506,7 @@
/**
* @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
* @param USARTx USART Instance
@@ -1519,7 +1519,7 @@
/**
* @brief Set Auto Baud-Rate mode bits
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
* @param USARTx USART Instance
@@ -1537,7 +1537,7 @@
/**
* @brief Return Auto Baud-Rate mode
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
* @param USARTx USART Instance
@@ -1644,7 +1644,7 @@
/**
* @brief Enable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1657,7 +1657,7 @@
/**
* @brief Disable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1670,7 +1670,7 @@
/**
* @brief Enable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1683,7 +1683,7 @@
/**
* @brief Disable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1696,7 +1696,7 @@
/**
* @brief Configure HW Flow Control mode (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
* CR3 CTSE LL_USART_SetHWFlowCtrl
@@ -1715,7 +1715,7 @@
/**
* @brief Return HW Flow Control configuration (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
* CR3 CTSE LL_USART_GetHWFlowCtrl
@@ -1799,7 +1799,7 @@
/**
* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_SetWKUPType
* @param USARTx USART Instance
@@ -1816,7 +1816,7 @@
/**
* @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_GetWKUPType
* @param USARTx USART Instance
@@ -1864,7 +1864,7 @@
uint32_t BaudRate)
{
uint32_t usartdiv;
- register uint32_t brrtemp;
+ uint32_t brrtemp;
if (PrescalerValue > LL_USART_PRESCALER_DIV256)
{
@@ -1912,9 +1912,9 @@
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling)
{
- register uint32_t usartdiv;
- register uint32_t brrresult = 0x0U;
- register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+ uint32_t usartdiv;
+ uint32_t brrresult = 0x0U;
+ uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
usartdiv = USARTx->BRR;
@@ -1996,7 +1996,7 @@
/**
* @brief Enable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_EnableIrda
* @param USARTx USART Instance
@@ -2009,7 +2009,7 @@
/**
* @brief Disable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_DisableIrda
* @param USARTx USART Instance
@@ -2022,7 +2022,7 @@
/**
* @brief Indicate if IrDA mode is enabled
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_IsEnabledIrda
* @param USARTx USART Instance
@@ -2035,7 +2035,7 @@
/**
* @brief Configure IrDA Power Mode (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
* @param USARTx USART Instance
@@ -2051,7 +2051,7 @@
/**
* @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
* @param USARTx USART Instance
@@ -2067,7 +2067,7 @@
/**
* @brief Set Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
* @param USARTx USART Instance
@@ -2082,7 +2082,7 @@
/**
* @brief Return Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
* @param USARTx USART Instance
@@ -2103,7 +2103,7 @@
/**
* @brief Enable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
* @param USARTx USART Instance
@@ -2116,7 +2116,7 @@
/**
* @brief Disable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
* @param USARTx USART Instance
@@ -2129,7 +2129,7 @@
/**
* @brief Indicate if Smartcard NACK transmission is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
* @param USARTx USART Instance
@@ -2142,7 +2142,7 @@
/**
* @brief Enable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_EnableSmartcard
* @param USARTx USART Instance
@@ -2155,7 +2155,7 @@
/**
* @brief Disable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_DisableSmartcard
* @param USARTx USART Instance
@@ -2168,7 +2168,7 @@
/**
* @brief Indicate if Smartcard mode is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
* @param USARTx USART Instance
@@ -2181,7 +2181,7 @@
/**
* @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
* In transmission mode, it specifies the number of automatic retransmission retries, before
@@ -2200,7 +2200,7 @@
/**
* @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
* @param USARTx USART Instance
@@ -2214,7 +2214,7 @@
/**
* @brief Set Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
* @param USARTx USART Instance
@@ -2229,7 +2229,7 @@
/**
* @brief Return Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
* @param USARTx USART Instance
@@ -2243,7 +2243,7 @@
/**
* @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
* @param USARTx USART Instance
@@ -2258,7 +2258,7 @@
/**
* @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
* @param USARTx USART Instance
@@ -2279,7 +2279,7 @@
/**
* @brief Enable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
* @param USARTx USART Instance
@@ -2292,7 +2292,7 @@
/**
* @brief Disable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
* @param USARTx USART Instance
@@ -2305,7 +2305,7 @@
/**
* @brief Indicate if Single Wire Half-Duplex mode is enabled
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
* @param USARTx USART Instance
@@ -2325,7 +2325,7 @@
*/
/**
* @brief Enable SPI Synchronous Slave mode
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_EnableSPISlave
* @param USARTx USART Instance
@@ -2338,7 +2338,7 @@
/**
* @brief Disable SPI Synchronous Slave mode
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_DisableSPISlave
* @param USARTx USART Instance
@@ -2351,7 +2351,7 @@
/**
* @brief Indicate if SPI Synchronous Slave mode is enabled
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave
* @param USARTx USART Instance
@@ -2364,7 +2364,7 @@
/**
* @brief Enable SPI Slave Selection using NSS input pin
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @note SPI Slave Selection depends on NSS input pin
* (The slave is selected when NSS is low and deselected when NSS is high).
@@ -2379,7 +2379,7 @@
/**
* @brief Disable SPI Slave Selection using NSS input pin
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @note SPI Slave will be always selected and NSS input pin will be ignored.
* @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
@@ -2393,7 +2393,7 @@
/**
* @brief Indicate if SPI Slave Selection depends on NSS input pin
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
* @param USARTx USART Instance
@@ -2414,7 +2414,7 @@
/**
* @brief Set LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
* @param USARTx USART Instance
@@ -2430,7 +2430,7 @@
/**
* @brief Return LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
* @param USARTx USART Instance
@@ -2445,7 +2445,7 @@
/**
* @brief Enable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_EnableLIN
* @param USARTx USART Instance
@@ -2458,7 +2458,7 @@
/**
* @brief Disable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_DisableLIN
* @param USARTx USART Instance
@@ -2471,7 +2471,7 @@
/**
* @brief Indicate if LIN mode is enabled
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
* @param USARTx USART Instance
@@ -2492,7 +2492,7 @@
/**
* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
* @param USARTx USART Instance
@@ -2506,7 +2506,7 @@
/**
* @brief Return DEDT (Driver Enable De-Assertion Time)
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
* @param USARTx USART Instance
@@ -2519,7 +2519,7 @@
/**
* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
* @param USARTx USART Instance
@@ -2533,7 +2533,7 @@
/**
* @brief Return DEAT (Driver Enable Assertion Time)
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
* @param USARTx USART Instance
@@ -2546,7 +2546,7 @@
/**
* @brief Enable Driver Enable (DE) Mode
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_EnableDEMode
* @param USARTx USART Instance
@@ -2559,7 +2559,7 @@
/**
* @brief Disable Driver Enable (DE) Mode
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_DisableDEMode
* @param USARTx USART Instance
@@ -2572,7 +2572,7 @@
/**
* @brief Indicate if Driver Enable (DE) Mode is enabled
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
* @param USARTx USART Instance
@@ -2585,7 +2585,7 @@
/**
* @brief Select Driver Enable Polarity
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
* @param USARTx USART Instance
@@ -2601,7 +2601,7 @@
/**
* @brief Return Driver Enable Polarity
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
* @param USARTx USART Instance
@@ -2665,7 +2665,7 @@
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the USART in Synchronous mode.
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2704,7 +2704,7 @@
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also set the UART/USART in LIN mode.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
@@ -2745,7 +2745,7 @@
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* This function also sets the UART/USART in Half Duplex mode.
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2785,7 +2785,7 @@
* This function also configures Stop bits to 1.5 bits and
* sets the USART in Smartcard mode (SCEN bit).
* Clock Output is also enabled (CLKEN).
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2828,7 +2828,7 @@
* - SCEN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the UART/USART in IRDA mode (IREN bit).
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2966,7 +2966,7 @@
/**
* @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
* @param USARTx USART Instance
@@ -2993,7 +2993,7 @@
/**
* @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
* @param USARTx USART Instance
@@ -3006,7 +3006,7 @@
/**
* @brief Check if the USART LIN Break Detection Flag is set or not
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
* @param USARTx USART Instance
@@ -3019,7 +3019,7 @@
/**
* @brief Check if the USART CTS interrupt Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
* @param USARTx USART Instance
@@ -3032,7 +3032,7 @@
/**
* @brief Check if the USART CTS Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
* @param USARTx USART Instance
@@ -3056,7 +3056,7 @@
/**
* @brief Check if the USART End Of Block Flag is set or not
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
* @param USARTx USART Instance
@@ -3069,7 +3069,7 @@
/**
* @brief Check if the SPI Slave Underrun error flag is set or not
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR
* @param USARTx USART Instance
@@ -3082,7 +3082,7 @@
/**
* @brief Check if the USART Auto-Baud Rate Error Flag is set or not
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
* @param USARTx USART Instance
@@ -3095,7 +3095,7 @@
/**
* @brief Check if the USART Auto-Baud Rate Flag is set or not
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
* @param USARTx USART Instance
@@ -3152,7 +3152,7 @@
/**
* @brief Check if the USART Wake Up from stop mode Flag is set or not
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
* @param USARTx USART Instance
@@ -3187,7 +3187,7 @@
/**
* @brief Check if the USART TX FIFO Empty Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE
* @param USARTx USART Instance
@@ -3200,7 +3200,7 @@
/**
* @brief Check if the USART RX FIFO Full Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF
* @param USARTx USART Instance
@@ -3224,7 +3224,7 @@
/**
* @brief Check if the USART TX FIFO Threshold Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT
* @param USARTx USART Instance
@@ -3237,7 +3237,7 @@
/**
* @brief Check if the USART RX FIFO Threshold Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT
* @param USARTx USART Instance
@@ -3305,7 +3305,7 @@
/**
* @brief Clear TX FIFO Empty Flag
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE
* @param USARTx USART Instance
@@ -3340,7 +3340,7 @@
/**
* @brief Clear LIN Break Detection Flag
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
* @param USARTx USART Instance
@@ -3353,7 +3353,7 @@
/**
* @brief Clear CTS Interrupt Flag
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
* @param USARTx USART Instance
@@ -3377,7 +3377,7 @@
/**
* @brief Clear End Of Block Flag
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
* @param USARTx USART Instance
@@ -3390,7 +3390,7 @@
/**
* @brief Clear SPI Slave Underrun Flag
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR
* @param USARTx USART Instance
@@ -3414,7 +3414,7 @@
/**
* @brief Clear Wake Up from stop mode Flag
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
* @param USARTx USART Instance
@@ -3449,7 +3449,7 @@
/**
* @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
* @param USARTx USART Instance
@@ -3476,7 +3476,7 @@
/**
* @brief Enable TX Empty and TX FIFO Not Full Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
* @param USARTx USART Instance
@@ -3522,7 +3522,7 @@
/**
* @brief Enable End Of Block Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
* @param USARTx USART Instance
@@ -3535,7 +3535,7 @@
/**
* @brief Enable TX FIFO Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE
* @param USARTx USART Instance
@@ -3559,7 +3559,7 @@
/**
* @brief Enable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
* @param USARTx USART Instance
@@ -3587,7 +3587,7 @@
/**
* @brief Enable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
* @param USARTx USART Instance
@@ -3600,7 +3600,7 @@
/**
* @brief Enable Wake Up from Stop Mode Interrupt
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
* @param USARTx USART Instance
@@ -3613,7 +3613,7 @@
/**
* @brief Enable TX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT
* @param USARTx USART Instance
@@ -3626,7 +3626,7 @@
/**
* @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT
* @param USARTx USART Instance
@@ -3639,7 +3639,7 @@
/**
* @brief Enable RX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT
* @param USARTx USART Instance
@@ -3666,7 +3666,7 @@
/**
* @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
* @param USARTx USART Instance
@@ -3693,7 +3693,7 @@
/**
* @brief Disable TX Empty and TX FIFO Not Full Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
* @param USARTx USART Instance
@@ -3739,7 +3739,7 @@
/**
* @brief Disable End Of Block Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
* @param USARTx USART Instance
@@ -3752,7 +3752,7 @@
/**
* @brief Disable TX FIFO Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE
* @param USARTx USART Instance
@@ -3765,7 +3765,7 @@
/**
* @brief Disable RX FIFO Full Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF
* @param USARTx USART Instance
@@ -3778,7 +3778,7 @@
/**
* @brief Disable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
* @param USARTx USART Instance
@@ -3806,7 +3806,7 @@
/**
* @brief Disable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
* @param USARTx USART Instance
@@ -3819,7 +3819,7 @@
/**
* @brief Disable Wake Up from Stop Mode Interrupt
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
* @param USARTx USART Instance
@@ -3832,7 +3832,7 @@
/**
* @brief Disable TX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT
* @param USARTx USART Instance
@@ -3845,7 +3845,7 @@
/**
* @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT
* @param USARTx USART Instance
@@ -3858,7 +3858,7 @@
/**
* @brief Disable RX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT
* @param USARTx USART Instance
@@ -3885,7 +3885,7 @@
/**
* @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
* @param USARTx USART Instance
@@ -3912,7 +3912,7 @@
/**
* @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
* @param USARTx USART Instance
@@ -3958,7 +3958,7 @@
/**
* @brief Check if the USART End Of Block Interrupt is enabled or disabled.
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
* @param USARTx USART Instance
@@ -3971,7 +3971,7 @@
/**
* @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
* @param USARTx USART Instance
@@ -3984,7 +3984,7 @@
/**
* @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
* @param USARTx USART Instance
@@ -3997,7 +3997,7 @@
/**
* @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
* @param USARTx USART Instance
@@ -4021,7 +4021,7 @@
/**
* @brief Check if the USART CTS Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
* @param USARTx USART Instance
@@ -4034,7 +4034,7 @@
/**
* @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
* @param USARTx USART Instance
@@ -4047,7 +4047,7 @@
/**
* @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
* @param USARTx USART Instance
@@ -4060,7 +4060,7 @@
/**
* @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
* @param USARTx USART Instance
@@ -4073,7 +4073,7 @@
/**
* @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
* @param USARTx USART Instance
@@ -4203,7 +4203,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
{
- register uint32_t data_reg_addr;
+ uint32_t data_reg_addr;
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{
@@ -4283,7 +4283,7 @@
/**
* @brief Request an Automatic Baud Rate measurement on next received data frame
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
* @param USARTx USART Instance
@@ -4318,7 +4318,7 @@
/**
* @brief Request a Receive Data and FIFO flush
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @note Allows to discard the received data without reading them, and avoid an overrun
* condition.
@@ -4333,7 +4333,7 @@
/**
* @brief Request a Transmit data and FIFO flush
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
* @param USARTx USART Instance
diff --git a/Inc/stm32h7xx_ll_usb.h b/Inc/stm32h7xx_ll_usb.h
index 99b5725..8970cfb 100644
--- a/Inc/stm32h7xx_ll_usb.h
+++ b/Inc/stm32h7xx_ll_usb.h
@@ -155,7 +155,7 @@
typedef struct
{
- uint8_t dev_addr ; /*!< USB device address.
+ uint8_t dev_addr; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
@@ -199,10 +199,10 @@
uint32_t ErrCnt; /*!< Host channel error count.*/
- USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
+ USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
- USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
+ USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@@ -237,11 +237,11 @@
/** @defgroup USB_LL Device Speed
* @{
*/
-#define USBD_HS_SPEED 0U
-#define USBD_HSINFS_SPEED 1U
-#define USBH_HS_SPEED 0U
-#define USBD_FS_SPEED 2U
-#define USBH_FS_SPEED 1U
+#define USBD_HS_SPEED 0U
+#define USBD_HSINFS_SPEED 1U
+#define USBH_HS_SPEED 0U
+#define USBD_FS_SPEED 2U
+#define USBH_FSLS_SPEED 1U
/**
* @}
*/
@@ -269,11 +269,11 @@
* @{
*/
#ifndef USBD_HS_TRDT_VALUE
-#define USBD_HS_TRDT_VALUE 9U
+#define USBD_HS_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
#ifndef USBD_FS_TRDT_VALUE
-#define USBD_FS_TRDT_VALUE 5U
-#define USBD_DEFAULT_TRDT_VALUE 9U
+#define USBD_FS_TRDT_VALUE 5U
+#define USBD_DEFAULT_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
@@ -282,9 +282,9 @@
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
-#define USB_OTG_HS_MAX_PACKET_SIZE 512U
-#define USB_OTG_FS_MAX_PACKET_SIZE 64U
-#define USB_OTG_MAX_EP0_SIZE 64U
+#define USB_OTG_HS_MAX_PACKET_SIZE 512U
+#define USB_OTG_FS_MAX_PACKET_SIZE 64U
+#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
@@ -402,7 +402,7 @@
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-#define EP_ADDR_MSK 0xFU
+#define EP_ADDR_MSK 0xFU
/**
* @}
*/
@@ -467,13 +467,9 @@
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address, uint8_t speed,
+ uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
diff --git a/Inc/stm32h7xx_ll_utils.h b/Inc/stm32h7xx_ll_utils.h
index 3dc60e7..2833148 100644
--- a/Inc/stm32h7xx_ll_utils.h
+++ b/Inc/stm32h7xx_ll_utils.h
@@ -199,12 +199,12 @@
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
* @{
*/
-#if defined(SYSCFG_PKGR_PKG)
+#if (STM32H7_DEV_ID == 0x450UL)
#define LL_UTILS_PACKAGETYPE_LQFP100 LL_SYSCFG_LQFP100_PACKAGE /*!< LQFP100 package type */
#define LL_UTILS_PACKAGETYPE_TQFP144 LL_SYSCFG_TQFP144_PACKAGE /*!< TQFP144 package type */
#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */
#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */
-#else
+#elif (STM32H7_DEV_ID == 0x480UL)
#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000UL /*!< LQFP64 package type */
#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 0x00000001UL /*!< TFBGA100 or LQFP100 package type */
#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x00000002UL /*!< LQFP100 with SMPS package type */
@@ -218,7 +218,19 @@
#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000AUL /*!< UFBGA176 with SMPS package type */
#define LL_UTILS_PACKAGETYPE_TFBGA216 0x0000000CUL /*!< TFBGA216 package type */
#define LL_UTILS_PACKAGETYPE_TFBGA225 0x0000000EUL /*!< TFBGA225 package type */
-#endif /* SYSCFG_PKGR_PKG */
+#elif (STM32H7_DEV_ID == 0x483UL)
+#define LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS LL_SYSCFG_VFQFPN68_INDUS_PACKAGE /*!< VFQFPN68 Industrial package type */
+#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 LL_SYSCFG_TFBGA100_LQFP100_PACKAGE /*!< TFBGA100 or LQFP100 Legacy package type */
+#define LL_UTILS_PACKAGETYPE_LQFP100_INDUS LL_SYSCFG_LQFP100_INDUS_PACKAGE /*!< LQFP100 Industrial package type */
+#define LL_UTILS_PACKAGETYPE_TFBGA100_INDUS LL_SYSCFG_TFBGA100_INDUS_PACKAGE /*!< TFBGA100 Industrial package type */
+#define LL_UTILS_PACKAGETYPE_WLCSP115_INDUS LL_SYSCFG_WLCSP115_INDUS_PACKAGE /*!< WLCSP115 Industrial package type */
+#define LL_UTILS_PACKAGETYPE_LQFP144 LL_SYSCFG_LQFP144_PACKAGE /*!< LQFP144 Legacy package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA144 LL_SYSCFG_UFBGA144_PACKAGE /*!< UFBGA144 Legacy package type */
+#define LL_UTILS_PACKAGETYPE_LQFP144_INDUS LL_SYSCFG_LQFP144_INDUS_PACKAGE /*!< LQFP144 Industrial package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA169_INDUS LL_SYSCFG_UFBGA169_INDUS_PACKAGE /*!< UFBGA169 Industrial package type */
+#define LL_UTILS_PACKAGETYPE_UFBGA176PLUS25_INDUS LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE /*!< UFBGA176+25 Industrial package type */
+#define LL_UTILS_PACKAGETYPE_LQFP176_INDUS LL_SYSCFG_LQFP176_INDUS_PACKAGE /*!< LQFP176 Industrial package type */
+#endif /* STM32H7_DEV_ID == 0x450UL */
/**
* @}
*/
@@ -296,6 +308,15 @@
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS (*)
* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_INDUS (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_INDUS (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP115_INDUS (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_INDUS (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_INDUS (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176+25_INDUS (*)
+ * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_INDUS (*)
*
* (*) Packages available on some STM32H7 lines only.
* @note For some SM32H7 lines, enabling the SYSCFG clock is mandatory.
diff --git a/License.md b/License.md
index d95c1db..f8a5385 100644
--- a/License.md
+++ b/License.md
@@ -1,3 +1,3 @@
# Copyright (c) 2017 STMicroelectronics
-This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
+This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
\ No newline at end of file
diff --git a/README.md b/README.md
index 1003ec6..3e4253b 100644
--- a/README.md
+++ b/README.md
@@ -38,9 +38,10 @@
HAL Driver H7 | CMSIS Device H7 | CMSIS Core | Was delivered in the full MCU package
------------- | --------------- | ---------- | -------------------------------------
-Tag v1.6.0 | Tag v1.6.0 | Tag v5.4.0 | Tag v1.5.0 (and following, if any, till next HAL tag)
-Tag v1.7.0 | Tag v1.7.0 | Tag v5.4.0 | Tag v1.6.0 (and following, if any, till next HAL tag)
-Tag v1.8.0 | Tag v1.8.0 | Tag v5.4.0 | Tag v1.7.0 (and following, if any, till next HAL tag)
+Tag v1.6.0 | Tag v1.6.0 | Tag v5.4.0 | Tag v1.5.0 (and following, if any, till next HAL tag)
+Tag v1.7.0 | Tag v1.7.0 | Tag v5.4.0 | Tag v1.6.0 (and following, if any, till next HAL tag)
+Tag v1.8.0 | Tag v1.8.0 | Tag v5.4.0 | Tag v1.7.0 (and following, if any, till next HAL tag)
+Tag v1.9.0 | Tag v1.9.0 | Tag v5.4.0 | Tag v1.8.0 (and following, if any, till next HAL tag)
The full **STM32CubeH7** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH7).
diff --git a/Release_Notes.html b/Release_Notes.html
index 37472cb..f4ede52 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -38,10 +38,617 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section9" checked aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
+<input type="checkbox" id="collapse-section12" checked aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
+<li>First official release of the STM32CubeH7 Firmware Package supporting <strong>STM32H72x/3x</strong> new devices</li>
+<li>General updates to fix known defects and implementation enhancements</li>
+<li><strong>HAL</strong>: generic, Update to support <strong>STM32H72x/3x</strong> new devices
+<ul>
+<li>stm32h7xx_hal.h:
+<ul>
+<li>Add SYSCGF defines for Adc2 Alternate Connection on Vinp[16] and Vinp[17]</li>
+<li>Add HAL_SYSCFG_ADC2ALT_Rout0Config and HAL_SYSCFG_ADC2ALT_Rout1Config APIs allowing to configure Adc2 Alternate Connection on Vinp[16] or Vinp[17]<br />
+</li>
+<li>Update EXTI lines definitions for <strong>STM32H72x/3x</strong> devices</li>
+<li>Add __HAL_DBGMCU_FREEZE_I2C5/__HAL_DBGMCU_UnFreeze_I2C5, __HAL_DBGMCU_FREEZE_TIM23/__HAL_DBGMCU_UnFreeze_TIM23 and __HAL_DBGMCU_FREEZE_TIM24/__HAL_DBGMCU_UnFreeze_TIM24 macros</li>
+</ul></li>
+<li>stm32h7xx_hal_conf_template.h:
+<ul>
+<li>Add CORDIC and FMAC modules enabling (new peripherals in STM32H723xx/33xx/25xx/35xx/30xx devices)</li>
+<li>Add CORDIC and FMAC register callback enabling</li>
+</ul></li>
+<li>stm32h7xx_hal.c:
+<ul>
+<li>Add implementation of HAL_SYSCFG_ADC2ALT_Rout0Config and HAL_SYSCFG_ADC2ALT_Rout1Config APIs implementation allowing to configure Adc2 Alternate Connection on Vinp[16] or Vinp[17]</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL ADC</strong>: Updated to support <strong>STM32H72x/3x</strong> devices: ADC1/2 (16 bits ADCs in D2 domain) and ADC3 (12 Bits ADC in D3 domain)
+<ul>
+<li>3 compilations defines are used:
+<ul>
+<li>ADC_VER_V5_V90 : for <strong>STM32H72x/3x</strong> ADCs : ADC1/2 (16 bits ADCs in D2 domain) and ADC3 (12 Bits ADC in D3 domain)</li>
+<li>ADC_VER_V5_3: For STM32H7Ax/Bx : ADC1/2 (16 bits ADCs in D2/CDC domain)</li>
+<li>ADC_VER_V5_X: For STM32H74x/5x : ADC1/2 (16 bits ADCs in D2/CDC domain) and ADC3 (16 Bits ADC in D3 domain)
+<ul>
+<li>supporting rev.Y and rev.V devices</li>
+</ul></li>
+<li>These defines are available on each CMSIS device header file stm32h723xx.h/stm32h733xx.h …/STM32H7a3xx.h/STM32H7b3xx.h/…/stm32h743xx/stm32h773xx…</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL DFSDM</strong>:
+<ul>
+<li>stm32h7xx_hal_dfsdm.h:
+<ul>
+<li>Use conditional define on STM32H7_DEV_ID for external triggers definition instead of device RPN definitions (STM32H7_DEV_ID define available on CMSIS device header files for each STM32H7 line : <strong>STM32H72x/3x</strong>/4x/5x/Ax/Bx)</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL DMA</strong>:
+<ul>
+<li>stm32h7xx_ll_bdma.h, stm32h7xx_ll_dma.h and stm32h7xx_ll_dmamux.h:
+<ul>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+<li>Add requests definitions for FMAC, CORDIC, I2C5, TIM23 and TIM24 new peripherals available on <strong>STM32H72x/3x</strong> devices</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL CORDIC</strong>:
+<ul>
+<li>New HAL and LL drivers to support CORDIC peripheral available on new <strong>STM32H72x/3x</strong> new devices</li>
+</ul></li>
+<li><strong>HAL CRYP</strong>:
+<ul>
+<li>stm32h7xx_hal_cryp.c/.h and stm32h7xx_hal_cryp_ex.c: Update doxygen documentation</li>
+</ul></li>
+<li><strong>HAL DCMI</strong>:
+<ul>
+<li>stm32h7xx_hal_dcmi.c:
+<ul>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL ETH</strong>:
+<ul>
+<li>stm32h7xx_hal_eth.h:
+<ul>
+<li><p>Update ETH_DMADescTypeDef definition: remove useless volatile of the BackupAddr0 and BackupAddr1 fields since they are not used by ETH DMA.</p></li>
+<li>stm32h7xx_hal_eth.c:
+<ul>
+<li>HAL_ETH_Start_IT:
+<ul>
+<li>Move the update of the ETH gState and RxState after ETH IT Start.</li>
+<li>Remove useless INCR_RX_DESC_INDEX(descindex, 1U) when enabling Interrupt on Completion fields</li>
+</ul></li>
+<li>HAL_ETH_Stop_IT:
+<ul>
+<li>Clear Fatal bus interrupt and Abnormal Interrupt Summary Enable</li>
+<li>Clear interrupt Enabled on Completion for all used descriptors</li>
+</ul></li>
+<li>HAL_ETH_Transmit:
+<ul>
+<li>Set ETH gState to HAL_ETH_STATE_ERROR when timeout error occurred</li>
+<li>Remove unnecessary set of ETH HAL State to Ready</li>
+</ul></li>
+<li>HAL_ETH_Transmit_IT:
+<ul>
+<li>Set ETH ErrorCode to HAL_ETH_ERROR_PARAM when parameter is not valid and use logical OR when updating the ErrorCode</li>
+</ul></li>
+<li>HAL_ETH_IsRxDataAvailable
+<ul>
+<li>Updating the CurRxDesc and FirstAppDesc values when building descriptor of an invalid/incomplete</li>
+</ul></li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL EXTI</strong>: Updated to support <strong>STM32H72x/3x</strong> devices
+<ul>
+<li>stm32h7xx_hal_exti.h and stm32h7xx_ll_exti.h:
+<ul>
+<li>Update EXTI lines definition with according to its availability on STM32H74x/5x STM32Ax/Bx or <strong>STM32H72x/3x</strong> devices</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL FDCAN</strong>:
+<ul>
+<li>stm32h7xx_hal_fdcan.h:
+<ul>
+<li>Add guard on FDCAN1 peripheral availability on top of the header file</li>
+</ul></li>
+<li>stm32h7xx_hal_fdcan.c:
+<ul>
+<li>Add guard on FDCAN1 peripheral availability on top of the source file</li>
+<li>Add FDCAN_TIMEOUT_COUNT private define to be used when a timeout based on number of trials is needed</li>
+<li>Fix HAL_FDCAN_GetRxMessage function implementation to discard first message in FIFO when overwrite status is on</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL FLASH</strong>:
+<ul>
+<li>stm32h7xx_hal_flash.h:
+<ul>
+<li>Update to use DUAL_BANK define in macros __HAL_FLASH_ENABLE_IT, __HAL_FLASH_DISABLE_IT, __HAL_FLASH_GET_FLAG and __HAL_FLASH_CLEAR_FLAG:
+<ul>
+<li>Two different implementations depending of dual bank device (STM32H74x/5x/Ax/Bx) of single bank device (<strong>STM32H72x/3x</strong>/50/B0)</li>
+</ul></li>
+<li>Delimit Bank2 private macros with DUAL_BANK define<br />
+</li>
+<li>Add IS_FLASH_PROGRAM_ADDRESS_OTP and IS_FLASH_PROGRAM_ADDRESS private macros used within the Flash HAL driver for STM32H7Ax/Bx devices</li>
+</ul></li>
+<li>stm32h7xx_hal_flash_ex.h:
+<ul>
+<li>Update to support option bytes TCM_AXI_SHARED and CPUFREQ_BOOST available on <strong>STM32H72x/3x</strong> new devices</li>
+</ul></li>
+<li>stm32h7xx_hal_flash.c:
+<ul>
+<li>Update implementation to consider dual bank devices (STM32H74x/5x and STM32H7Ax/Bx) and single bank devices (<strong>STM32H72x/3x</strong>)</li>
+</ul></li>
+<li>stm32h7xx_hal_flash_ex.c:
+<ul>
+<li>Update implementation to consider dual bank devices (STM32H74x/5x and STM32H7Ax/Bx) and single bank devices (<strong>STM32H72x/3x</strong>)</li>
+<li>Update implementation to to support option bytes TCM_AXI_SHARED and CPUFREQ_BOOST available on <strong>STM32H72x/3x</strong> new devices</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL FMAC</strong>:
+<ul>
+<li>New HAL and LL drivers to support FMAC peripheral available on new <strong>STM32H72x/3x</strong> new devices</li>
+</ul></li>
+<li><strong>HAL/LL GPIO</strong>:
+<ul>
+<li>stm32h7xx_hal_gpio_ex.h:
+<ul>
+<li>Update Alternate functions definition for new <strong>STM32H72x/3x</strong> devices</li>
+</ul></li>
+<li>stm32h7xx_hal_gpio.c:
+<ul>
+<li>Update HAL_GPIO_DeInit implementation to re-order register sequence and avoid inconsistent ISR behavior</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL USB</strong>:
+<ul>
+<li>stm32h7xx_hal_hcd.h:
+<ul>
+<li>Update HCD_SPEED_FULL HCD_SPEED_LOW defines values with respect to new defines in stm32h7xx_ll_usb.h (USBH_FSLS_SPEED)</li>
+</ul></li>
+<li>stm32h7xx_hal_hcd.c:
+<ul>
+<li>Update HCD_HC_IN_IRQHandler to handle USB_OTG_HCINT_BBERR IT</li>
+</ul></li>
+<li>stm32h7xx_ll_usb.h:
+<ul>
+<li>USBH_FS_SPEED define renamed to USBH_FSLS_SPEED (no impact as used by the stm32h7xx_hal_hcd.h that has been updated)</li>
+</ul></li>
+<li>stm32h7xx_ll_usb.c:
+<ul>
+<li>Update USB_DeactivateDedicatedEndpoint implementation to ensure to disable EP during deactivation</li>
+<li>Update USB_HostInit implementation to fix compilation error when host core is low speed</li>
+</ul></li>
+</ul></li>
+<li>__HAL/LL HRTIM:
+<ul>
+<li>stm32h7xx_hal_hrtim.c:
+<ul>
+<li>Update Doxygen documentation</li>
+</ul></li>
+<li>stm32h7xx_ll_hrtim.h:
+<ul>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL I2C</strong>:
+<ul>
+<li>stm32h7xx_hal_i2c_ex.h:
+<ul>
+<li>Update I2CEx_FastModePlus definition to add I2C_FASTMODEPLUS_I2C5 define allowing to support for I2C5 instance available on <strong>STM32H72x/3x</strong> devices</li>
+</ul></li>
+<li>stm32h7xx_hal_i2c.c:
+<ul>
+<li>Fix implementation of HAL_I2C_Master_Seq_Transmit_IT, HAL_I2C_Master_Seq_Transmit_DMA, HAL_I2C_Master_Seq_Receive_IT and HAL_I2C_Master_Seq_Receive_DMA
+<ul>
+<li>Update xfermode upon MAX_NBYTE_SIZE reached</li>
+</ul></li>
+<li>Improve implementation of I2C_ITMasterCplt function<br />
+</li>
+</ul></li>
+<li>stm32h7xx_hal_i2c_ex.c:
+<ul>
+<li>Update doxygen documentation with references to I2C5 instance available on <strong>STM32H72x/3x</strong> devices</li>
+</ul></li>
+<li>stm32h7xx_ll_i2c.h
+<ul>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+<li>Fix doxygen documentation</li>
+</ul></li>
+<li>stm32h7xx_ll_i2c.c
+<ul>
+<li>Update LL_I2C_DeInit implementation to add support of I2C5 instance available on <strong>STM32H72x/3x</strong> devices</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL I2S</strong>: Update to support <strong>I2S Full Duplex</strong> mode (no backward compatibility break):
+<ul>
+<li>stm32h7xx_hal_i2s.h:
+<ul>
+<li>Add HAL_I2S_STATE_BUSY_TX_RX state</li>
+<li>Add I2S_IT_DXP IT and I2S_FLAG_DXP flag definitions</li>
+<li>Update value of I2S_FLAG_MASK define</li>
+<li>Add extension <strong>Full Duplex</strong> APIs Transmit/Receive APIs (Polling, IT and DMA)
+<ul>
+<li>HAL_I2SEx_TransmitReceive,HAL_I2SEx_TransmitReceive_IT and HAL_I2SEx_TransmitReceive_DMA</li>
+</ul></li>
+<li>Add extension <strong>Full Duplex</strong> callbacks: HAL_I2SEx_TxRxHalfCpltCallback and HAL_I2SEx_TxRxCpltCallback</li>
+<li>Update register callback defines to support <strong>Full Duplex</strong> TxRx complete callbacks</li>
+<li>Add IS_I2S_FULLDUPLEX private macro use in the HAL I2S driver</li>
+</ul></li>
+<li>stm32h7xx_hal_i2s.c:
+<ul>
+<li>Update HAL_I2S_Init, HAL_I2S_RegisterCallback and HAL_I2S_UnRegisterCallback implementation to consider TxRxCpltCallback and TxRxHalfCpltCallback callbacks</li>
+<li>Add HAL_I2SEx_TransmitReceive, HAL_I2SEx_TransmitReceive_IT and HAL_I2SEx_TransmitReceive_DMA APIs implementation</li>
+<li>Update HAL_I2S_IRQHandler implementation to consider full duplex mode</li>
+<li>Add HAL_I2SEx_TxRxHalfCpltCallback and HAL_I2SEx_TxRxCpltCallback weak callbacks<br />
+</li>
+<li>Add I2SEx_DMATxRxCplt and I2SEx_DMATxRxHalfCplt private functions</li>
+<li>Update implementation of I2S_Transmit_16Bit_IT and I2S_Transmit_32Bit_IT functions</li>
+<li>Update implementation of I2S_Receive_16Bit_IT and I2S_Receive_32Bit_IT functions</li>
+<li>Update doxygen documentation</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL IWDG</strong>:
+<ul>
+<li>stm32h7xx_hal_iwdg.c:
+<ul>
+<li>Update HAL_IWDG_DEFAULT_TIMEOUT define value to consider LSI value instead of hardcoded value</li>
+<li>Update doxygen documentation</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL MDMA</strong>:
+<ul>
+<li>stm32h7xx_hal_mdma.h:
+<ul>
+<li>Add __HAL_MDMA_SET_COUNTER and __HAL_MDMA_GET_COUNTER macros (same macros as the HAL DMA)</li>
+</ul></li>
+<li>stm32h7xx_ll_mdma.h
+<ul>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL SD/MMC</strong>: Add support for Sanitize and Discard functions:
+<ul>
+<li>stm32h7xx_hal_mmc.h:
+<ul>
+<li>Added APIs: HAL_MMC_EraseSequence, HAL_MMC_Sanitize, HAL_MMC_ConfigSecRemovalType and HAL_MMC_GetSupportedSecRemovalType</li>
+<li>added defines:
+<ul>
+<li>defines used for HAL_MMC_EraseSequence API:
+<ul>
+<li>HAL_MMC_ERASE, HAL_MMC_TRIM, HAL_MMC_DISCARD, HAL_MMC_SECURE_ERASE, HAL_MMC_SECURE_TRIM_STEP1 and HAL_MMC_SECURE_TRIM_STEP2</li>
+</ul></li>
+<li>defines used for HAL_MMC_ConfigSecRemovalType/HAL_MMC_GetSupportedSecRemovalType API:
+<ul>
+<li>HAL_MMC_SRT_ERASE, HAL_MMC_SRT_WRITE_CHAR_ERASE, HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM and HAL_MMC_SRT_VENDOR_DEFINED</li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li>stm32h7xx_hal_mmc.c:
+<ul>
+<li>Add implementation of APIs HAL_MMC_EraseSequence, HAL_MMC_Sanitize, HAL_MMC_ConfigSecRemovalType and HAL_MMC_GetSupportedSecRemovalType</li>
+<li>Update implementation of MMC_HighSpeed, MMC_DDR_Mode private functions</li>
+<li>Update HAL_MMC_InitCard to allow upper to 200MHz SDMM Clock<br />
+</li>
+</ul></li>
+<li>stm32h7xx_hal_sd.c:
+<ul>
+<li>Update HAL_SD_Erase implementation to consider private SDMMC_CmdErase function update</li>
+<li>Update HAL_SD_InitCard to allow upper to 200MHz SDMM Clock<br />
+</li>
+</ul></li>
+<li>stm32h7xx_ll_sdmmc.h (HAL core driver, not a user driver)
+<ul>
+<li>Update SDMMC_CmdErase function to add EraseType parameter</li>
+</ul></li>
+<li>stm32h7xx_ll_sdmmc.c:
+<ul>
+<li>Update implementation of SDMMC_CmdErase to add EraseType parameter</li>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL OPAMP</strong>:
+<ul>
+<li>stm32h7xx_ll_opamp.h:
+<ul>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL OTFDEC</strong>:
+<ul>
+<li>stm32h7xx_hal_otfdec.h
+<ul>
+<li>Add implementation of macros __HAL_OTFDEC_GET_FLAG and __HAL_OTFDEC_CLEAR_FLAG</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL PWR</strong>:
+<ul>
+<li>stm32h7xx_hal_pwr.h:
+<ul>
+<li>Update __HAL_PWR_VOLTAGESCALING_CONFIG, __HAL_PWR_GET_FLAG, __HAL_PWR_GET_WAKEUPFLAG and __HAL_PWR_CLEAR_WAKEUPFLAG macros implementation to support <strong>STM32H72x/3x</strong> devices</li>
+</ul></li>
+<li>stm32h7xx_hal_pwr_ex.h:
+<ul>
+<li>Update to delimit wakeup pins 3 and 5 definitions according to their availability (not available on <strong>STM32H72x/3x</strong> devices)<br />
+</li>
+</ul></li>
+<li>stm32h7xx_hal_pwr.c:
+<ul>
+<li>Update Doxygen documentation to consider <strong>STM32H72x/3x</strong> devices</li>
+</ul></li>
+<li>stm32h7xx_hal_pwr_ex.c:
+<ul>
+<li>Update HAL_PWREx_ControlVoltageScaling implemenation for <strong>STM32H72x/3x</strong> devices<br />
+</li>
+<li>Update HAL_PWREx_EnterSTOPMode implementation to domain Deep sleep entry foe each Core (CM7/CM4)</li>
+<li>Update HAL_PWREx_WAKEUP_PIN_IRQHandler implemenation to delimit wakeup pins 3 and 5 usage according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
+</ul></li>
+<li>stm32h7xx_ll_pwr.h
+<ul>
+<li>Update to delimit wakeup pins 3 and 5 definitions according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
+<li>Update LL_PWR_REGU_VOLTAGE_SCALE0 value to support <strong>STM32H72x/3x</strong> devices</li>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+<li>stm32h7xx_ll_pwr.c
+<ul>
+<li>Update LL_PWR_DeInit implemenation to delimit wakeup pins 3 and 5 usage according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL RCC</strong>:
+<ul>
+<li>stm32h7xx_hal_rcc.h:
+<ul>
+<li>Fix RCC_HSICALIBRATION_DEFAULT and RCC_CSICALIBRATION_DEFAULT values for STM32H74x/5x rev.V and update __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST and __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST macros implementation to consider STM32H74x/7x rev.Y**</li>
+<li>Add FMAC anc CORDIC peripherals Clock enable/disable macros</li>
+<li>GPIOI not available on <strong>STM32H72x/3x</strong>, corresponding RCC macro are delimited with GPIOI availability check</li>
+<li>Add I2C5, TIM23,TIM24 clock enable/disable macros</li>
+<li>SAI2 not available on <strong>STM32H72x/3x</strong>, corresponding RCC macro are delimited with SAI2 availability check</li>
+<li>Update __HAL_RCC_AHB3_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)<br />
+</li>
+<li>Update __HAL_RCC_AHB1_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)<br />
+</li>
+<li>Update __HAL_RCC_AHB2_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
+<li>Update __HAL_RCC_AHB4_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
+<li>Update __HAL_RCC_APB3_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
+<li>Update __HAL_RCC_APB1L_FORCE_RESET and __HAL_RCC_APB1H_FORCE_RESET implementation to consider <strong>STM32H72x/3x</strong> (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
+<li>Update __HAL_RCC_APB2_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
+<li>Update __HAL_RCC_APB4_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
+<li>Update __HAL_RCC_APB4_FORCE_RESET implementation to consider STM32H72x/3x (DEV ID 483), STM32H7Ax/Bx (DEV ID 480) and STM32H74x/5x (DEV ID 450)</li>
+<li>Add __HAL_RCC_DTS_CLKAM_ENABLE and __HAL_RCC_DTS_CLKAM_DISABLE macro</li>
+</ul></li>
+<li>stm32h7xx_hal_rcc_ex.h:
+<ul>
+<li>Update to support I2C5, TIM23,TIM24 clock setting</li>
+<li>Update to USART 9/10 clock setting macros to support <strong>STM32H72x/3x</strong> devices<br />
+</li>
+<li>Update to OSPI clock setting macros to support <strong>STM32H72x/3x</strong> devices</li>
+</ul></li>
+<li>stm32h7xx_hal_rcc_ex.c:
+<ul>
+<li>Fix HAL_RCCEx_PeriphCLKConfig implementation
+<ul>
+<li>Use HRTIM1 con define instead of HRTIM</li>
+<li>Support I2C5 available on <strong>STM32H72x/3x</strong> devices</li>
+</ul></li>
+</ul></li>
+<li>stm32h7xx_ll_rcc.h
+<ul>
+<li>Update to support I2C5, TIM23,TIM24 clock setting</li>
+<li>Update to USART 9/10 clock setting macros to support <strong>STM32H72x/3x</strong> devices<br />
+</li>
+<li>Update to OSPI clock setting macros to support <strong>STM32H72x/3x</strong> devices</li>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+<li>stm32h7xx_ll_rcc.c:
+<ul>
+<li>Update LL_RCC_DeInit implementation to add Flash latency setting versus the clock when de-initializing</li>
+<li>SAI2 not available on <strong>STM32H72x/3x</strong>, corresponding RCC macro are delimited with SAI2 availability check</li>
+<li>SAI4 not available on STM32H7Ax/Bx, corresponding RCC macro are delimited with SAI4 availability check</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL RTC</strong>:
+<ul>
+<li>stm32h7xx_hal_rtc.h:
+<ul>
+<li>Add prototype of RTC_ExitInitMode private function</li>
+</ul></li>
+<li>stm32h7xx_hal_rtc_ex.h:
+<ul>
+<li>Add RTC_MONOTONIC_COUNTER_1 define</li>
+<li>Update HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes with new parameters Instance</li>
+</ul></li>
+<li>stm32h7xx_ll_rtc.h:
+<ul>
+<li>Fix Doxygen documentation</li>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+<li>stm32h7xx_hal_rtc.c:
+<ul>
+<li>Update HAL_RTC_Init, HAL_RTC_DeInit, HAL_RTC_SetTime, HAL_RTC_SetDate, implementation with enter/exit initialization sequence</li>
+<li>Update RTC_EnterInitMode implementation to set state to HAL_RTC_STATE_TIMEOUT upon timeout</li>
+<li>Add RTC_ExitInitMode private functions implementation</li>
+</ul></li>
+<li>stm32h7xx_hal_rtc_ex.c:
+<ul>
+<li>Update HAL_RTCEx_SetActiveTampers implementation to disable all active tampers with HAL_RTCEx_DeactivateActiveTampers in case of error</li>
+<li>Update HAL_RTCEx_SetRefClock and HAL_RTCEx_DeactivateRefClock implementation with enter/exit initialization sequence</li>
+<li>Update HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs with new parameters Instance</li>
+<li>Update HAL_RTCEx_SetWakeUpTimer to fix WUTWF flag management</li>
+</ul></li>
+<li>stm32h7xx_ll_rtc.h
+<ul>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL SAI</strong>:
+<ul>
+<li>stm32h7xx_hal_sai.h:
+<ul>
+<li>Update doxygen documentation</li>
+</ul></li>
+<li>stm32h7xx_hal_sai.c:
+<ul>
+<li>Update HAL_SAI_Init to add a check on master clock divider parameter and to fix SAI frequency calculation in case of SPDIF output</li>
+<li>Update SAI_Disable implementation to remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong>:
+<ul>
+<li>stm32h7xx_hal_smartcard.c:
+<ul>
+<li>Update HAL_SMARTCARD_Transmit, HAL_SMARTCARD_Transmit_IT, HAL_SMARTCARD_Transmit_DMA and SMARTCARD_EndTransmit_IT implementation to fix an issue when No repetition after NACK is received in smartcard T=0</li>
+</ul></li>
+<li>stm32h7xx_hal_smartcard_ex.c:
+<ul>
+<li>Update RX_FIFO_DEPTH and TX_FIFO_DEPTH private defines values to fix FIFO threshold level (16 instead of 8)</li>
+</ul></li>
+<li>Update doxygen documentation</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong>:
+<ul>
+<li>stm32h7xx_hal_smbus.h:
+<ul>
+<li>Add SMBUS_FIRST_FRAME_WITH_PEC define used within Master/Slave Transmit/Receive API
+<ul>
+<li>This fix allows to properly differentiate short read or write transfers with PEC and react adequately</li>
+</ul></li>
+</ul></li>
+<li>stm32h7xx_hal_smbus.c:
+<ul>
+<li>Update private functions implementation to use “SMBUS_HandleTypeDef type” instead of "struct __SMBUS_HandleTypeDef"</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL SPDIFRX</strong>:
+<ul>
+<li>stm32h7xx_hal_spdifrx.c:
+<ul>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL SPI</strong>:
+<ul>
+<li>stm32h7xx_hal_spi.c
+<ul>
+<li>Update HAL_SPI_TransmitReceive implementation to avoid a a risk going to infinite loop in 32 bit data mode (when timeout occurs)</li>
+</ul></li>
+<li>stm32h7xx_ll_spi.h
+<ul>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL TIM</strong>:
+<ul>
+<li>stm32h7xx_hal_tim.h:
+<ul>
+<li>Update to handle channel state and DMA burst state independently allowing to use multiple DMA request with different channels of same timer:
+<ul>
+<li>Add HAL_TIM_ChannelStateTypeDef and HAL_TIM_DMABurstStateTypeDef enumerations</li>
+<li>Add ChannelState, ChannelNState and DMABurstState private parameters to the TIM_HandleTypeDef structure</li>
+<li>Update __HAL_TIM_RESET_HANDLE_STATE to consider ChannelState, ChannelNState and DMABurstState.</li>
+<li>Add private macros: TIM_CHANNEL_STATE_GET, TIM_CHANNEL_STATE_SET, TIM_CHANNEL_STATE_SET_ALL, TIM_CHANNEL_N_STATE_GET, TIM_CHANNEL_N_STATE_SET and TIM_CHANNEL_N_STATE_SET_ALL</li>
+<li>Add APIs: HAL_TIM_GetActiveChannel, HAL_TIM_GetChannelState and HAL_TIM_DMABurstState and remove TIM_DMADelayPulseCplt callback</li>
+</ul></li>
+</ul></li>
+<li>stm32h7xx_hal_tim_ex.h:
+<ul>
+<li>Add HAL_TIMEx_GetChannelNState API allowing to retrieve a channel state</li>
+</ul></li>
+<li>stm32h7xx_hal_tim.c and stm32h7xx_hal_tim_ex.c:
+<ul>
+<li>Remove private function “TIM_DMADelayPulseCplt”</li>
+<li>Update to handle channel state and DMA burst state independently allowing to use multiple DMA request with different channels of same timer<br />
+</li>
+</ul></li>
+<li>stm32h7xx_ll_tim.h
+<ul>
+<li>Fix values of defines LL_TIM_COUNTERMODE_CENTER_UP and LL_TIM_COUNTERMODE_CENTER_DOWN (values was inverted)</li>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL UART</strong>:
+<ul>
+<li>stm32h7xx_hal_uart.h:
+<ul>
+<li>Update implementation of UART_DIV_LPUART, UART_DIV_SAMPLING8 and UART_DIV_SAMPLING16 macros using “UARTPrescTable” table</li>
+</ul></li>
+<li>stm32h7xx_hal_uart.c:
+<ul>
+<li>Update implementation of HAL_UART_Transmit and HAL_UART_Receive to add lock that avoid deadlock scenario while mixing polling Transmit and IT Receive requests</li>
+<li>Rework BRR register value computation in HAL_UART_Init() for code footprint size optimization
+<ul>
+<li>Add UARTPrescTable private table</li>
+<li>Update UART_SetConfig function to use UARTPrescTable instead of run time calculation<br />
+</li>
+</ul></li>
+</ul></li>
+<li>stm32h7xx_hal_uart_ex.c:
+<ul>
+<li>Update RX_FIFO_DEPTH and TX_FIFO_DEPTH private defines values to fix FIFO threshold level (16 instead of 8)</li>
+</ul></li>
+<li>stm32h7xx_ll_lpuart.h
+<ul>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL USART</strong>:
+<ul>
+<li>stm32h7xx_hal_usart.c
+<ul>
+<li>Update HAL_USART_IRQHandler implementation to fix typo when clearing USART_CLEAR_RTOF flag</li>
+</ul></li>
+<li>stm32h7xx_hal_usart_ex.c:
+<ul>
+<li>Update RX_FIFO_DEPTH and TX_FIFO_DEPTH private defines values to fix FIFO threshold level (16 instead of 8)<br />
+</li>
+</ul></li>
+<li>stm32h7xx_ll_usart.h
+<ul>
+<li>Remove “register” “C” keyword: The register storage class specifier was deprecated in C++11 and removed in C++17</li>
+<li>Fix doxygen documentation</li>
+</ul></li>
+</ul></li>
+<li><strong>LL SYSTEM</strong>:
+<ul>
+<li>stm32h7xx_ll_system.h: Update to support <strong>STM32H72x/3x</strong> devices
+<ul>
+<li>New I2C5 instance with Fast Mode plus capability</li>
+<li>GPIOI not available</li>
+<li>AXI to ITCM RAM sharing</li>
+<li>TIM23/TIM24 new instances</li>
+<li>Device ID: 0x483</li>
+</ul></li>
+</ul></li>
+<li><strong>LL UTIL</strong>:
+<ul>
+<li>stm32h7xx_ll_utils.h:
+<ul>
+<li>Update LL_UTILS_PACKAGETYPE_xx defines to support <strong>STM32H72x/3x</strong> devices (device ID 0x483)</li>
+</ul></li>
+<li>stm32h7xx_ll_utils.c:
+<ul>
+<li>Update UTILS_MAX_FREQUENCY_SCALEx values according the STM32H74x/5x devices (device ID 0x450): 480MHz max frequency</li>
+<li>Update UTILS_MAX_FREQUENCY_SCALEx values according the <strong>STM32H72x/3x</strong> devices (device ID 0x483) : 550MHz max frequency</li>
+<li>Update LL_SetFlashLatency to support <strong>STM32H72x/3x</strong> devices (device ID 0x483)</li>
+<li>Update doxygen documentation</li>
+</ul></li>
+</ul></li>
+</ul>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="backward-compatibility">Backward compatibility</h2>
+<ul>
+<li>Extension RTC APIs HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes updated with new parameters Instance (alignment with other STM32 familes)</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
<ul>
@@ -274,12 +881,26 @@
</ul></li>
</ul></li>
</ul>
+<h2 id="known-limitations-1">Known Limitations</h2>
+<ul>
+<li><strong>HAL I2S</strong>:
+<ul>
+<li>Full duplex Transmit/receive feature not available
+<ul>
+<li>stm32h7xx_hal_i2s_ex.h/stm32h7xx_hal_i2s_ex.c: These files are empty as full duplex feature is not available in this release</li>
+</ul></li>
+</ul></li>
+</ul>
+<h2 id="backward-compatibility-1">Backward compatibility</h2>
+<ul>
+<li>None</li>
+</ul>
</div>
</div>
<div class="collapse">
-<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
+<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Official release with support of STM32H7A3/B3xx/B0xx new devices<br />
</li>
@@ -834,7 +1455,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -848,7 +1469,7 @@
<li>New PSSI driver provided supporting both modes : DMA mode recommended/ polling mode has hardware limitation confirmed and mentioned in the STM32H7A3/B3xx/B0xx erratasheet.</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility">Backward compatibility</h2>
+<h2 id="backward-compatibility-2">Backward compatibility</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -872,7 +1493,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
@@ -1147,11 +1768,11 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
-<h2 id="backward-compatibility-1">Backward compatibility</h2>
+<h2 id="backward-compatibility-3">Backward compatibility</h2>
<ul>
<li><strong>HAL TIM</strong>:
<ul>
@@ -1169,7 +1790,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add support for VOS0 power regulator voltage scaling with 480MHz over clock</li>
@@ -1639,7 +2260,7 @@
<li>Update LL_Init1msTick and LL_SetSystemCoreClock description for <strong>DUAL CORE</strong> lines</li>
</ul></li>
</ul>
-<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
<ul>
<li><strong>HAL SD</strong>:
<ul>
@@ -1653,7 +2274,7 @@
<li>Full duplex Transmit/receive feature not available</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-2">Backward compatibility</h2>
+<h2 id="backward-compatibility-4">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
@@ -1705,7 +2326,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add LL drivers : LL_ADC, LL_BDMA, LL_BUS, LL_COMP, LL_CORTEX, LL_CRC, LL_DAC, LL_DMA, LL_DMA2D, LL_DMAMUX, LL_EXTI, LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA, LL_OPAMP,LL_PWR, LL_RCC, LL_RNG, LL_RTC, LL_SPI, LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG</li>
@@ -1974,7 +2595,7 @@
<li>Protect the hcd driver to be used only if the USB_OTG_FS, USB_OTG_HS are enabled</li>
</ul></li>
</ul>
-<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="known-limitations-5">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -1982,7 +2603,7 @@
<li>A new version of this driver will be available in next release with full features tested</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-3">Backward compatibility</h2>
+<h2 id="backward-compatibility-5">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
@@ -2022,7 +2643,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers</li>
<li><strong>HAL Cortex</strong>: Driver update to support 16 MPU regions instead of 8. User can now select an MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15</li>
@@ -2034,7 +2655,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL SPI</strong>: Driver reworked to fix critical issues</li>
@@ -2045,7 +2666,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL FLASH</strong>: Add Mass Erase for both banks</li>
@@ -2060,7 +2681,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>First official release for STM32H743xx/753xx devices</li>
</ul>
diff --git a/Src/stm32h7xx_hal.c b/Src/stm32h7xx_hal.c
index 861bf40..c128145 100644
--- a/Src/stm32h7xx_hal.c
+++ b/Src/stm32h7xx_hal.c
@@ -47,10 +47,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32H7xx HAL Driver version number V1.8.0
+ * @brief STM32H7xx HAL Driver version number V1.9.0
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
-#define __STM32H7xx_HAL_VERSION_SUB1 (0x08UL) /*!< [23:16] sub1 version */
+#define __STM32H7xx_HAL_VERSION_SUB1 (0x09UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
@@ -267,11 +267,11 @@
return HAL_ERROR;
}
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
- {
- return HAL_ERROR;
- }
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
+ {
+ return HAL_ERROR;
+ }
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
@@ -874,6 +874,42 @@
}
#endif /* SYSCFG_CCCR_NCC_MMC */
+#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0)
+/** @brief SYSCFG ADC2 internal input alternate connection macros
+ * @param Adc2AltRout0 This parameter can be a value of :
+ * @arg @ref SYSCFG_ADC2_ROUT0_DAC1_1 DAC1_out1 connected to ADC2 VINP[16]
+ * @arg @ref SYSCFG_ADC2_ROUT0_VBAT4 VBAT/4 connected to ADC2 VINP[16]
+ */
+void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_ADC2ALT_ROUT0(Adc2AltRout0));
+
+ MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0);
+}
+/**
+ * @}
+ */
+#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/
+
+#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1)
+/** @brief SYSCFG ADC2 internal input alternate connection macros
+ * @param Adc2AltRout1 This parameter can be a value of :
+ * @arg @ref SYSCFG_ADC2_ROUT1_DAC1_2 DAC1_out2 connected to ADC2 VINP[17]
+ * @arg @ref SYSCFG_ADC2_ROUT1_VREFINT VREFINT connected to ADC2 VINP[17]
+ */
+void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_ADC2ALT_ROUT1(Adc2AltRout1));
+
+ MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1);
+}
+/**
+ * @}
+ */
+#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/
+
/**
* @brief Enable the Debug Module during Domain1/CDomain SLEEP mode
* @retval None
diff --git a/Src/stm32h7xx_hal_adc.c b/Src/stm32h7xx_hal_adc.c
index 38183e0..9c1b530 100644
--- a/Src/stm32h7xx_hal_adc.c
+++ b/Src/stm32h7xx_hal_adc.c
@@ -25,6 +25,8 @@
==============================================================================
[..]
(+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.
+ Note: On devices STM32H72xx and STM32H73xx, these resolution are applicable to instances ADC1 and ADC2.
+ ADC3 is featuring resolutions 12-bit, 10-bit, 8-bit, 6-bit.
(+) Interrupt generation at the end of regular conversion and in case of
analog watchdog or overrun events.
@@ -327,6 +329,14 @@
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
when no regular conversion is on-going */
+#if defined(ADC_VER_V5_V90)
+#define ADC3_CFGR_FIELDS_1 ((ADC3_CFGR_RES | ADC3_CFGR_ALIGN |\
+ ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
+ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
+ when no regular conversion is on-going */
+#endif
+
#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR |\
ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
@@ -346,7 +356,7 @@
/* - ADC clock with prescaler 256 */
/* 823 * 256 = 210688 clock cycles max */
/* Unit: cycles of CPU clock. */
-#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688) /*!< ADC conversion completion time-out value */
+#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (210688UL) /*!< ADC conversion completion time-out value */
/**
* @}
@@ -575,26 +585,46 @@
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
#if defined(ADC_VER_V5_3)
- tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
- hadc->Init.Overrun |
- hadc->Init.Resolution |
- ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
-#else
- if((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
+ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ hadc->Init.Overrun |
+ hadc->Init.Resolution |
+ ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+
+#elif defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
{
- /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */
- tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
- hadc->Init.Overrun |
- hadc->Init.Resolution |(ADC_CFGR_RES_1|ADC_CFGR_RES_0) |
- ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
+ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ hadc->Init.Overrun |
+ hadc->Init.DataAlign |
+ ((__LL_ADC12_RESOLUTION_TO_ADC3(hadc->Init.Resolution) & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL) |
+ ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
}
else
{
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
hadc->Init.Overrun |
hadc->Init.Resolution |
- ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
+ ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+ }
+
+#else
+
+ if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
+ {
+ /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */
+ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ hadc->Init.Overrun |
+ hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) |
+ ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+ }
+ else
+ {
+
+ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ hadc->Init.Overrun |
+ hadc->Init.Resolution |
+ ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
}
#endif /* ADC_VER_V5_3 */
@@ -616,8 +646,24 @@
);
}
+
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ /* Update Configuration Register CFGR */
+ MODIFY_REG(hadc->Instance->CFGR, ADC3_CFGR_FIELDS_1, tmpCFGR);
+ /* Configuration of sampling mode */
+ MODIFY_REG(hadc->Instance->CFGR2, ADC3_CFGR2_BULB | ADC3_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
+ }
+ else
+ {
+ /* Update Configuration Register CFGR */
+ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
+ }
+#else
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
+#endif
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
@@ -631,38 +677,102 @@
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
{
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ tmpCFGR = (
+ ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC3_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+ }
+ else
+ {
+ tmpCFGR = (
+ ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
+ }
+#else
tmpCFGR = (
- ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
- ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
+ ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
+#endif
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
if (hadc->Init.OversamplingMode == ENABLE)
{
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ assert_param(IS_ADC_OVERSAMPLING_RATIO_ADC3(hadc->Init.Oversampling.Ratio));
+ }
+ else
+ {
+ assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
+ }
+#else
assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
+#endif
assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
- if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
+ if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
|| (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
{
/* Multi trigger is not applicable to software-triggered conversions */
assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
}
- /* Configuration of Oversampler: */
- /* - Oversampling Ratio */
- /* - Right bit shift */
- /* - Left bit shift */
- /* - Triggered mode */
- /* - Oversampling mode (continued/resumed) */
- MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
- ADC_CFGR2_ROVSE |
- ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
- hadc->Init.Oversampling.RightBitShift |
- hadc->Init.Oversampling.TriggeredMode |
- hadc->Init.Oversampling.OversamplingStopReset);
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ /* Configuration of Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+ /* - Triggered mode */
+ /* - Oversampling mode (continued/resumed) */
+ MODIFY_REG(hadc->Instance->CFGR2,
+ ADC_CFGR2_OVSR |
+ ADC_CFGR2_OVSS |
+ ADC_CFGR2_TROVS |
+ ADC_CFGR2_ROVSM,
+ ADC_CFGR2_ROVSE |
+ hadc->Init.Oversampling.Ratio |
+ hadc->Init.Oversampling.RightBitShift |
+ hadc->Init.Oversampling.TriggeredMode |
+ hadc->Init.Oversampling.OversamplingStopReset
+ );
+ }
+ else
+ {
+
+ /* Configuration of Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+ /* - Left bit shift */
+ /* - Triggered mode */
+ /* - Oversampling mode (continued/resumed) */
+ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
+ ADC_CFGR2_ROVSE |
+ ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
+ hadc->Init.Oversampling.RightBitShift |
+ hadc->Init.Oversampling.TriggeredMode |
+ hadc->Init.Oversampling.OversamplingStopReset);
+ }
+#else
+ /* Configuration of Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+ /* - Left bit shift */
+ /* - Triggered mode */
+ /* - Oversampling mode (continued/resumed) */
+ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
+ ADC_CFGR2_ROVSE |
+ ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
+ hadc->Init.Oversampling.RightBitShift |
+ hadc->Init.Oversampling.TriggeredMode |
+ hadc->Init.Oversampling.OversamplingStopReset);
+#endif
}
else
@@ -673,9 +783,16 @@
/* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
-
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance != ADC3)
+ {
+ /* Configure the BOOST Mode */
+ ADC_ConfigureBoostMode(hadc);
+ }
+#else
/* Configure the BOOST Mode */
ADC_ConfigureBoostMode(hadc);
+#endif
}
/* Configuration of regular group sequencer: */
@@ -803,11 +920,11 @@
/* Reset register CFGR */
CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
- ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
- ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
- ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
- ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL |
- ADC_CFGR_RES | ADC_CFGR_DMNGT);
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
+ ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
+ ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL |
+ ADC_CFGR_RES | ADC_CFGR_DMNGT);
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
/* Reset register CFGR2 */
@@ -822,6 +939,30 @@
ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ /* Reset register LTR1 and HTR1 */
+ CLEAR_BIT(hadc->Instance->LTR1_TR1, ADC3_TR1_HT1 | ADC3_TR1_LT1);
+ CLEAR_BIT(hadc->Instance->HTR1_TR2, ADC3_TR2_HT2 | ADC3_TR2_LT2);
+
+ /* Reset register LTR3 and HTR3 */
+ CLEAR_BIT(hadc->Instance->RES1_TR3, ADC3_TR3_HT3 | ADC3_TR3_LT3);
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->LTR1_TR1, ADC_LTR_LT);
+ CLEAR_BIT(hadc->Instance->HTR1_TR2, ADC_HTR_HT);
+
+ /* Reset register LTR2 and HTR2*/
+ CLEAR_BIT(hadc->Instance->LTR2_DIFSEL, ADC_LTR_LT);
+ CLEAR_BIT(hadc->Instance->HTR2_CALFACT, ADC_HTR_HT);
+
+ /* Reset register LTR3 and HTR3 */
+ CLEAR_BIT(hadc->Instance->LTR3_RES10, ADC_LTR_LT);
+ CLEAR_BIT(hadc->Instance->HTR3_RES11, ADC_HTR_HT);
+ }
+#else
/* Reset register LTR1 and HTR1 */
CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR_LT);
CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR_HT);
@@ -833,6 +974,8 @@
/* Reset register LTR3 and HTR3 */
CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR_LT);
CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR_HT);
+#endif /* ADC_VER_V5_V90 */
+
/* Reset register SQR1 */
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
@@ -872,12 +1015,30 @@
/* Reset register AWD3CR */
CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ /* Reset register DIFSEL */
+ CLEAR_BIT(hadc->Instance->LTR2_DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(hadc->Instance->HTR2_CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+ }
+ else
+ {
+ /* Reset register DIFSEL */
+ CLEAR_BIT(hadc->Instance->DIFSEL_RES12, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(hadc->Instance->CALFACT_RES13, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+ }
+#else
/* Reset register DIFSEL */
CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
/* Reset register CALFACT */
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
-
+#endif /* ADC_VER_V5_V90 */
/* ========== Reset common ADC registers ========== */
@@ -2035,7 +2196,21 @@
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Enable ADC DMA mode*/
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ LL_ADC_REG_SetDMATransferMode(hadc->Instance, ADC3_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+ LL_ADC_EnableDMAReq(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_REG_SetDataTransferMode(hadc->Instance, ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
+ }
+
+#else
LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement);
+#endif
+
/* Start the DMA channel */
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
@@ -2100,7 +2275,7 @@
if (tmp_hal_status == HAL_OK)
{
/* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
+ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1, 0UL);
/* Disable the DMA channel (in case of DMA in circular mode or stop */
/* while DMA transfer is on going) */
@@ -2485,10 +2660,10 @@
else
{
/* Multimode not set or feature not available or ADC independent */
- if ((hadc->Instance->CFGR & ADC_CFGR_DMNGT) != 0UL)
- {
- overrun_error = 1UL;
- }
+ if ((hadc->Instance->CFGR & ADC_CFGR_DMNGT) != 0UL)
+ {
+ overrun_error = 1UL;
+ }
}
}
@@ -2659,11 +2834,20 @@
/* Check offset range according to oversampling setting */
if (hadc->Init.OversamplingMode == ENABLE)
{
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset/(hadc->Init.Oversampling.Ratio+1U)));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset / (hadc->Init.Oversampling.Ratio + 1U)));
}
else
{
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ assert_param(IS_ADC3_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
+ }
+ else
+#endif /* ADC_VER_V5_V90 */
+ {
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
+ }
}
/* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
@@ -2704,8 +2888,17 @@
/* - Channel rank */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
+
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance != ADC3)
+ {
+ /* ADC channels preselection */
+ hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
+ }
+#else
/* ADC channels preselection */
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
+#endif /* ADC_VER_V5_V90 */
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
@@ -2728,27 +2921,72 @@
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
- tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
-
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
+ }
+ else
+#endif /* ADC_VER_V5_V90 */
+ {
+ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
+ }
+
if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
- assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation));
- /* Set ADC selected offset signed saturation */
- LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ assert_param(IS_ADC3_OFFSET_SIGN(sConfig->OffsetSign));
+ assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSaturation));
+ /* Set ADC selected offset sign & saturation */
+ LL_ADC_SetOffsetSign(hadc->Instance, sConfig->OffsetNumber, sConfig->OffsetSign);
+ LL_ADC_SetOffsetSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
+ }
+ else
+#endif /* ADC_VER_V5_V90 */
+ {
+ assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation));
+ /* Set ADC selected offset signed saturation */
+ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
- assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift));
- /* Set ADC selected offset right shift */
- LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
+ assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift));
+ /* Set ADC selected offset right shift */
+ LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
+ }
}
else
{
- /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
- If this is the case, offset OFRx is disabled since
- sConfig->OffsetNumber = ADC_OFFSET_NONE. */
+ /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
+ If this is the case, offset OFRx is disabled since
+ sConfig->OffsetNumber = ADC_OFFSET_NONE. */
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
+ }
+ }
+ else
+#endif /* ADC_VER_V5_V90 */
+ {
if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
{
CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
@@ -2765,7 +3003,9 @@
{
CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
}
- }
+ }
+
+ }
}
/* Parameters update conditioned to ADC state: */
@@ -2793,7 +3033,7 @@
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
- if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
{
/* Configuration of common ADC parameters */
@@ -2817,7 +3057,7 @@
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
- while(wait_loop_index != 0UL)
+ while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
@@ -2911,19 +3151,42 @@
assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
}
- /* Verify thresholds range */
- if (hadc->Init.OversamplingMode == ENABLE)
+#if defined(ADC_VER_V5_V90)
+
+ if (hadc->Instance == ADC3)
{
- /* Case of oversampling enabled: thresholds are compared to oversampling
- intermediate computation (after ratio, before shift application) */
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+ /* Verify thresholds range */
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ /* Case of oversampling enabled: thresholds are compared to oversampling
+ intermediate computation (after ratio, before shift application) */
+ assert_param(IS_ADC3_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+ assert_param(IS_ADC3_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+ }
+ else
+ {
+ /* Verify if thresholds are within the selected ADC resolution */
+ assert_param(IS_ADC3_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC3_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+ }
}
else
+#endif /* ADC_VER_V5_V90 */
{
- /* Verify if thresholds are within the selected ADC resolution */
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+ /* Verify thresholds range */
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ /* Case of oversampling enabled: thresholds are compared to oversampling
+ intermediate computation (after ratio, before shift application) */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+ }
+ else
+ {
+ /* Verify if thresholds are within the selected ADC resolution */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+ }
}
/* Process locked */
@@ -2987,8 +3250,25 @@
tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
/* Set the high and low thresholds */
- MODIFY_REG(hadc->Instance->LTR1, ADC_LTR_LT , tmpAWDLowThresholdShifted);
- MODIFY_REG(hadc->Instance->HTR1, ADC_HTR_HT , tmpAWDHighThresholdShifted);
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ MODIFY_REG(hadc->Instance->LTR1_TR1,
+ ADC3_TR1_AWDFILT,
+ AnalogWDGConfig->FilteringConfig);
+ MODIFY_REG(hadc->Instance->LTR1_TR1, ADC3_TR1_LT1, tmpAWDLowThresholdShifted);
+ MODIFY_REG(hadc->Instance->LTR1_TR1, ADC3_TR1_HT1, (tmpAWDHighThresholdShifted << ADC3_TR1_HT1_Pos));
+ }
+ else
+ {
+
+ MODIFY_REG(hadc->Instance->LTR1_TR1, ADC_LTR_LT, tmpAWDLowThresholdShifted);
+ MODIFY_REG(hadc->Instance->HTR1_TR2, ADC_HTR_HT, tmpAWDHighThresholdShifted);
+ }
+#else
+ MODIFY_REG(hadc->Instance->LTR1, ADC_LTR_LT, tmpAWDLowThresholdShifted);
+ MODIFY_REG(hadc->Instance->HTR1, ADC_HTR_HT, tmpAWDHighThresholdShifted);
+#endif
/* Update state, clear previous result related to AWD1 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
@@ -3032,16 +3312,30 @@
case ADC_ANALOGWATCHDOG_ALL_REG:
case ADC_ANALOGWATCHDOG_ALL_INJEC:
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
- /* Update AWD by bitfield to keep the possibility to monitor */
- /* several channels by successive calls of this function. */
- if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
{
- SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
+
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+
}
else
{
- SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
+#endif /*ADC_VER_V5_V90*/
+ /* Update AWD by bitfield to keep the possibility to monitor */
+ /* several channels by successive calls of this function. */
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+ else
+ {
+ SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+#if defined(ADC_VER_V5_V90)
}
+#endif /*ADC_VER_V5_V90*/
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
@@ -3054,19 +3348,56 @@
tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
- if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
{
- /* Set ADC analog watchdog thresholds value of both thresholds high and low */
- MODIFY_REG(hadc->Instance->LTR2, ADC_LTR_LT , tmpAWDLowThresholdShifted);
- MODIFY_REG(hadc->Instance->HTR2, ADC_HTR_HT , tmpAWDHighThresholdShifted);
+
+ /* Analog watchdog thresholds configuration */
+ if (AnalogWDGConfig->WatchdogNumber != ADC_ANALOGWATCHDOG_1)
+ {
+ /* Shift the offset with respect to the selected ADC resolution: */
+ /* Thresholds have to be left-aligned on bit 7, the LSB (right bits) */
+ /* are set to 0. */
+ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+ tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+ }
+
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
+
+
+ }
+ else
+ {
+
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ MODIFY_REG(hadc->Instance->LTR2_DIFSEL, ADC_LTR_LT, tmpAWDLowThresholdShifted);
+ MODIFY_REG(hadc->Instance->HTR2_CALFACT, ADC_HTR_HT, tmpAWDHighThresholdShifted);
+ }
+ else
+ {
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ MODIFY_REG(hadc->Instance->LTR3_RES10, ADC_LTR_LT, tmpAWDLowThresholdShifted);
+ MODIFY_REG(hadc->Instance->HTR3_RES11, ADC_HTR_HT, tmpAWDHighThresholdShifted);
+ }
+ }
+#else
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ MODIFY_REG(hadc->Instance->LTR2, ADC_LTR_LT, tmpAWDLowThresholdShifted);
+ MODIFY_REG(hadc->Instance->HTR2, ADC_HTR_HT, tmpAWDHighThresholdShifted);
}
else
{
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
- MODIFY_REG(hadc->Instance->LTR3, ADC_LTR_LT , tmpAWDLowThresholdShifted);
- MODIFY_REG(hadc->Instance->HTR3, ADC_HTR_HT , tmpAWDHighThresholdShifted);
+ MODIFY_REG(hadc->Instance->LTR3, ADC_LTR_LT, tmpAWDLowThresholdShifted);
+ MODIFY_REG(hadc->Instance->HTR3, ADC_HTR_HT, tmpAWDHighThresholdShifted);
}
+#endif
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
/* Update state, clear previous result related to AWD2 */
@@ -3366,11 +3697,11 @@
/* Poll for ADC ready flag raised except case of multimode enabled
and ADC slave selected. */
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
- if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
- || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
)
{
- while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
{
/* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
has been cleared (after a calibration), ADEN bit is reset by the
@@ -3380,12 +3711,12 @@
4 ADC clock cycle duration */
/* Note: Test of ADC enabled required due to hardware constraint to */
/* not enable ADC if already enabled. */
- if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
LL_ADC_Enable(hadc->Instance);
}
- if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@@ -3590,13 +3921,13 @@
* @param hadc ADC handle
* @retval None.
*/
-void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
+void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc)
{
uint32_t freq;
- if(ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
+ if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
{
freq = HAL_RCC_GetHCLKFreq();
- switch(hadc->Init.ClockPrescaler)
+ switch (hadc->Init.ClockPrescaler)
{
case ADC_CLOCK_SYNC_PCLK_DIV1:
case ADC_CLOCK_SYNC_PCLK_DIV2:
@@ -3612,7 +3943,7 @@
else
{
freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
- switch(hadc->Init.ClockPrescaler)
+ switch (hadc->Init.ClockPrescaler)
{
case ADC_CLOCK_ASYNC_DIV2:
case ADC_CLOCK_ASYNC_DIV4:
@@ -3624,8 +3955,8 @@
break;
case ADC_CLOCK_ASYNC_DIV16:
freq /= 16UL;
- break;
- case ADC_CLOCK_ASYNC_DIV32:
+ break;
+ case ADC_CLOCK_ASYNC_DIV32:
freq /= 32UL;
break;
case ADC_CLOCK_ASYNC_DIV64:
@@ -3642,18 +3973,17 @@
}
}
-#if defined(ADC_VER_V5_3)
+#if defined(ADC_VER_V5_3) || defined(ADC_VER_V5_V90)
freq /= 2U;
-
if (freq <= 6250000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
}
- else if(freq <= 12500000UL)
+ else if (freq <= 12500000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
}
- else if(freq <= 25000000UL)
+ else if (freq <= 25000000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
}
@@ -3662,9 +3992,9 @@
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
}
#else
- if(HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
+ if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
{
- if(freq > 20000000UL)
+ if (freq > 20000000UL)
{
SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
}
@@ -3681,11 +4011,11 @@
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
}
- else if(freq <= 12500000UL)
+ else if (freq <= 12500000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
}
- else if(freq <= 25000000UL)
+ else if (freq <= 25000000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
}
diff --git a/Src/stm32h7xx_hal_adc_ex.c b/Src/stm32h7xx_hal_adc_ex.c
index 858a7b5..a325f76 100644
--- a/Src/stm32h7xx_hal_adc_ex.c
+++ b/Src/stm32h7xx_hal_adc_ex.c
@@ -67,8 +67,8 @@
/* Fixed timeout value for ADC calibration. */
/* Fixed timeout value for ADC calibration. */
-/* Values defined to be higher than worst cases: low clock frequency, */
-/* maximum prescalers. */
+/* Values defined to be higher than worst cases: low clock frequency, */
+/* maximum prescalers. */
/* Ex of profile low frequency : f_ADC at 0.125 Mhz (minimum value */
/* according to Data sheet), calibration_time MAX = 165010 / f_ADC */
/* 165010 / 125000 = 1.32s */
@@ -159,7 +159,7 @@
HAL_ADC_STATE_BUSY_INTERNAL);
/* Start ADC calibration in mode single-ended or differential */
- LL_ADC_StartCalibration(hadc->Instance , CalibrationMode, SingleDiff );
+ LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff);
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
@@ -223,38 +223,38 @@
* @param LinearCalib_Buffer: Linear calibration factor
* @retval HAL state
*/
-HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer)
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
{
uint32_t cnt;
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t temp_REG_IsConversionOngoing = 0UL;
-
+
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
+
/* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
- if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
tmp_hal_status = ADC_Enable(hadc);
}
-
+
if (tmp_hal_status == HAL_OK)
{
- if(LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
{
LL_ADC_REG_StopConversion(hadc->Instance);
temp_REG_IsConversionOngoing = 1UL;
}
- for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL; cnt--)
+ for (cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL; cnt--)
{
- LinearCalib_Buffer[cnt-1U]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt));
+ LinearCalib_Buffer[cnt - 1U] = LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT - cnt));
}
- if(temp_REG_IsConversionOngoing != 0UL)
+ if (temp_REG_IsConversionOngoing != 0UL)
{
LL_ADC_REG_StartConversion(hadc->Instance);
}
}
-
+
return tmp_hal_status;
}
@@ -319,7 +319,7 @@
* @param LinearCalib_Buffer: Linear calibration factor
* @retval HAL state
*/
-HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer)
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
{
uint32_t cnt;
__IO uint32_t wait_loop_index = 0;
@@ -341,7 +341,7 @@
}
- if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
{
/* Enable ADC internal voltage regulator */
SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
@@ -350,7 +350,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL)));
- while(wait_loop_index != 0UL)
+ while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
@@ -370,37 +370,38 @@
return HAL_ERROR;
}
-/* Enable the ADC peripheral */
- if(LL_ADC_IsEnabled(hadc->Instance) == 0UL) /* Enable the ADC if it is disabled */
- {
+ /* Enable the ADC peripheral */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) /* Enable the ADC if it is disabled */
+ {
if (ADC_Enable(hadc) != HAL_OK)
{
return HAL_ERROR;
}
else
{
- for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
+ for (cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
{
- LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt), LinearCalib_Buffer[cnt-1U]);
+ LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT - cnt), LinearCalib_Buffer[cnt - 1U]);
}
(void)ADC_Disable(hadc);
}
- }else /* ADC is already enabled, so no need to enable it but need to stop conversion */
+ }
+ else /* ADC is already enabled, so no need to enable it but need to stop conversion */
+ {
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
{
- if(LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
- {
- LL_ADC_REG_StopConversion(hadc->Instance);
- temp_REG_IsConversionOngoing = 1UL;
- }
- for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
- {
- LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt), LinearCalib_Buffer[cnt-1U]);
- }
- if(temp_REG_IsConversionOngoing != 0UL)
- {
- LL_ADC_REG_StartConversion(hadc->Instance);
- }
+ LL_ADC_REG_StopConversion(hadc->Instance);
+ temp_REG_IsConversionOngoing = 1UL;
}
+ for (cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
+ {
+ LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT - cnt), LinearCalib_Buffer[cnt - 1U]);
+ }
+ if (temp_REG_IsConversionOngoing != 0UL)
+ {
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ }
return HAL_OK;
}
@@ -414,32 +415,34 @@
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t cnt, FactorOffset;
uint32_t LinearCalib_Buffer[ADC_LINEAR_CALIB_REG_COUNT];
-
+
/* Linearity calibration is retrieved from engi bytes
read values from registers and put them to the CALFACT2 register */
/* If needed linearity calibration can be done in runtime using
LL_ADC_GetCalibrationLinearFactor() */
- if(hadc->Instance == ADC1)
- {
+ if (hadc->Instance == ADC1)
+ {
FactorOffset = 0UL;
- }else if(hadc->Instance == ADC2)
- {
+ }
+ else if (hadc->Instance == ADC2)
+ {
FactorOffset = 8UL;
- }else /*Case ADC3*/
- {
- FactorOffset = 16UL;
- }
-
+ }
+ else /*Case ADC3*/
+ {
+ FactorOffset = 16UL;
+ }
+
for (cnt = 0UL; cnt < ADC_LINEAR_CALIB_REG_COUNT; cnt++)
{
- LinearCalib_Buffer[cnt] = *(uint32_t*)(ADC_LINEAR_CALIB_REG_1_ADDR + FactorOffset + cnt);
+ LinearCalib_Buffer[cnt] = *(uint32_t *)(ADC_LINEAR_CALIB_REG_1_ADDR + FactorOffset + cnt);
}
- if (HAL_ADCEx_LinearCalibration_SetValue(hadc,(uint32_t*)LinearCalib_Buffer) != HAL_OK)
+ if (HAL_ADCEx_LinearCalibration_SetValue(hadc, (uint32_t *)LinearCalib_Buffer) != HAL_OK)
{
tmp_hal_status = HAL_ERROR;
}
- return tmp_hal_status;
+ return tmp_hal_status;
}
/**
@@ -1531,8 +1534,8 @@
/* Clear HAL_ADC_STATE_REG_BUSY bit */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
- /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
- MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
+ /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1, 0UL);
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* while DMA transfer is on going) */
@@ -1790,8 +1793,19 @@
assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
+#if defined(ADC_VER_V5_V90)
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedOffsetSaturation));
+ if (hadc->Instance == ADC3)
+ {
+ assert_param(IS_ADC3_OFFSET_SIGN(sConfigInjected->InjectedOffsetSign));
+ assert_param(IS_ADC3_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
+ }
+ else
+#endif /* ADC_VER_V5_V90 */
+ {
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
+ }
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
{
@@ -1803,13 +1817,20 @@
/* Check offset range according to oversampling setting */
if (hadc->Init.OversamplingMode == ENABLE)
{
- assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset/(hadc->Init.Oversampling.Ratio+1U)));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset / (hadc->Init.Oversampling.Ratio + 1U)));
}
else
{
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
}
-
+#if defined(ADC_VER_V5_V90)
+ /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+ ignored (considered as reset) */
+ if (hadc->Instance == ADC3)
+ {
+ assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
+ }
+#endif /* ADC_VER_V5_V90 */
/* JDISCEN and JAUTO bits can't be set at the same time */
assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
@@ -1977,8 +1998,16 @@
/* mode is disabled. */
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
- /* ADC channels preselection */
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance != ADC3)
+ {
+ /* ADC channels preselection */
+ hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
+ }
+#else
+ /* ADC channels preselection */
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
+#endif /* ADC_VER_V5_V90 */
/* If auto-injected mode is disabled: no constraint */
if (sConfigInjected->AutoInjectedConv == DISABLE)
@@ -2061,8 +2090,8 @@
ADC_CFGR2_JOVSE |
ADC_CFGR2_OVSR |
ADC_CFGR2_OVSS,
- ADC_CFGR2_JOVSE |
- ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
+ ADC_CFGR2_JOVSE |
+ ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
sConfigInjected->InjecOversampling.RightBitShift
);
}
@@ -2072,47 +2101,89 @@
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
}
- /* Set sampling time of the selected ADC channel */
- LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
- tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
-
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
+ }
+ else
+#endif /* ADC_VER_V5_V90 */
+ {
+ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
+ }
+
if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
{
/* Set ADC selected offset number */
- LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel,
- tmpOffsetShifted);
+ LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted);
- /* Set ADC selected offset signed saturation */
- LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
-
- /* Set ADC selected offset right shift */
- LL_ADC_SetDataRightShift(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetRightShift == (uint32_t)ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ /* Set ADC selected offset sign & saturation */
+ LL_ADC_SetOffsetSign(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedOffsetSign);
+ LL_ADC_SetOffsetSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
+ }
+ else
+#endif /* ADC_VER_V5_V90 */
+ {
+ /* Set ADC selected offset signed saturation */
+ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
}
else
{
- /* Scan each offset register to check if the selected channel is targeted. */
- /* If this is the case, the corresponding offset number is disabled. */
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
{
- LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ /* Scan each offset register to check if the selected channel is targeted. */
+ /* If this is the case, the corresponding offset number is disabled. */
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
+ }
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ else
+#endif /* ADC_VER_V5_V90 */
{
- LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
- }
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
- {
- LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
- }
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
- {
- LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ /* Scan each offset register to check if the selected channel is targeted. */
+ /* If this is the case, the corresponding offset number is disabled. */
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
}
}
@@ -2141,7 +2212,7 @@
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
- if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
{
/* Configuration of common ADC parameters (continuation) */
/* Software is allowed to change common parameters only when all ADCs */
@@ -2164,7 +2235,7 @@
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
- while(wait_loop_index != 0UL)
+ while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
@@ -2274,7 +2345,7 @@
/* transition from multimode to independent mode). */
if (multimode->Mode != ADC_MODE_INDEPENDENT)
{
- MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
+ MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
diff --git a/Src/stm32h7xx_hal_cordic.c b/Src/stm32h7xx_hal_cordic.c
new file mode 100644
index 0000000..85c19c1
--- /dev/null
+++ b/Src/stm32h7xx_hal_cordic.c
@@ -0,0 +1,1352 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_cordic.c
+ * @author MCD Application Team
+ * @brief CORDIC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORDIC peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Callback functions
+ * + IRQ handler management
+ * + Peripheral State functions
+ *
+ * @verbatim
+ ================================================================================
+ ##### How to use this driver #####
+ ================================================================================
+ [..]
+ The CORDIC HAL driver can be used as follows:
+
+ (#) Initialize the CORDIC low level resources by implementing the HAL_CORDIC_MspInit():
+ (++) Enable the CORDIC interface clock using __HAL_RCC_CORDIC_CLK_ENABLE()
+ (++) In case of using interrupts (e.g. HAL_CORDIC_Calculate_IT())
+ (+++) Configure the CORDIC interrupt priority using HAL_NVIC_SetPriority()
+ (+++) Enable the CORDIC IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In CORDIC IRQ handler, call HAL_CORDIC_IRQHandler()
+ (++) In case of using DMA to control data transfer (e.g. HAL_CORDIC_Calculate_DMA())
+ (+++) Enable the DMA2 interface clock using
+ __HAL_RCC_DMA2_CLK_ENABLE()
+ (+++) Configure and enable two DMA channels one for managing data transfer from
+ memory to peripheral (input channel) and another channel for managing data
+ transfer from peripheral to memory (output channel)
+ (+++) Associate the initialized DMA handle to the CORDIC DMA handle
+ using __HAL_LINKDMA()
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the two DMA channels.
+ Resort to HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+
+ (#) Initialize the CORDIC HAL using HAL_CORDIC_Init(). This function
+ (++) resorts to HAL_CORDIC_MspInit() for low-level initialization,
+
+ (#) Configure CORDIC processing (calculation) using HAL_CORDIC_Configure().
+ This function configures:
+ (++) Processing functions: Cosine, Sine, Phase, Modulus, Arctangent,
+ Hyperbolic cosine, Hyperbolic sine, Hyperbolic arctangent,
+ Natural log, Square root
+ (++) Scaling factor: 1 to 2exp(-7)
+ (++) Width of input data: 32 bits input data size (Q1.31 format) or 16 bits
+ input data size (Q1.15 format)
+ (++) Width of output data: 32 bits output data size (Q1.31 format) or 16 bits
+ output data size (Q1.15 format)
+ (++) Number of 32-bit write expected for one calculation: One 32-bits write
+ or Two 32-bit write
+ (++) Number of 32-bit read expected after one calculation: One 32-bits read
+ or Two 32-bit read
+ (++) Precision: 1 to 15 cycles for calculation (the more cycles, the better precision)
+
+ (#) Four processing (calculation) functions are available:
+ (++) Polling mode: processing API is blocking function
+ i.e. it processes the data and wait till the processing is finished
+ API is HAL_CORDIC_Calculate
+ (++) Polling Zero-overhead mode: processing API is blocking function
+ i.e. it processes the data and wait till the processing is finished
+ A bit faster than standard polling mode, but blocking also AHB bus
+ API is HAL_CORDIC_CalculateZO
+ (++) Interrupt mode: processing API is not blocking functions
+ i.e. it processes the data under interrupt
+ API is HAL_CORDIC_Calculate_IT
+ (++) DMA mode: processing API is not blocking functions and the CPU is
+ not used for data transfer,
+ i.e. the data transfer is ensured by DMA
+ API is HAL_CORDIC_Calculate_DMA
+
+ (#) Call HAL_CORDIC_DeInit() to de-initialize the CORDIC peripheral. This function
+ (++) resorts to HAL_CORDIC_MspDeInit() for low-level de-initialization,
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_CORDIC_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_CORDIC_RegisterCallback() allows to register following callbacks:
+ (+) ErrorCallback : Error Callback.
+ (+) CalculateCpltCallback : Calculate complete Callback.
+ (+) MspInitCallback : CORDIC MspInit.
+ (+) MspDeInitCallback : CORDIC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ErrorCallback : Error Callback.
+ (+) CalculateCpltCallback : Calculate complete Callback.
+ (+) MspInitCallback : CORDIC MspInit.
+ (+) MspDeInitCallback : CORDIC MspDeInit.
+
+ By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET,
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_CORDIC_ErrorCallback(), @ref HAL_CORDIC_CalculateCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_CORDIC_RegisterCallback() before calling @ref HAL_CORDIC_DeInit()
+ or HAL_CORDIC_Init() function.
+
+ When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+#if defined(CORDIC)
+#ifdef HAL_CORDIC_MODULE_ENABLED
+
+/** @addtogroup STM32H7xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORDIC CORDIC
+ * @brief CORDIC HAL driver modules.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup CORDIC_Private_Functions CORDIC Private Functions
+ * @{
+ */
+static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff);
+static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff);
+static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CORDIC_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions
+ * @{
+ */
+
+/** @defgroup CORDIC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CORDIC peripheral and the associated handle
+ (+) DeInitialize the CORDIC peripheral
+ (+) Initialize the CORDIC MSP (MCU Specific Package)
+ (+) De-Initialize the CORDIC MSP
+
+ [..]
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the CORDIC peripheral and the associated handle.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Check the CORDIC handle allocation */
+ if (hcordic == NULL)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check the instance */
+ assert_param(IS_CORDIC_ALL_INSTANCE(hcordic->Instance));
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ if (hcordic->State == HAL_CORDIC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcordic->Lock = HAL_UNLOCKED;
+
+ /* Reset callbacks to legacy functions */
+ hcordic->ErrorCallback = HAL_CORDIC_ErrorCallback; /* Legacy weak ErrorCallback */
+ hcordic->CalculateCpltCallback = HAL_CORDIC_CalculateCpltCallback; /* Legacy weak CalculateCpltCallback */
+
+ if (hcordic->MspInitCallback == NULL)
+ {
+ hcordic->MspInitCallback = HAL_CORDIC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Initialize the low level hardware */
+ hcordic->MspInitCallback(hcordic);
+ }
+#else
+ if (hcordic->State == HAL_CORDIC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcordic->Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware */
+ HAL_CORDIC_MspInit(hcordic);
+ }
+#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
+
+ /* Set CORDIC error code to none */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Reset pInBuff and pOutBuff */
+ hcordic->pInBuff = NULL;
+ hcordic->pOutBuff = NULL;
+
+ /* Reset NbCalcToOrder and NbCalcToGet */
+ hcordic->NbCalcToOrder = 0U;
+ hcordic->NbCalcToGet = 0U;
+
+ /* Reset DMADirection */
+ hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
+
+ /* Change CORDIC peripheral state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the CORDIC peripheral.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Check the CORDIC handle allocation */
+ if (hcordic == NULL)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CORDIC_ALL_INSTANCE(hcordic->Instance));
+
+ /* Change CORDIC peripheral state */
+ hcordic->State = HAL_CORDIC_STATE_BUSY;
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ if (hcordic->MspDeInitCallback == NULL)
+ {
+ hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
+ }
+
+ /* De-Initialize the low level hardware */
+ hcordic->MspDeInitCallback(hcordic);
+#else
+ /* De-Initialize the low level hardware: CLOCK, NVIC, DMA */
+ HAL_CORDIC_MspDeInit(hcordic);
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+
+ /* Set CORDIC error code to none */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Reset pInBuff and pOutBuff */
+ hcordic->pInBuff = NULL;
+ hcordic->pOutBuff = NULL;
+
+ /* Reset NbCalcToOrder and NbCalcToGet */
+ hcordic->NbCalcToOrder = 0U;
+ hcordic->NbCalcToGet = 0U;
+
+ /* Reset DMADirection */
+ hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
+
+ /* Change CORDIC peripheral state */
+ hcordic->State = HAL_CORDIC_STATE_RESET;
+
+ /* Reset Lock */
+ hcordic->Lock = HAL_UNLOCKED;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the CORDIC MSP.
+ * @param hcordic CORDIC handle
+ * @retval None
+ */
+__weak void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcordic);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CORDIC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the CORDIC MSP.
+ * @param hcordic CORDIC handle
+ * @retval None
+ */
+__weak void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcordic);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CORDIC_MspDeInit can be implemented in the user file
+ */
+}
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+/**
+ * @brief Register a CORDIC CallBack.
+ * To be used instead of the weak predefined callback.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CORDIC_ERROR_CB_ID error Callback ID
+ * @arg @ref HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID
+ * @arg @ref HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, void (* pCallback)(CORDIC_HandleTypeDef *_hcordic))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CORDIC_ERROR_CB_ID :
+ hcordic->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CORDIC_CALCULATE_CPLT_CB_ID :
+ hcordic->CalculateCpltCallback = pCallback;
+ break;
+
+ case HAL_CORDIC_MSPINIT_CB_ID :
+ hcordic->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CORDIC_MSPDEINIT_CB_ID :
+ hcordic->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcordic->State == HAL_CORDIC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CORDIC_MSPINIT_CB_ID :
+ hcordic->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CORDIC_MSPDEINIT_CB_ID :
+ hcordic->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+/**
+ * @brief Unregister a CORDIC CallBack.
+ * CORDIC callback is redirected to the weak predefined callback.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CORDIC_ERROR_CB_ID error Callback ID
+ * @arg @ref HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID
+ * @arg @ref HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CORDIC_ERROR_CB_ID :
+ hcordic->ErrorCallback = HAL_CORDIC_ErrorCallback;
+ break;
+
+ case HAL_CORDIC_CALCULATE_CPLT_CB_ID :
+ hcordic->CalculateCpltCallback = HAL_CORDIC_CalculateCpltCallback;
+ break;
+
+ case HAL_CORDIC_MSPINIT_CB_ID :
+ hcordic->MspInitCallback = HAL_CORDIC_MspInit;
+ break;
+
+ case HAL_CORDIC_MSPDEINIT_CB_ID :
+ hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcordic->State == HAL_CORDIC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CORDIC_MSPINIT_CB_ID :
+ hcordic->MspInitCallback = HAL_CORDIC_MspInit;
+ break;
+
+ case HAL_CORDIC_MSPDEINIT_CB_ID :
+ hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Control functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the CORDIC peripheral: function, precision, scaling factor,
+ number of input data and output data, size of input data and output data.
+ (+) Calculate output data of CORDIC processing on input date, using the
+ existing CORDIC configuration
+ [..] Four processing functions are available for calculation:
+ (+) Polling mode
+ (+) Polling mode, with Zero-Overhead register access
+ (+) Interrupt mode
+ (+) DMA mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the CORDIC processing according to the specified
+ parameters in the CORDIC_ConfigTypeDef structure.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @param sConfig pointer to a CORDIC_ConfigTypeDef structure that
+ * contains the CORDIC configuration information.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_CORDIC_FUNCTION(sConfig->Function));
+ assert_param(IS_CORDIC_PRECISION(sConfig->Precision));
+ assert_param(IS_CORDIC_SCALE(sConfig->Scale));
+ assert_param(IS_CORDIC_NBWRITE(sConfig->NbWrite));
+ assert_param(IS_CORDIC_NBREAD(sConfig->NbRead));
+ assert_param(IS_CORDIC_INSIZE(sConfig->InSize));
+ assert_param(IS_CORDIC_OUTSIZE(sConfig->OutSize));
+
+ /* Check handle state is ready */
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ /* Apply all configuration parameters in CORDIC control register */
+ MODIFY_REG(hcordic->Instance->CSR, \
+ (CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE | \
+ CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE), \
+ (sConfig->Function | sConfig->Precision | sConfig->Scale | \
+ sConfig->NbWrite | sConfig->NbRead | sConfig->InSize | sConfig->OutSize));
+ }
+ else
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Carry out data of CORDIC processing in polling mode,
+ * according to the existing CORDIC configuration.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param pInBuff Pointer to buffer containing input data for CORDIC processing.
+ * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
+ * @param NbCalc Number of CORDIC calculation to process.
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t index;
+ int32_t *p_tmp_in_buff = pInBuff;
+ int32_t *p_tmp_out_buff = pOutBuff;
+
+ /* Check parameters setting */
+ if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ /* Reset CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Write of input data in Write Data register, and increment input buffer pointer */
+ CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
+
+ /* Calculation is started.
+ Provide next set of input data, until number of calculation is achieved */
+ for (index = (NbCalc - 1U); index > 0U; index--)
+ {
+ /* Write of input data in Write Data register, and increment input buffer pointer */
+ CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
+
+ /* Wait for RRDY flag to be raised */
+ do
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((HAL_GetTick() - tickstart) > Timeout)
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_TIMEOUT;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+ }
+ }
+ while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY));
+
+ /* Read output data from Read Data register, and increment output buffer pointer */
+ CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
+ }
+
+ /* Read output data from Read Data register, and increment output buffer pointer */
+ CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Carry out data of CORDIC processing in Zero-Overhead mode (output data being read
+ * soon as input data are written), according to the existing CORDIC configuration.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param pInBuff Pointer to buffer containing input data for CORDIC processing.
+ * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
+ * @param NbCalc Number of CORDIC calculation to process.
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t index;
+ int32_t *p_tmp_in_buff = pInBuff;
+ int32_t *p_tmp_out_buff = pOutBuff;
+
+ /* Check parameters setting */
+ if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ /* Reset CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Write of input data in Write Data register, and increment input buffer pointer */
+ CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
+
+ /* Calculation is started.
+ Provide next set of input data, until number of calculation is achieved */
+ for (index = (NbCalc - 1U); index > 0U; index--)
+ {
+ /* Write of input data in Write Data register, and increment input buffer pointer */
+ CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
+
+ /* Read output data from Read Data register, and increment output buffer pointer
+ The reading is performed in Zero-Overhead mode:
+ reading is ordered immediately without waiting result ready flag */
+ CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((HAL_GetTick() - tickstart) > Timeout)
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_TIMEOUT;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Read output data from Read Data register, and increment output buffer pointer
+ The reading is performed in Zero-Overhead mode:
+ reading is ordered immediately without waiting result ready flag */
+ CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Carry out data of CORDIC processing in interrupt mode,
+ * according to the existing CORDIC configuration.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param pInBuff Pointer to buffer containing input data for CORDIC processing.
+ * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
+ * @param NbCalc Number of CORDIC calculation to process.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc)
+{
+ int32_t *tmp_pInBuff = pInBuff;
+
+ /* Check parameters setting */
+ if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ /* Reset CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_BUSY;
+
+ /* Store the buffers addresses and number of calculations in handle,
+ provisioning initial write of input data that will be done */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
+ {
+ /* Two writes of input data are expected */
+ tmp_pInBuff++;
+ tmp_pInBuff++;
+ }
+ else
+ {
+ /* One write of input data is expected */
+ tmp_pInBuff++;
+ }
+ hcordic->pInBuff = tmp_pInBuff;
+ hcordic->pOutBuff = pOutBuff;
+ hcordic->NbCalcToOrder = NbCalc - 1U;
+ hcordic->NbCalcToGet = NbCalc;
+
+ /* Enable Result Ready Interrupt */
+ __HAL_CORDIC_ENABLE_IT(hcordic, CORDIC_IT_IEN);
+
+ /* Set back pointer to start of input data buffer */
+ tmp_pInBuff = pInBuff;
+
+ /* Initiate the processing by providing input data
+ in the Write Data register */
+ WRITE_REG(hcordic->Instance->WDATA, (uint32_t)*tmp_pInBuff);
+
+ /* Check if second write of input data is expected */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
+ {
+ /* Increment pointer to input data */
+ tmp_pInBuff++;
+
+ /* Perform second write of input data */
+ WRITE_REG(hcordic->Instance->WDATA, (uint32_t)*tmp_pInBuff);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Carry out input and/or output data of CORDIC processing in DMA mode,
+ * according to the existing CORDIC configuration.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param pInBuff Pointer to buffer containing input data for CORDIC processing.
+ * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
+ * @param NbCalc Number of CORDIC calculation to process.
+ * @param DMADirection Direction of DMA transfers.
+ * This parameter can be one of the following values:
+ * @arg @ref CORDIC_DMA_Direction CORDIC DMA direction
+ * @note pInBuff or pOutBuff is unused in case of unique DMADirection transfer, and can
+ * be set to NULL value in this case.
+ * @note pInBuff and pOutBuff buffers must be 32-bit aligned to ensure a correct
+ * DMA transfer to and from the Peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection)
+{
+ uint32_t sizeinbuff;
+ uint32_t sizeoutbuff;
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ /* Check the parameters */
+ assert_param(IS_CORDIC_DMA_DIRECTION(DMADirection));
+
+ /* Check parameters setting */
+ if (NbCalc == 0U)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Check if CORDIC DMA direction "Out" is requested */
+ if ((DMADirection == CORDIC_DMA_DIR_OUT) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
+ {
+ /* Check parameters setting */
+ if (pOutBuff == NULL)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+
+ /* Check if CORDIC DMA direction "In" is requested */
+ if ((DMADirection == CORDIC_DMA_DIR_IN) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
+ {
+ /* Check parameters setting */
+ if (pInBuff == NULL)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ }
+
+ if (hcordic->State == HAL_CORDIC_STATE_READY)
+ {
+ /* Reset CORDIC error code */
+ hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_BUSY;
+
+ /* Get DMA direction */
+ hcordic->DMADirection = DMADirection;
+
+ /* Check if CORDIC DMA direction "Out" is requested */
+ if ((DMADirection == CORDIC_DMA_DIR_OUT) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
+ {
+ /* Set the CORDIC DMA transfer complete callback */
+ hcordic->hdmaOut->XferCpltCallback = CORDIC_DMAOutCplt;
+ /* Set the DMA error callback */
+ hcordic->hdmaOut->XferErrorCallback = CORDIC_DMAError;
+
+ /* Check number of output data at each calculation,
+ to retrieve the size of output data buffer */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NRES))
+ {
+ sizeoutbuff = 2U * NbCalc;
+ }
+ else
+ {
+ sizeoutbuff = NbCalc;
+ }
+
+ outputaddr = (uint32_t)pOutBuff;
+
+ /* Enable the DMA stream managing CORDIC output data read */
+ if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, outputaddr, sizeoutbuff) != HAL_OK)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable output data Read DMA requests */
+ SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_REN);
+ }
+
+ /* Check if CORDIC DMA direction "In" is requested */
+ if ((DMADirection == CORDIC_DMA_DIR_IN) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
+ {
+ /* Set the CORDIC DMA transfer complete callback */
+ hcordic->hdmaIn->XferCpltCallback = CORDIC_DMAInCplt;
+ /* Set the DMA error callback */
+ hcordic->hdmaIn->XferErrorCallback = CORDIC_DMAError;
+
+ /* Check number of input data expected for each calculation,
+ to retrieve the size of input data buffer */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
+ {
+ sizeinbuff = 2U * NbCalc;
+ }
+ else
+ {
+ sizeinbuff = NbCalc;
+ }
+
+ inputaddr = (uint32_t)pInBuff;
+
+ /* Enable the DMA stream managing CORDIC input data write */
+ if (HAL_DMA_Start_IT(hcordic->hdmaIn, inputaddr, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff) != HAL_OK)
+ {
+ /* Update the error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Enable input data Write DMA request */
+ SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set CORDIC error code */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Exported_Functions_Group3 Callback functions
+ * @brief Callback functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..] This section provides Interruption and DMA callback functions:
+ (+) DMA or Interrupt calculate complete
+ (+) DMA or Interrupt error
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief CORDIC error callback.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @retval None
+ */
+__weak void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcordic);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CORDIC_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CORDIC calculate complete callback.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @retval None
+ */
+__weak void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcordic);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CORDIC_CalculateCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Exported_Functions_Group4 IRQ handler management
+ * @brief IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+[..] This section provides IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle CORDIC interrupt request.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @retval None
+ */
+void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Check if calculation complete interrupt is enabled and if result ready
+ flag is raised */
+ if (__HAL_CORDIC_GET_IT_SOURCE(hcordic, CORDIC_IT_IEN) != 0U)
+ {
+ if (__HAL_CORDIC_GET_FLAG(hcordic, CORDIC_FLAG_RRDY) != 0U)
+ {
+ /* Decrement number of calculations to get */
+ hcordic->NbCalcToGet--;
+
+ /* Read output data from Read Data register, and increment output buffer pointer */
+ CORDIC_ReadOutDataIncrementPtr(hcordic, &(hcordic->pOutBuff));
+
+ /* Check if calculations are still to be ordered */
+ if (hcordic->NbCalcToOrder > 0U)
+ {
+ /* Decrement number of calculations to order */
+ hcordic->NbCalcToOrder--;
+
+ /* Continue the processing by providing another write of input data
+ in the Write Data register, and increment input buffer pointer */
+ CORDIC_WriteInDataIncrementPtr(hcordic, &(hcordic->pInBuff));
+ }
+
+ /* Check if all calculations results are got */
+ if (hcordic->NbCalcToGet == 0U)
+ {
+ /* Disable Result Ready Interrupt */
+ __HAL_CORDIC_DISABLE_IT(hcordic, CORDIC_IT_IEN);
+
+ /* Change the CORDIC state */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Call calculation complete callback */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ /*Call registered callback*/
+ hcordic->CalculateCpltCallback(hcordic);
+#else
+ /*Call legacy weak (surcharged) callback*/
+ HAL_CORDIC_CalculateCpltCallback(hcordic);
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORDIC_Exported_Functions_Group5 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CORDIC handle state.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @retval HAL state
+ */
+HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Return CORDIC handle state */
+ return hcordic->State;
+}
+
+/**
+ * @brief Return the CORDIC peripheral error.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module
+ * @note The returned error is a bit-map combination of possible errors
+ * @retval Error bit-map
+ */
+uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic)
+{
+ /* Return CORDIC error code */
+ return hcordic->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CORDIC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Write input data for CORDIC processing, and increment input buffer pointer.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param ppInBuff Pointer to pointer to input buffer.
+ * @retval none
+ */
+static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff)
+{
+ /* First write of input data in the Write Data register */
+ WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff);
+
+ /* Increment input data pointer */
+ (*ppInBuff)++;
+
+ /* Check if second write of input data is expected */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
+ {
+ /* Second write of input data in the Write Data register */
+ WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff);
+
+ /* Increment input data pointer */
+ (*ppInBuff)++;
+ }
+}
+
+/**
+ * @brief Read output data of CORDIC processing, and increment output buffer pointer.
+ * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
+ * the configuration information for CORDIC module.
+ * @param ppOutBuff Pointer to pointer to output buffer.
+ * @retval none
+ */
+static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
+{
+ /* First read of output data from the Read Data register */
+ **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA);
+
+ /* Increment output data pointer */
+ (*ppOutBuff)++;
+
+ /* Check if second read of output data is expected */
+ if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NRES))
+ {
+ /* Second read of output data from the Read Data register */
+ **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA);
+
+ /* Increment output data pointer */
+ (*ppOutBuff)++;
+ }
+}
+
+/**
+ * @brief DMA CORDIC Input Data process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable the DMA transfer for input request */
+ CLEAR_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN);
+
+ /* Check if DMA direction is CORDIC Input only (no DMA for CORDIC Output) */
+ if (hcordic->DMADirection == CORDIC_DMA_DIR_IN)
+ {
+ /* Change the CORDIC DMA direction to none */
+ hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
+
+ /* Change the CORDIC state to ready */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Call calculation complete callback */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ /*Call registered callback*/
+ hcordic->CalculateCpltCallback(hcordic);
+#else
+ /*Call legacy weak (surcharged) callback*/
+ HAL_CORDIC_CalculateCpltCallback(hcordic);
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA CORDIC Output Data process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+ CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable the DMA transfer for output request */
+ CLEAR_BIT(hcordic->Instance->CSR, CORDIC_DMA_REN);
+
+ /* Change the CORDIC DMA direction to none */
+ hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
+
+ /* Change the CORDIC state to ready */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Call calculation complete callback */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ /*Call registered callback*/
+ hcordic->CalculateCpltCallback(hcordic);
+#else
+ /*Call legacy weak (surcharged) callback*/
+ HAL_CORDIC_CalculateCpltCallback(hcordic);
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA CORDIC communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void CORDIC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set CORDIC handle state to error */
+ hcordic->State = HAL_CORDIC_STATE_READY;
+
+ /* Set CORDIC handle error code to DMA error */
+ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
+
+ /* Call user callback */
+#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
+ /*Call registered callback*/
+ hcordic->ErrorCallback(hcordic);
+#else
+ /*Call legacy weak (surcharged) callback*/
+ HAL_CORDIC_ErrorCallback(hcordic);
+#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+#endif /* CORDIC */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_cryp.c b/Src/stm32h7xx_hal_cryp.c
index 2d8beb4..0407c65 100644
--- a/Src/stm32h7xx_hal_cryp.c
+++ b/Src/stm32h7xx_hal_cryp.c
@@ -103,6 +103,8 @@
(##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
encryption + data XORing. It works in a similar way for ciphertext (C).
(##) Final phase: IP generates the authenticated tag (T) using the last block of data.
+ HAL_CRYPEx_AESGCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond
+ to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits.
(#) structure of message construction in GCM is defined as below :
(##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
(##) The authenticated header A (also knows as Additional Authentication Data AAD)
@@ -143,6 +145,8 @@
(##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
encryption + data XORing. It works in a similar way for ciphertext (C).
(##) Final phase: IP generates the authenticated tag (T) using the last block of data.
+ HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag.
+ user should consider only part of this 4 words, if Tag length is less than 128 bits
*** Callback registration ***
=============================
@@ -900,7 +904,7 @@
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input: Pointer to the input buffer (plaintext)
- * @param Size: Length of the plaintext buffer in word.
+ * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit.
* @param Output: Pointer to the output buffer(ciphertext)
* @param Timeout: Specify Timeout value
* @retval HAL status
@@ -1030,7 +1034,7 @@
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input: Pointer to the input buffer (ciphertext )
- * @param Size: Length of the plaintext buffer in word.
+ * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
* @param Output: Pointer to the output buffer(plaintext)
* @param Timeout: Specify Timeout value
* @retval HAL status
@@ -1161,7 +1165,7 @@
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input: Pointer to the input buffer (plaintext)
- * @param Size: Length of the plaintext buffer in word
+ * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
* @param Output: Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
@@ -1278,7 +1282,7 @@
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input: Pointer to the input buffer (ciphertext )
- * @param Size: Length of the plaintext buffer in word.
+ * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
* @param Output: Pointer to the output buffer(plaintext)
* @retval HAL status
*/
@@ -1397,7 +1401,7 @@
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input: Pointer to the input buffer (plaintext)
- * @param Size: Length of the plaintext buffer in word.
+ * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
* @param Output: Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
@@ -1550,7 +1554,7 @@
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input: Pointer to the input buffer (ciphertext )
- * @param Size: Length of the plaintext buffer in word
+ * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
* @param Output: Pointer to the output buffer(plaintext)
* @retval HAL status
*/
diff --git a/Src/stm32h7xx_hal_cryp_ex.c b/Src/stm32h7xx_hal_cryp_ex.c
index d088f56..a8a94aa 100644
--- a/Src/stm32h7xx_hal_cryp_ex.c
+++ b/Src/stm32h7xx_hal_cryp_ex.c
@@ -103,6 +103,9 @@
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param AuthTag: Pointer to the authentication buffer
+ * the AuthTag generated here is 128bits length, if the TAG length is
+ * less than 128bits, user should consider only the valid part of AuthTag
+ * buffer which correspond exactly to TAG length.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -260,6 +263,9 @@
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param AuthTag: Pointer to the authentication buffer
+ * the AuthTag generated here is 128bits length, if the TAG length is
+ * less than 128bits, user should consider only the valid part of AuthTag
+ * buffer which correspond exactly to TAG length.
* @param Timeout: Timeout duration
* @retval HAL status
*/
diff --git a/Src/stm32h7xx_hal_dcmi.c b/Src/stm32h7xx_hal_dcmi.c
index 28ca216..46906e0 100644
--- a/Src/stm32h7xx_hal_dcmi.c
+++ b/Src/stm32h7xx_hal_dcmi.c
@@ -462,7 +462,7 @@
*/
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
{
- register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
+ uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
@@ -516,7 +516,7 @@
*/
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi)
{
- register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
+ uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
diff --git a/Src/stm32h7xx_hal_dfsdm.c b/Src/stm32h7xx_hal_dfsdm.c
index 75a3a58..e73cd80 100644
--- a/Src/stm32h7xx_hal_dfsdm.c
+++ b/Src/stm32h7xx_hal_dfsdm.c
@@ -459,7 +459,7 @@
/* Set analog watchdog parameters */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
- ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
+ ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
/* Set channel offset and right bit shift */
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
@@ -680,38 +680,38 @@
{
switch (CallbackID)
{
- case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
- hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
- break;
- case HAL_DFSDM_CHANNEL_SCD_CB_ID :
- hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
- break;
- case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
- hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
- break;
- case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
- hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
+ hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_SCD_CB_ID :
+ hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
+ hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
+ hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
{
switch (CallbackID)
{
- case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
- hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
- break;
- case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
- hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
+ hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
+ hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1094,7 +1094,7 @@
/* Configure threshold and break signals */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
- Threshold);
+ Threshold);
/* Start short circuit detection */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
@@ -1263,7 +1263,7 @@
/* Configure threshold and break signals */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
- Threshold);
+ Threshold);
/* Start short circuit detection */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
@@ -1911,14 +1911,14 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
{
/* Configure channel and continuous mode for regular conversion */
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
{
hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
- DFSDM_FLTCR1_RCONT);
+ DFSDM_FLTCR1_RCONT);
}
else
{
@@ -1954,7 +1954,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
{
/* Configure channel for injected conversion */
hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
@@ -1962,7 +1962,7 @@
hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
/* Update number of injected channels remaining */
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1U;
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
}
else
{
@@ -2022,7 +2022,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
{
/* Start regular conversion */
DFSDM_RegConvStart(hdfsdm_filter);
@@ -2052,7 +2052,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
/* Return error status */
return HAL_ERROR;
@@ -2091,7 +2091,7 @@
}
/* Update DFSDM filter state only if not continuous conversion and SW trigger */
if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
{
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
@@ -2116,7 +2116,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
/* Return error status */
status = HAL_ERROR;
@@ -2146,7 +2146,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
{
/* Enable interrupts for regular conversions */
hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
@@ -2177,7 +2177,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
/* Return error status */
status = HAL_ERROR;
@@ -2227,21 +2227,21 @@
}
/* Check parameters compatibility */
else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
- (Length != 1U))
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
+ (Length != 1U))
{
status = HAL_ERROR;
}
else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
{
status = HAL_ERROR;
}
/* Check DFSDM filter state */
else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
{
/* Set callbacks on DMA handler */
hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
@@ -2251,7 +2251,7 @@
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
- (uint32_t) pData, Length) != HAL_OK)
+ (uint32_t) pData, Length) != HAL_OK)
{
/* Set DFSDM filter in error state */
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
@@ -2304,21 +2304,21 @@
}
/* Check parameters compatibility */
else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
- (Length != 1U))
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
+ (Length != 1U))
{
status = HAL_ERROR;
}
else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
+ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
+ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
{
status = HAL_ERROR;
}
/* Check DFSDM filter state */
else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
{
/* Set callbacks on DMA handler */
hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
@@ -2328,7 +2328,7 @@
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \
- (uint32_t) pData, Length) != HAL_OK)
+ (uint32_t) pData, Length) != HAL_OK)
{
/* Set DFSDM filter in error state */
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
@@ -2363,7 +2363,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
/* Return error status */
status = HAL_ERROR;
@@ -2433,7 +2433,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
{
/* Start injected conversion */
DFSDM_InjConvStart(hdfsdm_filter);
@@ -2463,7 +2463,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
/* Return error status */
return HAL_ERROR;
@@ -2514,7 +2514,7 @@
/* end of injected sequence, reset the value */
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1U;
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
}
/* Return function status */
@@ -2537,7 +2537,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
/* Return error status */
status = HAL_ERROR;
@@ -2567,7 +2567,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
{
/* Enable interrupts for injected conversions */
hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
@@ -2598,7 +2598,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
/* Return error status */
status = HAL_ERROR;
@@ -2648,19 +2648,19 @@
}
/* Check parameters compatibility */
else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
- (Length > hdfsdm_filter->InjConvRemaining))
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
+ (Length > hdfsdm_filter->InjConvRemaining))
{
status = HAL_ERROR;
}
else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
{
status = HAL_ERROR;
}
/* Check DFSDM filter state */
else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
{
/* Set callbacks on DMA handler */
hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
@@ -2670,7 +2670,7 @@
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
- (uint32_t) pData, Length) != HAL_OK)
+ (uint32_t) pData, Length) != HAL_OK)
{
/* Set DFSDM filter in error state */
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
@@ -2723,19 +2723,19 @@
}
/* Check parameters compatibility */
else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
- (Length > hdfsdm_filter->InjConvRemaining))
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
+ (Length > hdfsdm_filter->InjConvRemaining))
{
status = HAL_ERROR;
}
else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
- (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
+ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
{
status = HAL_ERROR;
}
/* Check DFSDM filter state */
else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
{
/* Set callbacks on DMA handler */
hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
@@ -2745,7 +2745,7 @@
/* Start DMA in interrupt mode */
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \
- (uint32_t) pData, Length) != HAL_OK)
+ (uint32_t) pData, Length) != HAL_OK)
{
/* Set DFSDM filter in error state */
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
@@ -2780,7 +2780,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
- (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
+ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
/* Return error status */
status = HAL_ERROR;
@@ -2856,7 +2856,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
{
/* Return error status */
status = HAL_ERROR;
@@ -2898,7 +2898,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
{
/* Return error status */
status = HAL_ERROR;
@@ -2940,7 +2940,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
{
/* Return error status */
status = HAL_ERROR;
@@ -2971,7 +2971,7 @@
/* Check DFSDM filter state */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
- (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
+ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
{
/* Return error status */
status = HAL_ERROR;
@@ -3113,7 +3113,7 @@
/* Check if overrun occurs during regular conversion */
if(((temp_fltisr & DFSDM_FLTISR_ROVRF) != 0U) && \
- ((temp_fltcr2 & DFSDM_FLTCR2_ROVRIE) != 0U))
+ ((temp_fltcr2 & DFSDM_FLTCR2_ROVRIE) != 0U))
{
/* Clear regular overrun flag */
hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
@@ -3130,7 +3130,7 @@
}
/* Check if overrun occurs during injected conversion */
else if(((temp_fltisr & DFSDM_FLTISR_JOVRF) != 0U) && \
- ((temp_fltcr2 & DFSDM_FLTCR2_JOVRIE) != 0U))
+ ((temp_fltcr2 & DFSDM_FLTCR2_JOVRIE) != 0U))
{
/* Clear injected overrun flag */
hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
@@ -3147,7 +3147,7 @@
}
/* Check if end of regular conversion */
else if(((temp_fltisr & DFSDM_FLTISR_REOCF) != 0U) && \
- ((temp_fltcr2 & DFSDM_FLTCR2_REOCIE) != 0U))
+ ((temp_fltcr2 & DFSDM_FLTCR2_REOCIE) != 0U))
{
/* Call regular conversion complete callback */
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
@@ -3158,7 +3158,7 @@
/* End of conversion if mode is not continuous and software trigger */
if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
- (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
{
/* Disable interrupts for regular conversions */
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
@@ -3170,7 +3170,7 @@
}
/* Check if end of injected conversion */
else if(((temp_fltisr & DFSDM_FLTISR_JEOCF) != 0U) && \
- ((temp_fltcr2 & DFSDM_FLTCR2_JEOCIE) != 0U))
+ ((temp_fltcr2 & DFSDM_FLTCR2_JEOCIE) != 0U))
{
/* Call injected conversion complete callback */
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
@@ -3195,12 +3195,12 @@
}
/* end of injected sequence, reset the value */
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1U;
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
}
}
/* Check if analog watchdog occurs */
else if(((temp_fltisr & DFSDM_FLTISR_AWDF) != 0U) && \
- ((temp_fltcr2 & DFSDM_FLTCR2_AWDIE) != 0U))
+ ((temp_fltcr2 & DFSDM_FLTCR2_AWDIE) != 0U))
{
uint32_t reg;
uint32_t threshold;
@@ -3232,8 +3232,8 @@
}
/* Check if clock absence occurs */
else if((hdfsdm_filter->Instance == filter0Instance) && \
- ((temp_fltisr & DFSDM_FLTISR_CKABF) != 0U) && \
- ((temp_fltcr2 & DFSDM_FLTCR2_CKABIE) != 0U))
+ ((temp_fltisr & DFSDM_FLTISR_CKABF) != 0U) && \
+ ((temp_fltcr2 & DFSDM_FLTCR2_CKABIE) != 0U))
{
uint32_t reg;
uint32_t channel = 0;
@@ -3265,8 +3265,8 @@
}
/* Check if short circuit detection occurs */
else if((hdfsdm_filter->Instance == filter0Instance) && \
- ((temp_fltisr & DFSDM_FLTISR_SCDF) != 0U) && \
- ((temp_fltcr2 & DFSDM_FLTCR2_SCDIE) != 0U))
+ ((temp_fltisr & DFSDM_FLTISR_SCDF) != 0U) && \
+ ((temp_fltcr2 & DFSDM_FLTCR2_SCDIE) != 0U))
{
uint32_t reg;
uint32_t channel = 0;
@@ -3609,7 +3609,7 @@
}
else /* DFSDM1_Channel7 */
{
- channel = 7;
+ channel = 7;
}
return channel;
@@ -3648,12 +3648,12 @@
}
/* Update remaining injected conversions */
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1U;
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
}
}
/* Update DFSDM filter state */
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
- HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
+ HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
}
/**
@@ -3684,12 +3684,12 @@
}
/* Update remaining injected conversions */
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1U;
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
}
/* Update DFSDM filter state */
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
- HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
}
/**
@@ -3726,7 +3726,7 @@
/* If regular conversion was in progress, restart it */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
- (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
}
@@ -3766,18 +3766,18 @@
/* If regular conversion was in progress, restart it */
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
- (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
+ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
}
/* Update remaining injected conversions */
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
- hdfsdm_filter->InjectedChannelsNbr : 1U;
+ hdfsdm_filter->InjectedChannelsNbr : 1U;
/* Update DFSDM filter state */
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
- HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
+ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
}
/**
diff --git a/Src/stm32h7xx_hal_dma.c b/Src/stm32h7xx_hal_dma.c
index aeabc95..6a8bce5 100644
--- a/Src/stm32h7xx_hal_dma.c
+++ b/Src/stm32h7xx_hal_dma.c
@@ -529,7 +529,9 @@
return HAL_ERROR;
}
+#if defined (BDMA1) /* No DMAMUX available for BDMA1 available on STM32H7Ax/Bx devices only */
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+#endif /* BDMA1 */
{
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
diff --git a/Src/stm32h7xx_hal_dts.c b/Src/stm32h7xx_hal_dts.c
index 1196317..e2774d1 100644
--- a/Src/stm32h7xx_hal_dts.c
+++ b/Src/stm32h7xx_hal_dts.c
@@ -76,6 +76,10 @@
*/
#define TS_TIMEOUT_MS (5UL)
+/**
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
diff --git a/Src/stm32h7xx_hal_eth.c b/Src/stm32h7xx_hal_eth.c
index a34d44e..033739e 100644
--- a/Src/stm32h7xx_hal_eth.c
+++ b/Src/stm32h7xx_hal_eth.c
@@ -791,19 +791,19 @@
*/
HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
{
- uint32_t descindex = 0, counter;
- ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
+ uint32_t descindex;
+
+ ETH_DMADescTypeDef *dmarxdesc;
if(heth->gState == HAL_ETH_STATE_READY)
{
heth->gState = HAL_ETH_STATE_BUSY;
/* Set IOC bit to all Rx descriptors */
- for(counter= 0; counter < (uint32_t)ETH_RX_DESC_CNT; counter++)
+ for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
{
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
- INCR_RX_DESC_INDEX(descindex, 1U);
dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
+ SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
}
/* save IT mode to ETH Handle */
@@ -827,9 +827,6 @@
/* Clear Tx and Rx process stopped flags */
heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
- heth->gState = HAL_ETH_STATE_READY;
- heth->RxState = HAL_ETH_STATE_BUSY_RX;
-
/* Enable ETH DMA interrupts:
- Tx complete interrupt
- Rx complete interrupt
@@ -838,6 +835,9 @@
__HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE |
ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
+ heth->gState = HAL_ETH_STATE_READY;
+ heth->RxState = HAL_ETH_STATE_BUSY_RX;
+
return HAL_OK;
}
else
@@ -894,8 +894,8 @@
*/
HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
{
- ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[0];
- uint32_t index;
+ ETH_DMADescTypeDef *dmarxdesc;
+ uint32_t descindex;
if(heth->gState != HAL_ETH_STATE_RESET)
{
@@ -904,8 +904,11 @@
/* Disable intrrupts:
- Tx complete interrupt
- - Rx complete interrupt */
- __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMA_NORMAL_IT | ETH_DMA_RX_IT | ETH_DMA_TX_IT));
+ - Rx complete interrupt
+ - Fatal bus interrupt
+ */
+ __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE |
+ ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
/* Disable the DMA transmission */
CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
@@ -923,8 +926,9 @@
CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
/* Clear IOC bit to all Rx descriptors */
- for(index = 0; index < (uint32_t)ETH_RX_DESC_CNT; index++)
+ for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
{
+ dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
}
@@ -1001,15 +1005,12 @@
if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
{
heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
- heth->gState = HAL_ETH_STATE_READY;
+ heth->gState = HAL_ETH_STATE_ERROR;
return HAL_ERROR;
}
}
}
- /* Set ETH HAL State to Ready */
- heth->gState = HAL_ETH_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -1030,6 +1031,7 @@
{
if(pTxConfig == NULL)
{
+ heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
return HAL_ERROR;
}
@@ -1038,7 +1040,7 @@
/* Config DMA Tx descriptor by Tx Packet info */
if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
{
- heth->ErrorCode = HAL_ETH_ERROR_BUSY;
+ heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
return HAL_ERROR;
}
@@ -1148,6 +1150,8 @@
/* Build Descriptors if an incomplete Packet is received */
if(appdesccnt > 0U)
{
+ dmarxdesclist->CurRxDesc = descidx;
+ dmarxdesclist->FirstAppDesc = firstappdescidx;
descidx = firstappdescidx;
dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
@@ -1168,12 +1172,17 @@
{
SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
}
-
- /* Increment rx descriptor index */
- INCR_RX_DESC_INDEX(descidx, 1U);
- /* Get descriptor address */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ if(descscancnt < (appdesccnt - 1U))
+ {
+ /* Increment rx descriptor index */
+ INCR_RX_DESC_INDEX(descidx, 1U);
+ /* Get descriptor address */
+ dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ }
}
+
+ /* Set the Tail pointer address to the last rx descriptor hold by the app */
+ WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
}
/* Fill information to Rx descriptors list: No received Packet */
@@ -1234,7 +1243,7 @@
if(dmarxdesc->BackupAddr1 != 0U)
{
/* Point to next buffer */
- rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
+ rxbuff = rxbuff->next;
/* Get Address and length of the second buffer address */
rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
rxbuff->len = heth->Init.RxBuffLen;
@@ -1252,7 +1261,7 @@
dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
/* Point to next buffer */
- rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
+ rxbuff = rxbuff->next;
}
/* last descriptor data length */
@@ -1272,7 +1281,7 @@
/* Get the Length of the first buffer address */
rxbuff->len = heth->Init.RxBuffLen;
/* Point to next buffer */
- rxbuff = (struct __ETH_BufferTypeDef *)rxbuff->next;
+ rxbuff = rxbuff->next;
/* Get the Address the Length of the second buffer address */
rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
rxbuff->len = lastdesclen - (heth->Init.RxBuffLen);
@@ -1435,7 +1444,7 @@
SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
}
- if(descscan < (dmarxdesclist->AppDescNbr - 1U))
+ if(descscan < (totalappdescnbr - 1U))
{
/* Increment rx descriptor index */
INCR_RX_DESC_INDEX(descindex, 1U);
@@ -1450,6 +1459,9 @@
/* reset the Application desc number */
WRITE_REG(dmarxdesclist->AppDescNbr, 0);
+ /* reset the application context descriptor */
+ WRITE_REG(heth->RxDescList.AppContextDesc, 0);
+
return HAL_OK;
}
@@ -2390,6 +2402,10 @@
* @}
*/
+/** @addtogroup ETH_Private_Functions ETH Private Functions
+ * @{
+ */
+
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
{
uint32_t macregval;
@@ -2703,7 +2719,7 @@
WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
/* Set Receive Descriptor Tail pointer Address */
- WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (((uint32_t)(ETH_RX_DESC_CNT - 1))*sizeof(ETH_DMADescTypeDef)))));
+ WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1))));
}
/**
@@ -2900,7 +2916,7 @@
descnbr += 1U;
/* Get the next Tx buffer in the list */
- txbuffer = (struct __ETH_BufferTypeDef *)txbuffer->next;
+ txbuffer = txbuffer->next;
/* Set header or buffer 1 address */
WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
@@ -2910,7 +2926,7 @@
if (txbuffer->next != NULL)
{
/* Get the next Tx buffer in the list */
- txbuffer = (struct __ETH_BufferTypeDef *)txbuffer->next;
+ txbuffer = txbuffer->next;
/* Set buffer 2 address */
WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
/* Set buffer 2 Length */
@@ -2982,6 +2998,9 @@
}
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
/**
* @}
diff --git a/Src/stm32h7xx_hal_fdcan.c b/Src/stm32h7xx_hal_fdcan.c
index fb4b0fa..35b51b6 100644
--- a/Src/stm32h7xx_hal_fdcan.c
+++ b/Src/stm32h7xx_hal_fdcan.c
@@ -185,6 +185,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
+#if defined(FDCAN1)
+
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
@@ -202,6 +204,7 @@
* @{
*/
#define FDCAN_TIMEOUT_VALUE 10U
+#define FDCAN_TIMEOUT_COUNT 50U
#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
@@ -2618,7 +2621,7 @@
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -2643,7 +2646,7 @@
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -2934,8 +2937,20 @@
}
else
{
+ /* Check that the Rx FIFO 0 is full & overwrite mode is on*/
+ if(((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U)
+ {
+ if(((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0OM) >> FDCAN_RXF0C_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+ {
+ /* When overwrite status is on discard first message in FIFO */
+ GetIndex = 1U;
+ }
+ }
+
+ /* Calculate Rx FIFO 0 element index*/
+ GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
+
/* Calculate Rx FIFO 0 element address */
- GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U));
}
}
@@ -2960,8 +2975,20 @@
}
else
{
+ /* Check that the Rx FIFO 1 is full & overwrite mode is on*/
+ if(((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U)
+ {
+ if(((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1OM) >> FDCAN_RXF1C_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+ {
+ /* When overwrite status is on discard first message in FIFO */
+ GetIndex = 1U;
+ }
+ }
+
+ /* Calculate Rx FIFO 1 element index*/
+ GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
+
/* Calculate Rx FIFO 1 element address */
- GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U));
}
}
@@ -3120,7 +3147,7 @@
pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
}
- /* Retrieve RxFrameType */
+ /* Retrieve TxFrameType */
pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
/* Retrieve ErrorStateIndicator */
@@ -3129,7 +3156,7 @@
/* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
TxEventAddress++;
- /* Retrieve RxTimestamp */
+ /* Retrieve TxTimestamp */
pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
/* Retrieve DataLength */
@@ -3801,7 +3828,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -3875,7 +3902,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -3931,7 +3958,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4000,7 +4027,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4036,7 +4063,7 @@
while ((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4060,7 +4087,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4111,7 +4138,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4161,7 +4188,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4213,7 +4240,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4274,7 +4301,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4335,7 +4362,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4396,7 +4423,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4459,7 +4486,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4520,7 +4547,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4590,7 +4617,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4660,7 +4687,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4764,7 +4791,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -4814,7 +4841,7 @@
while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
{
/* Check for the Timeout */
- if (Counter > FDCAN_TIMEOUT_VALUE)
+ if (Counter > FDCAN_TIMEOUT_COUNT)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
@@ -6166,4 +6193,6 @@
* @}
*/
+#endif /* FDCAN1 */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_flash.c b/Src/stm32h7xx_hal_flash.c
index 7f3bc10..6383da5 100644
--- a/Src/stm32h7xx_hal_flash.c
+++ b/Src/stm32h7xx_hal_flash.c
@@ -105,7 +105,6 @@
* @{
*/
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
-
/**
* @}
*/
@@ -166,10 +165,16 @@
{
bank = FLASH_BANK_1;
}
- else
+#if defined (DUAL_BANK)
+ else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
{
bank = FLASH_BANK_2;
}
+#endif /* DUAL_BANK */
+ else
+ {
+ return HAL_ERROR;
+ }
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
@@ -179,6 +184,7 @@
if(status == HAL_OK)
{
+#if defined (DUAL_BANK)
if(bank == FLASH_BANK_1)
{
#if defined (FLASH_OPTCR_PG_OTP)
@@ -199,6 +205,20 @@
/* Set PG bit */
SET_BIT(FLASH->CR2, FLASH_CR_PG);
}
+#else /* Single Bank */
+#if defined (FLASH_OPTCR_PG_OTP)
+ if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+ {
+ /* Set OTP_PG bit */
+ SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+ }
+ else
+#endif /* FLASH_OPTCR_PG_OTP */
+ {
+ /* Set PG bit */
+ SET_BIT(FLASH->CR1, FLASH_CR_PG);
+ }
+#endif /* DUAL_BANK */
__ISB();
__DSB();
@@ -228,6 +248,7 @@
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+#if defined (DUAL_BANK)
#if defined (FLASH_OPTCR_PG_OTP)
if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
{
@@ -248,6 +269,20 @@
CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
}
}
+#else /* Single Bank */
+#if defined (FLASH_OPTCR_PG_OTP)
+ if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+ {
+ /* If the program operation is completed, disable the OTP_PG */
+ CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+ }
+ else
+#endif /* FLASH_OPTCR_PG_OTP */
+ {
+ /* If the program operation is completed, disable the PG */
+ CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
+ }
+#endif /* DUAL_BANK */
}
/* Process Unlocked */
@@ -291,10 +326,16 @@
{
bank = FLASH_BANK_1;
}
- else
+#if defined (DUAL_BANK)
+ else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
{
bank = FLASH_BANK_2;
}
+#endif /* DUAL_BANK */
+ else
+ {
+ return HAL_ERROR;
+ }
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
@@ -308,6 +349,7 @@
{
pFlash.Address = FlashAddress;
+#if defined (DUAL_BANK)
if(bank == FLASH_BANK_1)
{
/* Set internal variables used by the IRQ handler */
@@ -352,6 +394,32 @@
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
#endif /* FLASH_CR_OPERRIE */
}
+#else /* Single Bank */
+ /* Set internal variables used by the IRQ handler */
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
+
+#if defined (FLASH_OPTCR_PG_OTP)
+ if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+ {
+ /* Set OTP_PG bit */
+ SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+ }
+ else
+#endif /* FLASH_OPTCR_PG_OTP */
+ {
+ /* Set PG bit */
+ SET_BIT(FLASH->CR1, FLASH_CR_PG);
+ }
+
+ /* Enable End of Operation and Error interrupts for Bank 1 */
+#if defined (FLASH_CR_OPERRIE)
+ __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+ FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+#else
+ __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+ FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+#endif /* FLASH_CR_OPERRIE */
+#endif /* DUAL_BANK */
__ISB();
__DSB();
@@ -460,7 +528,8 @@
}
}
- /* Check FLASH Bank2 End of Operation flag */
+#if defined (DUAL_BANK)
+ /* Check FLASH Bank2 End of Operation flag */
if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET)
{
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2)
@@ -527,6 +596,7 @@
}
}
}
+#endif /* DUAL_BANK */
/* Check FLASH Bank1 operation error flags */
#if defined (FLASH_SR_OPERR)
@@ -571,6 +641,7 @@
HAL_FLASH_OperationErrorCallback(temp);
}
+#if defined (DUAL_BANK)
/* Check FLASH Bank2 operation error flags */
#if defined (FLASH_SR_OPERR)
errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
@@ -613,6 +684,7 @@
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(temp);
}
+#endif /* DUAL_BANK */
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
@@ -621,17 +693,21 @@
__HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+#if defined (DUAL_BANK)
/* Disable Bank2 Operation and Error source interrupt */
__HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#endif /* DUAL_BANK */
#else
/* Disable Bank1 Operation and Error source interrupt */
__HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+#if defined (DUAL_BANK)
/* Disable Bank2 Operation and Error source interrupt */
__HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* DUAL_BANK */
#endif /* FLASH_CR_OPERRIE */
/* Process Unlocked */
@@ -714,6 +790,7 @@
}
}
+#if defined (DUAL_BANK)
if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
{
/* Authorize the FLASH Bank2 Registers access */
@@ -726,6 +803,7 @@
return HAL_ERROR;
}
}
+#endif /* DUAL_BANK */
return HAL_OK;
}
@@ -745,6 +823,7 @@
return HAL_ERROR;
}
+#if defined (DUAL_BANK)
/* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */
SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
@@ -753,6 +832,7 @@
{
return HAL_ERROR;
}
+#endif /* DUAL_BANK */
return HAL_OK;
}
@@ -810,10 +890,12 @@
{
status = HAL_ERROR;
}
+#if defined (DUAL_BANK)
else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
{
status = HAL_ERROR;
}
+#endif /* DUAL_BANK */
else
{
status = HAL_OK;
@@ -908,20 +990,22 @@
Even if the FLASH operation fails, the QW flag will be reset and an error
flag will be set */
- uint32_t bsyflag, errorflag;
+ uint32_t bsyflag = FLASH_FLAG_QW_BANK1;
+ uint32_t errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
uint32_t tickstart = HAL_GetTick();
assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
- /* Select bsyflag depending on Bank */
- if(Bank == FLASH_BANK_1)
+#if defined (DUAL_BANK)
+
+ if (Bank == FLASH_BANK_2)
{
- bsyflag = FLASH_FLAG_QW_BANK1;
- }
- else
- {
+ /* Get Error Flags */
+ errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
+ /* Select bsyflag depending on Bank */
bsyflag = FLASH_FLAG_QW_BANK2;
}
+#endif /* DUAL_BANK */
while(__HAL_FLASH_GET_FLAG(bsyflag))
{
@@ -934,18 +1018,8 @@
}
}
- /* Get Error Flags */
- if (Bank == FLASH_BANK_1)
- {
- errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
- }
- else
- {
- errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
- }
-
- /* In case of error reported in Flash SR1 or SR2 registers (ECCC not managed as an error) */
- if((errorflag & 0x7DFFFFFFU) != 0U)
+ /* In case of error reported in Flash SR1 or SR2 register */
+ if((errorflag & 0x7FFFFFFFU) != 0U)
{
/*Save the error code*/
pFlash.ErrorCode |= errorflag;
@@ -965,6 +1039,7 @@
__HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
}
}
+#if defined (DUAL_BANK)
else
{
if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2))
@@ -973,6 +1048,7 @@
__HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
}
}
+#endif /* DUAL_BANK */
return HAL_OK;
}
@@ -1064,6 +1140,7 @@
return HAL_ERROR;
}
}
+#if defined (DUAL_BANK)
else
{
if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2))
@@ -1077,6 +1154,7 @@
return HAL_ERROR;
}
}
+#endif /* DUAL_BANK */
/* If there is no error flag set */
return HAL_OK;
diff --git a/Src/stm32h7xx_hal_flash_ex.c b/Src/stm32h7xx_hal_flash_ex.c
index 33f9e87..dc45d4a 100644
--- a/Src/stm32h7xx_hal_flash_ex.c
+++ b/Src/stm32h7xx_hal_flash_ex.c
@@ -45,6 +45,8 @@
(++) PCROP protection configuration and control per bank
(++) Secure area configuration and control per bank
(++) Core Boot address configuration
+ (++) TCM / AXI shared RAM configuration
+ (++) CPU Frequency Boost configuration
(#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(),
HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions
@@ -123,12 +125,22 @@
#if defined (DUAL_CORE)
static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
-#endif /* DUAL_CORE */
+#endif /*DUAL_CORE*/
#if defined (FLASH_OTPBL_LOCKBL)
static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block);
static uint32_t FLASH_OB_OTP_GetLock(void);
#endif /* FLASH_OTPBL_LOCKBL */
+
+#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
+static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig);
+static uint32_t FLASH_OB_SharedRAM_GetConfig(void);
+#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
+
+#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
+static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost);
+static uint32_t FLASH_OB_CPUFreq_GetBoost(void);
+#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
/**
* @}
*/
@@ -187,6 +199,7 @@
}
}
+#if defined (DUAL_BANK)
/* Wait for last operation to be completed on Bank2 */
if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
@@ -195,6 +208,7 @@
status = HAL_ERROR;
}
}
+#endif /* DUAL_BANK */
if(status == HAL_OK)
{
@@ -203,7 +217,7 @@
/* Mass erase to be done */
FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
- /* Wait for last operation to be completed */
+ /* Wait for last operation to be completed on Bank 1 */
if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
{
if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
@@ -213,6 +227,8 @@
/* if the erase operation is completed, disable the Bank1 BER Bit */
FLASH->CR1 &= (~FLASH_CR_BER);
}
+#if defined (DUAL_BANK)
+ /* Wait for last operation to be completed on Bank 2 */
if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
@@ -222,6 +238,7 @@
/* if the erase operation is completed, disable the Bank2 BER Bit */
FLASH->CR2 &= (~FLASH_CR_BER);
}
+#endif /* DUAL_BANK */
}
else
{
@@ -241,6 +258,7 @@
/* If the erase operation is completed, disable the SER Bit */
FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
}
+#if defined (DUAL_BANK)
if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Wait for last operation to be completed */
@@ -249,6 +267,7 @@
/* If the erase operation is completed, disable the SER Bit */
FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
}
+#endif /* DUAL_BANK */
if(status != HAL_OK)
{
@@ -287,7 +306,7 @@
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
- /* Wait for last operation to be completed */
+ /* Wait for last operation to be completed on Bank 1 */
if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
{
if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
@@ -296,6 +315,8 @@
}
}
+#if defined (DUAL_BANK)
+ /* Wait for last operation to be completed on Bank 2 */
if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
@@ -303,6 +324,7 @@
status = HAL_ERROR;
}
}
+#endif /* DUAL_BANK */
if (status != HAL_OK)
{
@@ -322,6 +344,7 @@
FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
#endif /* FLASH_CR_OPERRIE */
}
+#if defined (DUAL_BANK)
if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Enable End of Operation and Error interrupts for Bank 2 */
@@ -333,6 +356,7 @@
FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
#endif /* FLASH_CR_OPERRIE */
}
+#endif /* DUAL_BANK */
if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
{
@@ -341,10 +365,12 @@
{
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1;
}
+#if defined (DUAL_BANK)
else if(pEraseInit->Banks == FLASH_BANK_2)
{
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2;
}
+#endif /* DUAL_BANK */
else
{
pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE;
@@ -355,6 +381,7 @@
else
{
/* Erase by sector to be done */
+#if defined (DUAL_BANK)
if(pEraseInit->Banks == FLASH_BANK_1)
{
pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
@@ -363,6 +390,9 @@
{
pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2;
}
+#else
+ pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
+#endif /* DUAL_BANK */
pFlash.NbSectorsToErase = pEraseInit->NbSectors;
pFlash.Sector = pEraseInit->Sector;
@@ -401,10 +431,12 @@
{
status = HAL_ERROR;
}
+#if defined (DUAL_BANK)
else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
{
status = HAL_ERROR;
}
+#endif /* DUAL_BANK */
else
{
status = HAL_OK;
@@ -491,6 +523,22 @@
FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock);
}
#endif /* FLASH_OTPBL_LOCKBL */
+
+#if defined(FLASH_OPTSR2_TCM_AXI_SHARED)
+ /* TCM / AXI Shared RAM configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_SHARED_RAM) == OPTIONBYTE_SHARED_RAM)
+ {
+ FLASH_OB_SharedRAM_Config(pOBInit->SharedRamConfig);
+ }
+#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
+
+#if defined(FLASH_OPTSR2_CPUFREQ_BOOST)
+ /* CPU Frequency Boost configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_FREQ_BOOST) == OPTIONBYTE_FREQ_BOOST)
+ {
+ FLASH_OB_CPUFreq_BoostConfig(pOBInit->FreqBoostState);
+ }
+#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
}
/* Process Unlocked */
@@ -521,7 +569,11 @@
/*Get BOR Level*/
pOBInit->BORLevel = FLASH_OB_GetBOR();
+#if defined (DUAL_BANK)
if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2))
+#else
+ if (pOBInit->Banks == FLASH_BANK_1)
+#endif /* DUAL_BANK */
{
pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA);
@@ -552,6 +604,20 @@
/* Get OTP Block Lock */
pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock();
#endif /* FLASH_OTPBL_LOCKBL */
+
+#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
+ pOBInit->OptionType |= OPTIONBYTE_SHARED_RAM;
+
+ /* Get TCM / AXI Shared RAM */
+ pOBInit->SharedRamConfig = FLASH_OB_SharedRAM_GetConfig();
+#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
+
+#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
+ pOBInit->OptionType |= OPTIONBYTE_FREQ_BOOST;
+
+ /* Get CPU Frequency Boost */
+ pOBInit->FreqBoostState = FLASH_OB_CPUFreq_GetBoost();
+#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
}
/**
@@ -587,6 +653,7 @@
return HAL_OK;
}
+#if defined (DUAL_BANK)
/**
* @brief Unlock the FLASH Bank2 control registers access
* @retval HAL Status
@@ -619,6 +686,7 @@
SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
return HAL_OK;
}
+#endif /* DUAL_BANK */
/*
* @brief Perform a CRC computation on the specified FLASH memory area
@@ -693,6 +761,7 @@
/* Clear CRC flags */
__HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1);
}
+#if defined (DUAL_BANK)
else
{
/* Enable CRC feature */
@@ -741,6 +810,7 @@
/* Clear CRC flags */
__HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2);
}
+#endif /* DUAL_BANK */
}
return status;
@@ -787,6 +857,7 @@
#endif /* FLASH_CR_PSIZE */
assert_param(IS_FLASH_BANK(Banks));
+#if defined (DUAL_BANK)
/* Flash Mass Erase */
if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
{
@@ -804,6 +875,7 @@
FLASH->OPTCR |= FLASH_OPTCR_MER;
}
else
+#endif /* DUAL_BANK */
{
/* Proceed to erase Flash Bank */
if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
@@ -817,6 +889,8 @@
/* Erase Bank1 */
FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START);
}
+
+#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
#if defined (FLASH_CR_PSIZE)
@@ -828,6 +902,7 @@
/* Erase Bank2 */
FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START);
}
+#endif /* DUAL_BANK */
}
}
@@ -874,6 +949,7 @@
#endif /* FLASH_CR_PSIZE */
}
+#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
#if defined (FLASH_CR_PSIZE)
@@ -888,6 +964,7 @@
FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
#endif /* FLASH_CR_PSIZE */
}
+#endif /* DUAL_BANK */
}
/**
@@ -916,11 +993,13 @@
FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN));
}
+#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Enable Write Protection for bank 2 */
FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN));
}
+#endif /* DUAL_BANK */
}
/**
@@ -949,11 +1028,13 @@
FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN);
}
+#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Disable Write Protection for bank 2 */
FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN);
}
+#endif /* DUAL_BANK */
}
/**
@@ -978,15 +1059,17 @@
{
uint32_t regvalue = 0U;
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+ if(Bank == FLASH_BANK_1)
{
regvalue = FLASH->WPSN_CUR1;
}
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+#if defined (DUAL_BANK)
+ if(Bank == FLASH_BANK_2)
{
regvalue = FLASH->WPSN_CUR2;
}
+#endif /* DUAL_BANK */
(*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN;
@@ -1199,7 +1282,9 @@
optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7);
optr_reg_mask |= FLASH_OPTSR_BCM7;
}
+#endif /* DUAL_CORE */
+#if defined (FLASH_OPTSR_NRST_STOP_D2)
if((UserType & OB_USER_NRST_STOP_D2) != 0U)
{
/* NRST_STOP option byte should be modified */
@@ -1219,7 +1304,9 @@
optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2);
optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2;
}
-#endif /* DUAL_CORE */
+#endif /* FLASH_OPTSR_NRST_STOP_D2 */
+
+#if defined (DUAL_BANK)
if((UserType & OB_USER_SWAP_BANK) != 0U)
{
/* SWAP_BANK_OPT option byte should be modified */
@@ -1229,6 +1316,7 @@
optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT);
optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT;
}
+#endif /* DUAL_BANK */
if((UserType & OB_USER_IOHSLV) != 0U)
{
@@ -1325,6 +1413,7 @@
PCROPConfig;
}
+#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr));
@@ -1335,6 +1424,7 @@
(((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
PCROPConfig;
}
+#endif /* DUAL_BANK */
}
/**
@@ -1360,17 +1450,19 @@
uint32_t regvalue = 0;
uint32_t bankBase = 0;
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+ if(Bank == FLASH_BANK_1)
{
regvalue = FLASH->PRAR_CUR1;
bankBase = FLASH_BANK1_BASE;
}
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+#if defined (DUAL_BANK)
+ if(Bank == FLASH_BANK_2)
{
regvalue = FLASH->PRAR_CUR2;
bankBase = FLASH_BANK2_BASE;
}
+#endif /* DUAL_BANK */
(*PCROPConfig) = (regvalue & FLASH_PRAR_DMEP);
@@ -1561,6 +1653,7 @@
(SecureAreaConfig & FLASH_SCAR_DMES);
}
+#if defined (DUAL_BANK)
if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
{
/* Check the parameters */
@@ -1572,6 +1665,7 @@
(((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
(SecureAreaConfig & FLASH_SCAR_DMES);
}
+#endif /* DUAL_BANK */
}
/**
@@ -1589,17 +1683,19 @@
uint32_t bankBase = 0;
/* Check Bank parameter value */
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+ if(Bank == FLASH_BANK_1)
{
regvalue = FLASH->SCAR_CUR1;
bankBase = FLASH_BANK1_BASE;
}
- if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+#if defined (DUAL_BANK)
+ if(Bank == FLASH_BANK_2)
{
regvalue = FLASH->SCAR_CUR2;
bankBase = FLASH_BANK2_BASE;
}
+#endif /* DUAL_BANK */
/* Get the secure area settings */
(*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES);
@@ -1627,6 +1723,7 @@
/* Select CRC Sector and activate ADD_SECT bit */
FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT;
}
+#if defined (DUAL_BANK)
else
{
/* Clear CRC sector */
@@ -1635,6 +1732,7 @@
/* Select CRC Sector and activate ADD_SECT bit */
FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT;
}
+#endif /* DUAL_BANK */
}
/**
@@ -1655,6 +1753,7 @@
FLASH->CRCSADD1 = CRCStartAddr;
FLASH->CRCEADD1 = CRCEndAddr;
}
+#if defined (DUAL_BANK)
else
{
assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr));
@@ -1664,6 +1763,7 @@
FLASH->CRCSADD2 = CRCStartAddr;
FLASH->CRCEADD2 = CRCEndAddr;
}
+#endif /* DUAL_BANK */
}
/**
* @}
@@ -1696,6 +1796,60 @@
}
#endif /* FLASH_OTPBL_LOCKBL */
+#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
+/**
+ * @brief Configure the TCM / AXI Shared RAM.
+ * @param SharedRamConfig specifies the Shared RAM configuration.
+ * This parameter can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED
+ * @retval None
+ */
+static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_OB_USER_TCM_AXI_SHARED(SharedRamConfig));
+
+ /* Configure the TCM / AXI Shared RAM in the option bytes register */
+ MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_TCM_AXI_SHARED, SharedRamConfig);
+}
+
+/**
+ * @brief Get the TCM / AXI Shared RAM configurtion.
+ * @retval SharedRamConfig returns the TCM / AXI Shared RAM configuration.
+ * This return value can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED
+ */
+static uint32_t FLASH_OB_SharedRAM_GetConfig(void)
+{
+ return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);;
+}
+#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
+
+#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
+/**
+ * @brief Configure the CPU Frequency Boost.
+ * @param FreqBoost specifies the CPU Frequency Boost state.
+ * This parameter can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST
+ * @retval None
+ */
+static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost)
+{
+ /* Check the parameters */
+ assert_param(IS_OB_USER_CPUFREQ_BOOST(FreqBoost));
+
+ /* Configure the CPU Frequency Boost in the option bytes register */
+ MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_CPUFREQ_BOOST, FreqBoost);
+}
+
+/**
+ * @brief Get the CPU Frequency Boost state.
+ * @retval FreqBoost returns the CPU Frequency Boost state.
+ * This return value can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST
+ */
+static uint32_t FLASH_OB_CPUFreq_GetBoost(void)
+{
+ return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);;
+}
+#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
+
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
diff --git a/Src/stm32h7xx_hal_fmac.c b/Src/stm32h7xx_hal_fmac.c
new file mode 100644
index 0000000..9159210
--- /dev/null
+++ b/Src/stm32h7xx_hal_fmac.c
@@ -0,0 +1,2520 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_fmac.c
+ * @author MCD Application Team
+ * @brief FMAC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the FMAC peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Callback functions
+ * + IRQ handler management
+ * + Peripheral State functions
+ *
+ * @verbatim
+================================================================================
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ The FMAC HAL driver can be used as follows:
+
+ (#) Initialize the FMAC low level resources by implementing the HAL_FMAC_MspInit():
+ (++) Enable the FMAC interface clock using __HAL_RCC_FMAC_CLK_ENABLE().
+ (++) In case of using interrupts (e.g. access configured as FMAC_BUFFER_ACCESS_IT):
+ (+++) Configure the FMAC interrupt priority using HAL_NVIC_SetPriority().
+ (+++) Enable the FMAC IRQ handler using HAL_NVIC_EnableIRQ().
+ (+++) In FMAC IRQ handler, call HAL_FMAC_IRQHandler().
+ (++) In case of using DMA to control data transfer (e.g. access configured
+ as FMAC_BUFFER_ACCESS_DMA):
+ (+++) Enable the DMA1 interface clock using __HAL_RCC_DMA1_CLK_ENABLE().
+ (+++) Enable the DMAMUX1 interface clock using __HAL_RCC_DMAMUX1_CLK_ENABLE().
+ (+++) If the initialisation of the internal buffers (coefficients, input,
+ output) is done via DMA, configure and enable one DMA channel for
+ managing data transfer from memory to memory (preload channel).
+ (+++) If the input buffer is accessed via DMA, configure and enable one
+ DMA channel for managing data transfer from memory to peripheral
+ (input channel).
+ (+++) If the output buffer is accessed via DMA, configure and enable
+ one DMA channel for managing data transfer from peripheral to
+ memory (output channel).
+ (+++) Associate the initialized DMA handle(s) to the FMAC DMA handle(s)
+ using __HAL_LINKDMA().
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the enabled DMA channel(s) using HAL_NVIC_SetPriority()
+ and HAL_NVIC_EnableIRQ().
+
+ (#) Initialize the FMAC HAL using HAL_FMAC_Init(). This function
+ resorts to HAL_FMAC_MspInit() for low-level initialization.
+
+ (#) Configure the FMAC processing (filter) using HAL_FMAC_FilterConfig()
+ or HAL_FMAC_FilterConfig_DMA().
+ This function:
+ (++) Defines the memory area within the FMAC internal memory
+ (input, coefficients, output) and the associated threshold (input, output).
+ (++) Configures the filter and its parameters:
+ (+++) Finite Impulse Response (FIR) filter (also known as convolution).
+ (+++) Infinite Impulse Response (IIR) filter (direct form 1).
+ (++) Choose the way to access to the input and output buffers: none, polling,
+ DMA, IT. "none" means the input and/or output data will be handled by
+ another IP (ADC, DAC, etc.).
+ (++) Enable the error interruptions in the input access and/or the output
+ access is done through IT/DMA. If an error occurs, the interruption
+ will be triggered in loop. In order to recover, the user will have
+ to reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
+ Optionally, he can also disable the interrupt using __HAL_FMAC_DISABLE_IT;
+ the error status will be kept, but no more interrupt will be triggered.
+ (++) Write the provided coefficients into the internal memory using polling
+ mode (HAL_FMAC_FilterConfig()) or DMA (HAL_FMAC_FilterConfig_DMA()).
+ In the DMA case, HAL_FMAC_FilterConfigCallback() is called when
+ the handling is over.
+
+ (#) Optionally, the user can enable the error interruption related to
+ saturation by calling __HAL_FMAC_ENABLE_IT. This helps in debugging the
+ filter. If a saturation occurs, the interruption will be triggered in loop.
+ In order to recover, the user will have to:
+ (++) Disable the interruption by calling __HAL_FMAC_DISABLE_IT if
+ he wishes to continue all the same.
+ (++) Reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
+
+ (#) Optionally, preload input (FIR, IIR) and output (IIR) data using
+ HAL_FMAC_FilterPreload() or HAL_FMAC_FilterPreload_DMA().
+ In the DMA case, HAL_FMAC_FilterPreloadCallback() is called when
+ the handling is over.
+ This step is optional as the filter can be started without preloaded
+ data.
+
+ (#) Start the FMAC processing (filter) using HAL_FMAC_FilterStart().
+ This function also configures the output buffer that will be filled from
+ the circular internal output buffer. The function returns immediately
+ without updating the provided buffer. The IP processing will be active until
+ HAL_FMAC_FilterStop() is called.
+
+ (#) If the input internal buffer is accessed via DMA, HAL_FMAC_HalfGetDataCallback()
+ will be called to indicate that half of the input buffer has been handled.
+
+ (#) If the input internal buffer is accessed via DMA or interrupt, HAL_FMAC_GetDataCallback()
+ will be called to require new input data. It will be provided through
+ HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode.
+
+ (#) If the output internal buffer is accessed via DMA, HAL_FMAC_HalfOutputDataReadyCallback()
+ will be called to indicate that half of the output buffer has been handled.
+
+ (#) If the output internal buffer is accessed via DMA or interrupt,
+ HAL_FMAC_OutputDataReadyCallback() will be called to require a new output
+ buffer. It will be provided through HAL_FMAC_ConfigFilterOutputBuffer()
+ if the DMA isn't in circular mode.
+
+ (#) In all modes except none, provide new input data to be processed via HAL_FMAC_AppendFilterData().
+ This function should only be called once the previous input data has been handled
+ (the preloaded input data isn't concerned).
+
+ (#) In all modes except none, provide a new output buffer to be filled via
+ HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous
+ user's output buffer has been filled.
+
+ (#) In polling mode, handle the input and output data using HAL_FMAC_PollFilterData().
+ This function:
+ (++) Write the user's input data (provided via HAL_FMAC_AppendFilterData())
+ into the FMAC input memory area.
+ (++) Read the FMAC output memory area and write it into the user's output buffer.
+ It will return either when:
+ (++) the user's output buffer is filled.
+ (++) the user's input buffer has been handled.
+ The unused data (unread input data or free output data) will not be saved.
+ The user will have to use the updated input and output sizes to keep track
+ of them.
+
+ (#) Stop the FMAC processing (filter) using HAL_FMAC_FilterStop().
+
+ (#) Call HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function
+ resorts to HAL_FMAC_MspDeInit() for low-level de-initialization.
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_FMAC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_FMAC_RegisterCallback() to register a user callback.
+ Function @ref HAL_FMAC_RegisterCallback() allows to register following callbacks:
+ (+) ErrorCallback : Error Callback.
+ (+) HalfGetDataCallback : Get Half Data Callback.
+ (+) GetDataCallback : Get Data Callback.
+ (+) HalfOutputDataReadyCallback : Half Output Data Ready Callback.
+ (+) OutputDataReadyCallback : Output Data Ready Callback.
+ (+) FilterConfigCallback : Filter Configuration Callback.
+ (+) FilterPreloadCallback : Filter Preload Callback.
+ (+) MspInitCallback : FMAC MspInit.
+ (+) MspDeInitCallback : FMAC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_FMAC_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ErrorCallback : Error Callback.
+ (+) HalfGetDataCallback : Get Half Data Callback.
+ (+) GetDataCallback : Get Data Callback.
+ (+) HalfOutputDataReadyCallback : Half Output Data Ready Callback.
+ (+) OutputDataReadyCallback : Output Data Ready Callback.
+ (+) FilterConfigCallback : Filter Configuration Callback.
+ (+) FilterPreloadCallback : Filter Preload Callback.
+ (+) MspInitCallback : FMAC MspInit.
+ (+) MspDeInitCallback : FMAC MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_FMAC_TxCpltCallback(), @ref HAL_FMAC_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_FMAC_Init()
+ and @ref HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_FMAC_Init() and @ref HAL_FMAC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_FMAC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_FMAC_STATE_READY or HAL_FMAC_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_FMAC_RegisterCallback() before calling @ref HAL_FMAC_DeInit()
+ or @ref HAL_FMAC_Init() function.
+
+ [..]
+ When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ @endverbatim
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+#if defined(FMAC)
+#ifdef HAL_FMAC_MODULE_ENABLED
+
+/** @addtogroup STM32H7xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FMAC FMAC
+ * @brief FMAC HAL driver modules
+ * @{
+ */
+
+/* External variables --------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup FMAC_Private_Constants FMAC Private Constants
+ * @{
+ */
+
+#define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)
+#define PRELOAD_ACCESS_DMA 0x00U
+#define PRELOAD_ACCESS_POLLING 0x01U
+#define POLLING_DISABLED 0U
+#define POLLING_ENABLED 1U
+#define POLLING_NOT_STOPPED 0U
+#define POLLING_STOPPED 1U
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FMAC_Private_Macros FMAC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Get the X1 memory area size.
+ * @param __HANDLE__ FMAC handle.
+ * @retval X1_BUF_SIZE
+ */
+#define FMAC_GET_X1_SIZE(__HANDLE__) \
+ ((((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_X1_BUF_SIZE)) >> (FMAC_X1BUFCFG_X1_BUF_SIZE_Pos))
+
+/**
+ * @brief Get the X1 watermark.
+ * @param __HANDLE__ FMAC handle.
+ * @retval FULL_WM
+ */
+#define FMAC_GET_X1_FULL_WM(__HANDLE__) \
+ (((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_FULL_WM))
+
+/**
+ * @brief Get the X2 memory area size.
+ * @param __HANDLE__ FMAC handle.
+ * @retval X2_BUF_SIZE
+ */
+#define FMAC_GET_X2_SIZE(__HANDLE__) \
+ ((((__HANDLE__)->Instance->X2BUFCFG) & (FMAC_X2BUFCFG_X2_BUF_SIZE)) >> (FMAC_X2BUFCFG_X2_BUF_SIZE_Pos))
+
+/**
+ * @brief Get the Y memory area size.
+ * @param __HANDLE__ FMAC handle.
+ * @retval Y_BUF_SIZE
+ */
+#define FMAC_GET_Y_SIZE(__HANDLE__) \
+ ((((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_Y_BUF_SIZE)) >> (FMAC_YBUFCFG_Y_BUF_SIZE_Pos))
+
+/**
+ * @brief Get the Y watermark.
+ * @param __HANDLE__ FMAC handle.
+ * @retval EMPTY_WM
+ */
+#define FMAC_GET_Y_EMPTY_WM(__HANDLE__) \
+ (((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_EMPTY_WM))
+
+/**
+ * @brief Get the start bit state.
+ * @param __HANDLE__ FMAC handle.
+ * @retval START
+ */
+#define FMAC_GET_START_BIT(__HANDLE__) \
+ ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
+
+/**
+ * @brief Get the threshold matching the watermak.
+ * @param __WM__ Watermark value.
+ * @retval THRESHOLD
+ */
+#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) ((__WM__ == FMAC_THRESHOLD_1)? 1U: \
+ (__WM__ == FMAC_THRESHOLD_2)? 2U: \
+ (__WM__ == FMAC_THRESHOLD_4)? 4U:8U)
+
+/**
+ * @brief Check whether the threshold is applicable.
+ * @param __SIZE__ Size of the matching buffer.
+ * @param __WM__ Watermark value.
+ * @param __ACCESS__ Access to the buffer (polling, it, dma, none).
+ * @retval THRESHOLD
+ */
+#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
+ ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
+ ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
+ ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&&((__WM__) == FMAC_THRESHOLD_1))|| \
+ ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+
+static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac);
+static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac);
+static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
+static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
+static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig,
+ uint8_t PreloadAccess);
+static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess);
+static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size);
+static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput,
+ uint16_t *pInputSize);
+static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput,
+ uint16_t *pOutputSize);
+static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite);
+static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead);
+static void FMAC_DMAHalfGetData(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAGetData(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAHalfOutputDataReady(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAOutputDataReady(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma);
+static void FMAC_DMAError(DMA_HandleTypeDef *hdma);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FMAC_Exported_Functions FMAC Exported Functions
+ * @{
+ */
+
+/** @defgroup FMAC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the FMAC peripheral and the associated handle
+ (+) DeInitialize the FMAC peripheral
+ (+) Initialize the FMAC MSP (MCU Specific Package)
+ (+) De-Initialize the FMAC MSP
+
+ [..]
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the FMAC peripheral and the associated handle.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac)
+{
+ /* Check the FMAC handle allocation */
+ if (hfmac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the instance */
+ assert_param(IS_FMAC_ALL_INSTANCE(hfmac->Instance));
+
+ if (hfmac->State == HAL_FMAC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hfmac->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ /* Register the default callback functions */
+ hfmac->ErrorCallback = HAL_FMAC_ErrorCallback;
+ hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback;
+ hfmac->GetDataCallback = HAL_FMAC_GetDataCallback;
+ hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback;
+ hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback;
+ hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback;
+ hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback;
+
+ if (hfmac->MspInitCallback == NULL)
+ {
+ hfmac->MspInitCallback = HAL_FMAC_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hfmac->MspInitCallback(hfmac);
+#else
+ /* Init the low level hardware */
+ HAL_FMAC_MspInit(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+
+ /* Reset pInput and pOutput */
+ hfmac->FilterParam = 0UL;
+ FMAC_ResetDataPointers(hfmac);
+
+ /* Reset FMAC unit (internal pointers) */
+ if (FMAC_Reset(hfmac) == HAL_TIMEOUT)
+ {
+ /* Update FMAC error code and FMAC peripheral state */
+ hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmac);
+
+ return HAL_TIMEOUT;
+ }
+
+ /* Update FMAC error code and FMAC peripheral state */
+ hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmac);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-initialize the FMAC peripheral.
+ * @param hfmac pointer to a FMAC structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac)
+{
+ /* Check the FMAC handle allocation */
+ if (hfmac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FMAC_ALL_INSTANCE(hfmac->Instance));
+
+ /* Change FMAC peripheral state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
+ /* Set FMAC error code to none */
+ hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
+
+ /* Reset pInput and pOutput */
+ hfmac->FilterParam = 0UL;
+ FMAC_ResetDataPointers(hfmac);
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ if (hfmac->MspDeInitCallback == NULL)
+ {
+ hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hfmac->MspDeInitCallback(hfmac);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC, DMA */
+ HAL_FMAC_MspDeInit(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+
+ /* Change FMAC peripheral state */
+ hfmac->State = HAL_FMAC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the FMAC MSP.
+ * @param hfmac FMAC handle.
+ * @retval None
+ */
+__weak void HAL_FMAC_MspInit(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMAC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-initialize the FMAC MSP.
+ * @param hfmac FMAC handle.
+ * @retval None
+ */
+__weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMAC_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User FMAC Callback
+ * to be used instead of the weak predefined callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param CallbackID ID of the callback to be registered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FMAC_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_FMAC_HALF_GET_DATA_CB_ID Get Half Data Callback ID
+ * @arg @ref HAL_FMAC_GET_DATA_CB_ID Get Data Callback ID
+ * @arg @ref HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID Half Output Data Ready Callback ID
+ * @arg @ref HAL_FMAC_OUTPUT_DATA_READY_CB_ID Output Data Ready Callback ID
+ * @arg @ref HAL_FMAC_FILTER_CONFIG_CB_ID Filter Configuration Callback ID
+ * @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
+ * @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
+ * @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
+ * @param pCallback pointer to the Callback function.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
+ pFMAC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hfmac);
+
+ if (HAL_FMAC_STATE_READY == hfmac->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMAC_ERROR_CB_ID :
+ hfmac->ErrorCallback = pCallback;
+ break;
+
+ case HAL_FMAC_HALF_GET_DATA_CB_ID :
+ hfmac->HalfGetDataCallback = pCallback;
+ break;
+
+ case HAL_FMAC_GET_DATA_CB_ID :
+ hfmac->GetDataCallback = pCallback;
+ break;
+
+ case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID :
+ hfmac->HalfOutputDataReadyCallback = pCallback;
+ break;
+
+ case HAL_FMAC_OUTPUT_DATA_READY_CB_ID :
+ hfmac->OutputDataReadyCallback = pCallback;
+ break;
+
+ case HAL_FMAC_FILTER_CONFIG_CB_ID :
+ hfmac->FilterConfigCallback = pCallback;
+ break;
+
+ case HAL_FMAC_FILTER_PRELOAD_CB_ID :
+ hfmac->FilterPreloadCallback = pCallback;
+ break;
+
+ case HAL_FMAC_MSPINIT_CB_ID :
+ hfmac->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FMAC_MSPDEINIT_CB_ID :
+ hfmac->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_FMAC_STATE_RESET == hfmac->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMAC_MSPINIT_CB_ID :
+ hfmac->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FMAC_MSPDEINIT_CB_ID :
+ hfmac->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmac);
+
+ return status;
+}
+
+/**
+ * @brief Unregister a FMAC CallBack.
+ * FMAC callback is redirected to the weak predefined callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module
+ * @param CallbackID ID of the callback to be unregistered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FMAC_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_FMAC_HALF_GET_DATA_CB_ID Get Half Data Callback ID
+ * @arg @ref HAL_FMAC_GET_DATA_CB_ID Get Data Callback ID
+ * @arg @ref HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID Half Output Data Ready Callback ID
+ * @arg @ref HAL_FMAC_OUTPUT_DATA_READY_CB_ID Output Data Ready Callback ID
+ * @arg @ref HAL_FMAC_FILTER_CONFIG_CB_ID Filter Configuration Callback ID
+ * @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
+ * @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
+ * @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hfmac);
+
+ if (HAL_FMAC_STATE_READY == hfmac->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMAC_ERROR_CB_ID :
+ hfmac->ErrorCallback = HAL_FMAC_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_FMAC_HALF_GET_DATA_CB_ID :
+ hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback; /* Legacy weak HalfGetDataCallback */
+ break;
+
+ case HAL_FMAC_GET_DATA_CB_ID :
+ hfmac->GetDataCallback = HAL_FMAC_GetDataCallback; /* Legacy weak GetDataCallback */
+ break;
+
+ case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID :
+ hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak HalfOutputDataReadyCallback */
+ break;
+
+ case HAL_FMAC_OUTPUT_DATA_READY_CB_ID :
+ hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback; /* Legacy weak OutputDataReadyCallback */
+ break;
+
+ case HAL_FMAC_FILTER_CONFIG_CB_ID :
+ hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback; /* Legacy weak FilterConfigCallback */
+ break;
+
+ case HAL_FMAC_FILTER_PRELOAD_CB_ID :
+ hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback; /* Legacy weak FilterPreloadCallback */
+ break;
+
+ case HAL_FMAC_MSPINIT_CB_ID :
+ hfmac->MspInitCallback = HAL_FMAC_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_FMAC_MSPDEINIT_CB_ID :
+ hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_FMAC_STATE_RESET == hfmac->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMAC_MSPINIT_CB_ID :
+ hfmac->MspInitCallback = HAL_FMAC_MspInit;
+ break;
+
+ case HAL_FMAC_MSPDEINIT_CB_ID :
+ hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmac);
+
+ return status;
+}
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Control functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the FMAC peripheral: memory area, filter type and parameters,
+ way to access to the input and output memory area (none, polling, IT, DMA).
+ (+) Start the FMAC processing (filter).
+ (+) Handle the input data that will be provided into FMAC.
+ (+) Handle the output data provided by FMAC.
+ (+) Stop the FMAC processing (filter).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the FMAC filter according to the parameters
+ * specified in the FMAC_FilterConfigTypeDef structure.
+ * The provided data will be loaded using polling mode.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * contains the FMAC configuration information.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig)
+{
+ return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_POLLING));
+}
+
+/**
+ * @brief Configure the FMAC filter according to the parameters
+ * specified in the FMAC_FilterConfigTypeDef structure.
+ * The provided data will be loaded using DMA.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * contains the FMAC configuration information.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig)
+{
+ return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_DMA));
+}
+
+/**
+ * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
+ * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+ * The provided data will be loaded using polling mode.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pInput Preloading of the first elements of the input buffer (X1).
+ * If not needed (no data available when starting), it should be set to NULL.
+ * @param InputSize Size of the input vector.
+ * As pInput is used for preloading data, it cannot be bigger than the input memory area.
+ * @param pOutput [IIR] Preloading of the first elements of the output vector (Y).
+ * If not needed, it should be set to NULL.
+ * @param OutputSize Size of the output vector.
+ * As pOutput is used for preloading data, it cannot be bigger than the output memory area.
+ * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+ * (each call filling partly the buffers). In case of overflow (too much data provided through
+ * all these calls), an error will be returned.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize)
+{
+ return (FMAC_FilterPreload(hfmac, pInput, InputSize, pOutput, OutputSize, PRELOAD_ACCESS_POLLING));
+}
+
+/**
+ * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
+ * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+ * The provided data will be loaded using DMA.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pInput Preloading of the first elements of the input buffer (X1).
+ * If not needed (no data available when starting), it should be set to NULL.
+ * @param InputSize Size of the input vector.
+ * As pInput is used for preloading data, it cannot be bigger than the input memory area.
+ * @param pOutput [IIR] Preloading of the first elements of the output vector (Y).
+ * If not needed, it should be set to NULL.
+ * @param OutputSize Size of the output vector.
+ * As pOutput is used for preloading data, it cannot be bigger than the output memory area.
+ * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+ * (each call filling partly the buffers). In case of overflow (too much data provided through
+ * all these calls), an error will be returned.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize)
+{
+ return (FMAC_FilterPreload(hfmac, pInput, InputSize, pOutput, OutputSize, PRELOAD_ACCESS_DMA));
+}
+
+
+/**
+ * @brief Start the FMAC processing according to the existing FMAC configuration.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pOutput pointer to buffer where output data of FMAC processing will be stored
+ * in the next steps.
+ * If it is set to NULL, the output will not be read and it will be up to
+ * an external IP to empty the output buffer.
+ * @param pOutputSize pointer to the size of the output buffer. The number of read data will be written here.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
+{
+ uint32_t tmpcr = 0UL;
+ HAL_StatusTypeDef status;
+
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) != 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check that a valid configuration was done previously */
+ if (hfmac->FilterParam == 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hfmac->State == HAL_FMAC_STATE_READY)
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
+ /* CR: Configure the input access (error interruptions enabled only for IT or DMA) */
+ if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA)
+ {
+ tmpcr |= FMAC_DMA_WEN;
+ }
+ else if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_IT)
+ {
+ tmpcr |= FMAC_IT_WIEN;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* CR: Configure the output access (error interruptions enabled only for IT or DMA) */
+ if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA)
+ {
+ tmpcr |= FMAC_DMA_REN;
+ }
+ else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT)
+ {
+ tmpcr |= FMAC_IT_RIEN;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* CR: Write the configuration */
+ MODIFY_REG(hfmac->Instance->CR, \
+ FMAC_IT_RIEN | FMAC_IT_WIEN | FMAC_DMA_REN | FMAC_CR_DMAWEN, \
+ tmpcr);
+
+ /* Register the new output buffer */
+ status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize);
+
+ if (status == HAL_OK)
+ {
+ /* PARAM: Start the filter ( this can generate interrupts before the end of the HAL_FMAC_FilterStart ) */
+ WRITE_REG(hfmac->Instance->PARAM, (uint32_t)(hfmac->FilterParam));
+ }
+
+ /* Reset the busy flag (do not overwrite the possible write and read flag) */
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ /* Return function status */
+ return status;
+ }
+ else
+ {
+ /* Return function status */
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Provide a new input buffer that will be loaded into the FMAC
+ * input memory area.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pInput New input vector (additional input data).
+ * @param pInputSize Size of the input vector (if all the data can't be
+ * written, it will be updated with the number of data read from FMAC).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
+{
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) == 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the function parameters */
+ if ((pInput == NULL) || (pInputSize == NULL))
+ {
+ return HAL_ERROR;
+ }
+ if (*pInputSize == 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the FMAC configuration */
+ if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_NONE)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check whether the previous input vector has been handled */
+ if ((hfmac->pInputSize != NULL) && (hfmac->InputCurrentSize < * (hfmac->pInputSize)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check that FMAC was initialized and that no writing is already ongoing */
+ if (hfmac->WrState == HAL_FMAC_STATE_READY)
+ {
+ /* Register the new input buffer */
+ return (FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize));
+ }
+ else
+ {
+ /* Return function status */
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Provide a new output buffer to be filled with the data
+ * computed by FMAC unit.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pOutput New output vector.
+ * @param pOutputSize Size of the output vector (if the vector can't
+ * be entirely filled, pOutputSize will be updated with the number
+ * of data read from FMAC).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
+{
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) == 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the function parameters */
+ if ((pOutput == NULL) || (pOutputSize == NULL))
+ {
+ return HAL_ERROR;
+ }
+ if (*pOutputSize == 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the FMAC configuration */
+ if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check whether the previous output vector has been handled */
+ if ((hfmac->pOutputSize != NULL) && (hfmac->OutputCurrentSize < * (hfmac->pOutputSize)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check that FMAC was initialized and that not reading is already ongoing */
+ if (hfmac->RdState == HAL_FMAC_STATE_READY)
+ {
+ /* Register the new output buffer */
+ return (FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize));
+ }
+ else
+ {
+ /* Return function status */
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Write the previously provided user's input data and
+ * fill the previously provided user's output buffer,
+ * according to the existing FMAC configuration (polling mode only).
+ * The function returns when the input data has been handled or
+ * when the output data is filled. The possible unused data isn't
+ * kept. It will be up to the user to handle it. The previously
+ * provided pInputSize and pOutputSize will be used to indicate to the
+ * size of the read/written data to the user.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param Timeout timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint8_t inpolling;
+ uint8_t inpollingover = POLLING_NOT_STOPPED;
+ uint8_t outpolling;
+ uint8_t outpollingover = POLLING_NOT_STOPPED;
+
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) == 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the configuration */
+
+ /* Get the input and output mode (if no buffer was previously provided, nothing will be read/written) */
+ if ((hfmac->InputAccess == FMAC_BUFFER_ACCESS_POLLING) && (hfmac->pInput != NULL))
+ {
+ inpolling = POLLING_ENABLED;
+ }
+ else
+ {
+ inpolling = POLLING_DISABLED;
+ }
+ if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_POLLING) && (hfmac->pOutput != NULL))
+ {
+ outpolling = POLLING_ENABLED;
+ }
+ else
+ {
+ outpolling = POLLING_DISABLED;
+ }
+
+ /* Check the configuration */
+ if ((inpolling == POLLING_DISABLED) && (outpolling == POLLING_DISABLED))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hfmac->State == HAL_FMAC_STATE_READY)
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Loop on reading and writing until timeout */
+ while ((HAL_GetTick() - tickstart) < Timeout)
+ {
+ /* X1: Check the mode: polling or none */
+ if (inpolling != POLLING_DISABLED)
+ {
+ FMAC_WriteDataIncrementPtr(hfmac, MAX_FILTER_DATA_SIZE_TO_HANDLE);
+ if (hfmac->InputCurrentSize == *(hfmac->pInputSize))
+ {
+ inpollingover = POLLING_STOPPED;
+ }
+ }
+
+ /* Y: Check the mode: polling or none */
+ if (outpolling != POLLING_DISABLED)
+ {
+ FMAC_ReadDataIncrementPtr(hfmac, MAX_FILTER_DATA_SIZE_TO_HANDLE);
+ if (hfmac->OutputCurrentSize == *(hfmac->pOutputSize))
+ {
+ outpollingover = POLLING_STOPPED;
+ }
+ }
+
+ /* Exit if there isn't data to handle anymore on one side or another */
+ if ((inpollingover != POLLING_NOT_STOPPED) || (outpollingover != POLLING_NOT_STOPPED))
+ {
+ break;
+ }
+ }
+
+ /* Change the FMAC state; update the input and output sizes; reset the indexes */
+ if (inpolling != POLLING_DISABLED)
+ {
+ (*(hfmac->pInputSize)) = hfmac->InputCurrentSize;
+ FMAC_ResetInputStateAndDataPointers(hfmac);
+ }
+ if (outpolling != POLLING_DISABLED)
+ {
+ (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize;
+ FMAC_ResetOutputStateAndDataPointers(hfmac);
+ }
+
+ /* Reset the busy flag (do not overwrite the possible write and read flag) */
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ /* Return function status */
+ if ((HAL_GetTick() - tickstart) >= Timeout)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ /* Return function status */
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Stop the FMAC processing.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac)
+{
+
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) == 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hfmac->State == HAL_FMAC_STATE_READY)
+ {
+ /* Set the START bit to 0 (stop the previously configured filter) */
+ CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START);
+
+ /* Disable the interrupts in order to avoid crossing cases */
+ CLEAR_BIT(hfmac->Instance->CR, FMAC_DMA_REN | FMAC_DMA_WEN | FMAC_IT_RIEN | FMAC_IT_WIEN);
+
+ /* In case of IT, update the sizes */
+ if ((hfmac->InputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pInput != NULL))
+ {
+ (*(hfmac->pInputSize)) = hfmac->InputCurrentSize;
+ }
+ if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL))
+ {
+ (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize;
+ }
+
+ /* Reset FMAC unit (internal pointers) */
+ if (FMAC_Reset(hfmac) == HAL_TIMEOUT)
+ {
+ /* Update FMAC error code and FMAC peripheral state */
+ hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+
+ /* Reset the data pointers */
+ FMAC_ResetDataPointers(hfmac);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Return function status */
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Exported_Functions_Group3 Callback functions
+ * @brief Callback functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..] This section provides Interruption and DMA callback functions:
+ (+) DMA or Interrupt: the user's input data is half written (DMA only)
+ or completely written.
+ (+) DMA or Interrupt: the user's output buffer is half filled (DMA only)
+ or completely filled.
+ (+) DMA or Interrupt: error handling.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief FMAC error callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_ErrorCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC get half data callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_HalfGetDataCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_HalfGetDataCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC get data callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_GetDataCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_GetDataCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC half output data ready callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_HalfOutputDataReadyCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_HalfOutputDataReadyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC output data ready callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_OutputDataReadyCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_OutputDataReadyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC filter configuration callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_FilterConfigCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_FilterConfigCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief FMAC filter preload callback.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+__weak void HAL_FMAC_FilterPreloadCallback(FMAC_HandleTypeDef *hfmac)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmac);
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_FMAC_FilterPreloadCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Exported_Functions_Group4 IRQ handler management
+ * @brief IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+[..] This section provides IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle FMAC interrupt request.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval None
+ */
+void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac)
+{
+ uint32_t itsource;
+
+ /* Check if the read interrupt is enabled and if Y buffer empty flag isn't set */
+ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_RIEN);
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0UL))
+ {
+ /* Read some data if possible (Y size is used as a pseudo timeout in order
+ to not get stuck too long under IT if FMAC keeps on processing input
+ data reloaded via DMA for instance). */
+ if (hfmac->pOutput != NULL)
+ {
+ FMAC_ReadDataIncrementPtr(hfmac, (uint16_t)FMAC_GET_Y_SIZE(hfmac));
+ }
+
+ /* Indicate that data is ready to be read */
+ if ((hfmac->pOutput == NULL) || (hfmac->OutputCurrentSize == *(hfmac->pOutputSize)))
+ {
+ /* Reset the pointers to indicate new data will be needed */
+ FMAC_ResetOutputStateAndDataPointers(hfmac);
+
+ /* Call the output data ready callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->OutputDataReadyCallback(hfmac);
+#else
+ HAL_FMAC_OutputDataReadyCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Check if the write interrupt is enabled and if X1 buffer full flag isn't set */
+ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_WIEN);
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0UL))
+ {
+ /* Write some data if possible (X1 size is used as a pseudo timeout in order
+ to not get stuck too long under IT if FMAC keep on processing input
+ data whereas its output emptied via DMA for instance). */
+ if (hfmac->pInput != NULL)
+ {
+ FMAC_WriteDataIncrementPtr(hfmac, (uint16_t)FMAC_GET_X1_SIZE(hfmac));
+ }
+
+ /* Indicate that new data will be needed */
+ if ((hfmac->pInput == NULL) || (hfmac->InputCurrentSize == *(hfmac->pInputSize)))
+ {
+ /* Reset the pointers to indicate new data will be needed */
+ FMAC_ResetInputStateAndDataPointers(hfmac);
+
+ /* Call the get data callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->GetDataCallback(hfmac);
+#else
+ HAL_FMAC_GetDataCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Check if the overflow error interrupt is enabled and if overflow error flag is raised */
+ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_OVFLIEN);
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0UL))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
+ }
+
+ /* Check if the underflow error interrupt is enabled and if underflow error flag is raised */
+ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_UNFLIEN);
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0UL))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
+ }
+
+ /* Check if the saturation error interrupt is enabled and if saturation error flag is raised */
+ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_SATIEN);
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0UL))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
+ }
+
+ /* Call the error callback if an error occurred */
+ if (hfmac->ErrorCode != HAL_FMAC_ERROR_NONE)
+ {
+ /* Call the error callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->ErrorCallback(hfmac);
+#else
+ HAL_FMAC_ErrorCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the FMAC handle state.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @retval HAL state
+ */
+HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac)
+{
+ /* Return FMAC handle state */
+ return hfmac->State;
+}
+
+/**
+ * @brief Return the FMAC peripheral error.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @note The returned error is a bit-map combination of possible errors.
+ * @retval Error bit-map
+ */
+uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac)
+{
+ /* Return FMAC error code */
+ return hfmac->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_Private_Functions FMAC Private Functions
+ * @{
+ */
+
+/**
+ ==============================================================================
+ ##### FMAC Private Functions #####
+ ==============================================================================
+ */
+/**
+ * @brief Perform a reset of the FMAC unit.
+ * @param hfmac FMAC handle.
+ * @retval FMAC status
+ */
+static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac)
+{
+ uint32_t tickstart;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Perform the reset */
+ SET_BIT(hfmac->Instance->CR, FMAC_CR_RESET);
+
+ /* Wait until flag is reset */
+ while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the data pointers of the FMAC unit.
+ * @param hfmac FMAC handle.
+ * @retval FMAC status
+ */
+static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac)
+{
+ FMAC_ResetInputStateAndDataPointers(hfmac);
+ FMAC_ResetOutputStateAndDataPointers(hfmac);
+}
+
+/**
+ * @brief Reset the input data pointers of the FMAC unit.
+ * @param hfmac FMAC handle.
+ * @retval FMAC status
+ */
+static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
+{
+ hfmac->pInput = NULL;
+ hfmac->pInputSize = NULL;
+ hfmac->InputCurrentSize = 0U;
+ hfmac->WrState = HAL_FMAC_STATE_READY;
+}
+
+/**
+ * @brief Reset the output data pointers of the FMAC unit.
+ * @param hfmac FMAC handle.
+ * @retval FMAC status
+ */
+static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
+{
+ hfmac->pOutput = NULL;
+ hfmac->pOutputSize = NULL;
+ hfmac->OutputCurrentSize = 0U;
+ hfmac->RdState = HAL_FMAC_STATE_READY;
+}
+
+/**
+ * @brief Configure the FMAC filter according to the parameters
+ specified in the FMAC_FilterConfigTypeDef structure.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * contains the FMAC configuration information.
+ * @param PreloadAccess buffer preload method
+ * This parameter can be one of the following values:
+ * @arg @ref PRELOAD_ACCESS_POLLING preloading using CPU
+ * @arg @ref PRELOAD_ACCESS_DMA Get preloading using DMA
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig,
+ uint8_t PreloadAccess)
+{
+ uint32_t tickstart;
+ uint32_t tmpcr;
+#if defined(USE_FULL_ASSERT)
+ uint32_t x2size;
+#endif /* USE_FULL_ASSERT */
+
+ /* Check the parameters */
+ assert_param(IS_FMAC_THRESHOLD(sConfig->InputThreshold));
+ assert_param(IS_FMAC_THRESHOLD(sConfig->OutputThreshold));
+ assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->InputAccess));
+ assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->OutputAccess));
+ assert_param(IS_FMAC_CLIP_STATE(sConfig->Clip));
+ assert_param(IS_FMAC_FILTER_FUNCTION(sConfig->Filter));
+ assert_param(IS_FMAC_PARAM_P(sConfig->Filter, sConfig->P));
+ assert_param(IS_FMAC_PARAM_Q(sConfig->Filter, sConfig->Q));
+ assert_param(IS_FMAC_PARAM_R(sConfig->Filter, sConfig->R));
+
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) != 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hfmac->State == HAL_FMAC_STATE_READY)
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Indicate that there is no valid configuration done */
+ hfmac->FilterParam = 0UL;
+
+ /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */
+ if (sConfig->InputBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->X1BUFCFG, \
+ (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \
+ (((((uint32_t)(sConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \
+ ((((uint32_t)(sConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & FMAC_X1BUFCFG_X1_BUF_SIZE)));
+ }
+
+ /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */
+ if (sConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE)
+ {
+ /* Check the parameter */
+ assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), sConfig->InputThreshold, sConfig->InputAccess));
+
+ MODIFY_REG(hfmac->Instance->X1BUFCFG, \
+ FMAC_X1BUFCFG_FULL_WM, \
+ ((sConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM));
+ }
+
+ /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */
+ if (sConfig->CoeffBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->X2BUFCFG, \
+ (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \
+ (((((uint32_t)(sConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \
+ ((((uint32_t)(sConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) & FMAC_X2BUFCFG_X2_BUF_SIZE)));
+ }
+
+ /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */
+ if (sConfig->OutputBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->YBUFCFG, \
+ (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE), \
+ (((((uint32_t)(sConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos) & FMAC_YBUFCFG_Y_BASE) | \
+ ((((uint32_t)(sConfig->OutputBufferSize)) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE)));
+ }
+
+ /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */
+ if (sConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE)
+ {
+ /* Check the parameter */
+ assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), sConfig->OutputThreshold, sConfig->OutputAccess));
+
+ MODIFY_REG(hfmac->Instance->YBUFCFG, \
+ FMAC_YBUFCFG_EMPTY_WM, \
+ ((sConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM));
+ }
+
+ /* CR: Configure the clip feature */
+ tmpcr = sConfig->Clip & FMAC_CR_CLIPEN;
+
+ /* CR: If IT or DMA will be used, enable error interrupts.
+ * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */
+ if ((sConfig->InputAccess == FMAC_BUFFER_ACCESS_DMA) || (sConfig->InputAccess == FMAC_BUFFER_ACCESS_IT) ||
+ (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT))
+ {
+ tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN;
+ }
+
+ /* CR: write the value */
+ WRITE_REG(hfmac->Instance->CR, tmpcr);
+
+ /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */
+ hfmac->InputAccess = sConfig->InputAccess;
+ hfmac->OutputAccess = sConfig->OutputAccess;
+
+ /* Check whether the configured X2 is big enough for the filter */
+#if defined(USE_FULL_ASSERT)
+ x2size = FMAC_GET_X2_SIZE(hfmac);
+#endif /* USE_FULL_ASSERT */
+ assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= sConfig->P)) || \
+ ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && (x2size >= ((uint32_t)sConfig->P + (uint32_t)sConfig->Q))));
+
+ /* Build the PARAM value that will be used when starting the filter */
+ hfmac->FilterParam = (FMAC_PARAM_START | sConfig->Filter | \
+ ((((uint32_t)(sConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \
+ ((((uint32_t)(sConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \
+ ((((uint32_t)(sConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R));
+
+ /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */
+ if ((sConfig->pCoeffB != NULL) && (sConfig->CoeffBSize != 0U))
+ {
+ /* FIR/IIR: The provided coefficients should match X2 size */
+ assert_param(((uint32_t)sConfig->CoeffASize + (uint32_t)sConfig->CoeffBSize) <= x2size);
+ /* FIR/IIR: The size of pCoeffB should match the parameter P */
+ assert_param(sConfig->CoeffBSize >= sConfig->P);
+ /* pCoeffA should be provided for IIR but not for FIR */
+ /* IIR : if pCoeffB is provided, pCoeffA should also be there */
+ /* IIR: The size of pCoeffA should match the parameter Q */
+ assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) &&
+ (sConfig->pCoeffA == NULL) && (sConfig->CoeffASize == 0U)) ||
+ ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) &&
+ (sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U) &&
+ (sConfig->CoeffASize >= sConfig->Q)));
+
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)(sConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \
+ ((uint32_t)(sConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \
+ FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ {
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffB), sConfig->CoeffBSize);
+
+ /* Load pCoeffA if needed */
+ if ((sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U))
+ {
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffA), sConfig->CoeffASize);
+ }
+
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+ }
+ else
+ {
+ hfmac->pInput = sConfig->pCoeffA;
+ hfmac->InputCurrentSize = sConfig->CoeffASize;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)sConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA,
+ sConfig->CoeffBSize));
+ }
+ }
+ else
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+ }
+ }
+ else
+ {
+ /* Return function status */
+ return HAL_BUSY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
+ * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pInput Preloading of the first elements of the input buffer (X1).
+ * If not needed (no data available when starting), it should be set to NULL.
+ * @param InputSize Size of the input vector.
+ * As pInput is used for preloading data, it cannot be bigger than the input memory area.
+ * @param pOutput [IIR] Preloading of the first elements of the output vector (Y).
+ * If not needed, it should be set to NULL.
+ * @param OutputSize Size of the output vector.
+ * As pOutput is used for preloading data, it cannot be bigger than the output memory area.
+ * @param PreloadAccess buffer preload method
+ * This parameter can be one of the following values:
+ * @arg @ref PRELOAD_ACCESS_POLLING preloading using CPU
+ * @arg @ref PRELOAD_ACCESS_DMA Get preloading using DMA
+ * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+ * (each call filling partly the buffers). In case of overflow (too much data provided through
+ * all these calls), an error will be returned.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
+ int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess)
+{
+ uint32_t tickstart;
+
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) != 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check that a valid configuration was done previously */
+ if (hfmac->FilterParam == 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the preload input buffers isn't too big */
+ if ((InputSize > FMAC_GET_X1_SIZE(hfmac)) && (pInput != NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the preload output buffer isn't too big */
+ if ((OutputSize > FMAC_GET_Y_SIZE(hfmac)) && (pOutput != NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check handle state is ready */
+ if (hfmac->State == HAL_FMAC_STATE_READY)
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Preload the input buffer if required */
+ if ((pInput != NULL) && (InputSize != 0U))
+ {
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ {
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize);
+
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ hfmac->pInput = pOutput;
+ hfmac->InputCurrentSize = OutputSize;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize));
+ }
+ }
+
+ /* Preload the output buffer if required */
+ if ((pOutput != NULL) && (OutputSize != 0U))
+ {
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ {
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize);
+
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ hfmac->pInput = NULL;
+ hfmac->InputCurrentSize = 0U;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize));
+ }
+ }
+
+ /* Update the error codes */
+ if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
+ }
+ if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
+ }
+
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ /* Return function status */
+ if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Return function status */
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Write data into FMAC internal memory through WDATA and increment input buffer pointer.
+ * This function is only used with preload functions.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param ppData pointer to pointer to the data buffer.
+ * @param Size size of the data buffer.
+ * @retval none
+ */
+static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size)
+{
+ uint8_t index;
+
+ /* Load the buffer into the internal memory */
+ for (index = Size; index > 0U; index--)
+ {
+ WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(*ppData))) & FMAC_WDATA_WDATA));
+ (*ppData)++;
+ }
+}
+
+/**
+ * @brief Handle FMAC Function Timeout.
+ * @param hfmac FMAC handle.
+ * @param Tickstart Tick start value.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag changes */
+ while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+ {
+ if ((HAL_GetTick() - Tickstart) > Timeout)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmac);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Register the new input buffer, update DMA configuration
+ * if needed and change the FMAC state.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pInput New input vector (additional input data).
+ * @param pInputSize Size of the input vector (if all the data can't be
+ * written, it will be updated with the number of data read from FMAC).
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput,
+ uint16_t *pInputSize)
+{
+ /* Change the FMAC state */
+ hfmac->WrState = HAL_FMAC_STATE_BUSY_WR;
+
+ /* Reset the current size */
+ hfmac->InputCurrentSize = 0U;
+
+ /* Handle the pointer depending on the input access */
+ if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA)
+ {
+ hfmac->pInput = NULL;
+ hfmac->pInputSize = NULL;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaIn->XferHalfCpltCallback = FMAC_DMAHalfGetData;
+ hfmac->hdmaIn->XferCpltCallback = FMAC_DMAGetData;
+ /* Set the DMA error callback */
+ hfmac->hdmaIn->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC input data write */
+ return (HAL_DMA_Start_IT(hfmac->hdmaIn, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, *pInputSize));
+ }
+ else
+ {
+ /* Update the input data information (polling, IT) */
+ hfmac->pInput = pInput;
+ hfmac->pInputSize = pInputSize;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Register the new output buffer, update DMA configuration
+ * if needed and change the FMAC state.
+ * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
+ * the configuration information for FMAC module.
+ * @param pOutput New output vector.
+ * @param pOutputSize Size of the output vector (if the vector can't
+ * be entirely filled, pOutputSize will be updated with the number
+ * of data read from FMAC).
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput,
+ uint16_t *pOutputSize)
+{
+ /* Reset the current size */
+ hfmac->OutputCurrentSize = 0U;
+
+ /* Check whether a valid pointer was provided */
+ if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0UL))
+ {
+ /* The user will have to provide a valid configuration later */
+ hfmac->pOutput = NULL;
+ hfmac->pOutputSize = NULL;
+ hfmac->RdState = HAL_FMAC_STATE_READY;
+ }
+ /* Handle the pointer depending on the input access */
+ else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA)
+ {
+ hfmac->pOutput = NULL;
+ hfmac->pOutputSize = NULL;
+ hfmac->RdState = HAL_FMAC_STATE_BUSY_RD;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaOut->XferHalfCpltCallback = FMAC_DMAHalfOutputDataReady;
+ hfmac->hdmaOut->XferCpltCallback = FMAC_DMAOutputDataReady;
+ /* Set the DMA error callback */
+ hfmac->hdmaOut->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC output data read */
+ return (HAL_DMA_Start_IT(hfmac->hdmaOut, (uint32_t)&hfmac->Instance->RDATA, (uint32_t)pOutput, *pOutputSize));
+ }
+ else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE)
+ {
+ hfmac->pOutput = NULL;
+ hfmac->pOutputSize = NULL;
+ hfmac->RdState = HAL_FMAC_STATE_READY;
+ }
+ else
+ {
+ /* Update the output data information (polling, IT) */
+ hfmac->pOutput = pOutput;
+ hfmac->pOutputSize = pOutputSize;
+ hfmac->RdState = HAL_FMAC_STATE_BUSY_RD;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Read available output data until Y EMPTY is set.
+ * @param hfmac FMAC handle.
+ * @param MaxSizeToRead Maximum number of data to read (this serves as a timeout
+ * if FMAC continuously writes into the output buffer).
+ * @retval HAL status
+ */
+static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead)
+{
+ uint16_t maxsize;
+ uint16_t threshold;
+ uint32_t tmpvalue;
+
+ /* Check if there is data to read */
+ if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0UL)
+ {
+ return;
+ }
+
+ /* Get the maximum index (no wait allowed, no overstepping of the output buffer) */
+ if ((hfmac->OutputCurrentSize + MaxSizeToRead) > *(hfmac->pOutputSize))
+ {
+ maxsize = *(hfmac->pOutputSize);
+ }
+ else
+ {
+ maxsize = hfmac->OutputCurrentSize + MaxSizeToRead;
+ }
+
+ /* Read until there is no more room or no more data */
+ do
+ {
+ /* If there is no more room, return */
+ if (!(hfmac->OutputCurrentSize < maxsize))
+ {
+ return;
+ }
+
+ /* Read the available data */
+ tmpvalue = ((READ_REG(hfmac->Instance->RDATA))& FMAC_RDATA_RDATA);
+ *(hfmac->pOutput) = (int16_t)tmpvalue;
+ hfmac->pOutput++;
+ hfmac->OutputCurrentSize++;
+ } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0UL);
+
+ /* Y buffer empty flag has just be raised, read the threshold */
+ threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_Y_EMPTY_WM(hfmac)) - 1U;
+
+ /* Update the maximum size if needed (limited data available) */
+ if ((hfmac->OutputCurrentSize + threshold) < maxsize)
+ {
+ maxsize = hfmac->OutputCurrentSize + threshold;
+ }
+
+ /* Read the available data */
+ while (hfmac->OutputCurrentSize < maxsize)
+ {
+ tmpvalue = ((READ_REG(hfmac->Instance->RDATA))& FMAC_RDATA_RDATA);
+ *(hfmac->pOutput) = (int16_t)tmpvalue;
+ hfmac->pOutput++;
+ hfmac->OutputCurrentSize++;
+ }
+}
+
+/**
+ * @brief Write available input data until X1 FULL is set.
+ * @param hfmac FMAC handle.
+ * @param MaxSizeToWrite Maximum number of data to write (this serves as a timeout
+ * if FMAC continuously empties the input buffer).
+ * @retval HAL status
+ */
+static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite)
+{
+ uint16_t maxsize;
+ uint16_t threshold;
+
+ /* Check if there is room in FMAC */
+ if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0UL)
+ {
+ return;
+ }
+
+ /* Get the maximum index (no wait allowed, no overstepping of the output buffer) */
+ if ((hfmac->InputCurrentSize + MaxSizeToWrite) > *(hfmac->pInputSize))
+ {
+ maxsize = *(hfmac->pInputSize);
+ }
+ else
+ {
+ maxsize = hfmac->InputCurrentSize + MaxSizeToWrite;
+ }
+
+ /* Write until there is no more room or no more data */
+ do
+ {
+ /* If there is no more room, return */
+ if (!(hfmac->InputCurrentSize < maxsize))
+ {
+ return;
+ }
+
+ /* Write the available data */
+ WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA));
+ hfmac->pInput++;
+ hfmac->InputCurrentSize++;
+ } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0UL);
+
+ /* X1 buffer full flag has just be raised, read the threshold */
+ threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_X1_FULL_WM(hfmac)) - 1U;
+
+ /* Update the maximum size if needed (limited data available) */
+ if ((hfmac->InputCurrentSize + threshold) < maxsize)
+ {
+ maxsize = hfmac->InputCurrentSize + threshold;
+ }
+
+ /* Write the available data */
+ while (hfmac->InputCurrentSize < maxsize)
+ {
+ WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA));
+ hfmac->pInput++;
+ hfmac->InputCurrentSize++;
+ }
+}
+
+/**
+ * @brief DMA FMAC Input Data process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAHalfGetData(DMA_HandleTypeDef *hdma)
+{
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Call half get data callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->HalfGetDataCallback(hfmac);
+#else
+ HAL_FMAC_HalfGetDataCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA FMAC Input Data process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAGetData(DMA_HandleTypeDef *hdma)
+{
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Reset the pointers to indicate new data will be needed */
+ FMAC_ResetInputStateAndDataPointers(hfmac);
+
+ /* Call get data callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->GetDataCallback(hfmac);
+#else
+ HAL_FMAC_GetDataCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA FMAC Output Data process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAHalfOutputDataReady(DMA_HandleTypeDef *hdma)
+{
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Call half output data ready callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->HalfOutputDataReadyCallback(hfmac);
+#else
+ HAL_FMAC_HalfOutputDataReadyCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA FMAC Output Data process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAOutputDataReady(DMA_HandleTypeDef *hdma)
+{
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Reset the pointers to indicate new data will be needed */
+ FMAC_ResetOutputStateAndDataPointers(hfmac);
+
+ /* Call output data ready callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->OutputDataReadyCallback(hfmac);
+#else
+ HAL_FMAC_OutputDataReadyCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA FMAC Filter Configuration process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma)
+{
+ uint8_t index;
+
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* If needed, write CoeffA and exit */
+ if (hfmac->pInput != NULL)
+ {
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ if (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)hfmac->pInput, (uint32_t)&hfmac->Instance->WDATA,
+ hfmac->InputCurrentSize) == HAL_OK)
+ {
+ hfmac->pInput = NULL;
+ hfmac->InputCurrentSize = 0U;
+ return;
+ }
+
+ /* If not exited, there was an error: set FMAC handle state to error */
+ hfmac->State = HAL_FMAC_STATE_ERROR;
+ }
+ else
+ {
+ /* Wait for the end of the writing */
+ for (index = 0U; index < 0xFFU; index++)
+ {
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
+ {
+ break;
+ }
+ }
+
+ /* If 'START' is still set, there was an error: set FMAC handle state to error */
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+ {
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ }
+ else
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ /* Call output data ready callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->FilterConfigCallback(hfmac);
+#else
+ HAL_FMAC_FilterConfigCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ return;
+ }
+ }
+
+ /* If not exited, there was an error: set FMAC handle error code to DMA error */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_DMA;
+
+ /* Call user callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->ErrorCallback(hfmac);
+#else
+ HAL_FMAC_ErrorCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+
+}
+
+/**
+ * @brief DMA FMAC Filter Configuration process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma)
+{
+ uint8_t index;
+
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Wait for the end of the X1 writing */
+ for (index = 0U; index < 0xFFU; index++)
+ {
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0UL)
+ {
+ break;
+ }
+ }
+
+ /* If 'START' is still set, there was an error: set FMAC handle state to error */
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+ {
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ }
+ /* If needed, preload Y buffer */
+ else if ((hfmac->pInput != NULL) && (hfmac->InputCurrentSize != 0U))
+ {
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)(hfmac->InputCurrentSize) << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ if (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)hfmac->pInput, (uint32_t)&hfmac->Instance->WDATA,
+ hfmac->InputCurrentSize) == HAL_OK)
+ {
+ hfmac->pInput = NULL;
+ hfmac->InputCurrentSize = 0U;
+ return;
+ }
+
+ /* If not exited, there was an error */
+ hfmac->ErrorCode = HAL_FMAC_ERROR_DMA;
+ hfmac->State = HAL_FMAC_STATE_ERROR;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* Return function status */
+ if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
+ {
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ /* Call output data ready callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->FilterPreloadCallback(hfmac);
+#else
+ HAL_FMAC_FilterPreloadCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Call user callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->ErrorCallback(hfmac);
+#else
+ HAL_FMAC_ErrorCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+ }
+}
+
+
+/**
+ * @brief DMA FMAC communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void FMAC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set FMAC handle state to error */
+ hfmac->State = HAL_FMAC_STATE_ERROR;
+
+ /* Set FMAC handle error code to DMA error */
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_DMA;
+
+ /* Call user callback */
+#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
+ hfmac->ErrorCallback(hfmac);
+#else
+ HAL_FMAC_ErrorCallback(hfmac);
+#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FMAC_MODULE_ENABLED */
+#endif /* FMAC */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_hcd.c b/Src/stm32h7xx_hal_hcd.c
index a7f2968..45d8061 100644
--- a/Src/stm32h7xx_hal_hcd.c
+++ b/Src/stm32h7xx_hal_hcd.c
@@ -1170,6 +1170,13 @@
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
}
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
+ {
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
+ hhcd->hc[ch_num].state = HC_BBLERR;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
@@ -1234,6 +1241,7 @@
else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
+ hhcd->hc[ch_num].toggle_in ^= 1U;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
@@ -1289,6 +1297,11 @@
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
}
+ else if (hhcd->hc[ch_num].state == HC_BBLERR)
+ {
+ hhcd->hc[ch_num].ErrCnt++;
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
+ }
else
{
/* ... */
diff --git a/Src/stm32h7xx_hal_hrtim.c b/Src/stm32h7xx_hal_hrtim.c
index fcb9319..914930c 100644
--- a/Src/stm32h7xx_hal_hrtim.c
+++ b/Src/stm32h7xx_hal_hrtim.c
@@ -5132,11 +5132,11 @@
* @param Timers Timer counter(s) to stop
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_A
- * @arg HRTIM_TIMERID_B
- * @arg HRTIM_TIMERID_C
- * @arg HRTIM_TIMERID_D
- * @arg HRTIM_TIMERID_E
+ * @arg HRTIM_TIMERID_TIMER_A
+ * @arg HRTIM_TIMERID_TIMER_B
+ * @arg HRTIM_TIMERID_TIMER_C
+ * @arg HRTIM_TIMERID_TIMER_D
+ * @arg HRTIM_TIMERID_TIMER_E
* @retval HAL status
* @note The counter of a timer is stopped only if all timer outputs are disabled
*/
@@ -5169,11 +5169,11 @@
* @param Timers Timer counter(s) to start
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_A
- * @arg HRTIM_TIMERID_B
- * @arg HRTIM_TIMERID_C
- * @arg HRTIM_TIMERID_D
- * @arg HRTIM_TIMERID_E
+ * @arg HRTIM_TIMERID_TIMER_A
+ * @arg HRTIM_TIMERID_TIMER_B
+ * @arg HRTIM_TIMERID_TIMER_C
+ * @arg HRTIM_TIMERID_TIMER_D
+ * @arg HRTIM_TIMERID_TIMER_E
* @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
* to the timers to start are enabled within this function.
* Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
@@ -5233,11 +5233,11 @@
* @param Timers Timer counter(s) to stop
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERID_MASTER
- * @arg HRTIM_TIMERID_A
- * @arg HRTIM_TIMERID_B
- * @arg HRTIM_TIMERID_C
- * @arg HRTIM_TIMERID_D
- * @arg HRTIM_TIMERID_E
+ * @arg HRTIM_TIMERID_TIMER_A
+ * @arg HRTIM_TIMERID_TIMER_B
+ * @arg HRTIM_TIMERID_TIMER_C
+ * @arg HRTIM_TIMERID_TIMER_D
+ * @arg HRTIM_TIMERID_TIMER_E
* @retval HAL status
* @note The counter of a timer is stopped only if all timer outputs are disabled
* @note All enabled timer related interrupts are disabled.
diff --git a/Src/stm32h7xx_hal_hsem.c b/Src/stm32h7xx_hal_hsem.c
index bba63f6..78ae43b 100644
--- a/Src/stm32h7xx_hal_hsem.c
+++ b/Src/stm32h7xx_hal_hsem.c
@@ -101,6 +101,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#if defined(DUAL_CORE)
+/** @defgroup HSEM_Private_Constants HSEM Private Constants
+ * @{
+ */
+
#ifndef HSEM_R_MASTERID
#define HSEM_R_MASTERID HSEM_R_COREID
#endif
@@ -112,6 +116,10 @@
#ifndef HSEM_CR_MASTERID
#define HSEM_CR_MASTERID HSEM_CR_COREID
#endif
+
+/**
+ * @}
+ */
#endif /* DUAL_CORE */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
diff --git a/Src/stm32h7xx_hal_i2c.c b/Src/stm32h7xx_hal_i2c.c
index a9e7408..cecdbb4 100644
--- a/Src/stm32h7xx_hal_i2c.c
+++ b/Src/stm32h7xx_hal_i2c.c
@@ -3203,7 +3203,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -3288,7 +3288,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -3449,7 +3449,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -3534,7 +3534,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -5477,7 +5477,7 @@
{
uint32_t tmperror;
uint32_t tmpITFlags = ITFlags;
- uint32_t tmp;
+ __IO uint32_t tmpreg;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@@ -5518,9 +5518,8 @@
if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
{
/* Read data from RXDR */
- tmp = (uint8_t)hi2c->Instance->RXDR;
-
- UNUSED(tmp);
+ tmpreg = (uint8_t)hi2c->Instance->RXDR;
+ UNUSED(tmpreg);
}
/* Flush TX register */
diff --git a/Src/stm32h7xx_hal_i2c_ex.c b/Src/stm32h7xx_hal_i2c_ex.c
index 6d8b28a..f568c3e 100644
--- a/Src/stm32h7xx_hal_i2c_ex.c
+++ b/Src/stm32h7xx_hal_i2c_ex.c
@@ -276,6 +276,8 @@
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ * @note For all I2C5 pins fast mode plus driving capability can be enabled
+ * only by using I2C_FASTMODEPLUS_I2C5 parameter.
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
@@ -305,6 +307,8 @@
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ * @note For all I2C5 pins fast mode plus driving capability can be disabled
+ * only by using I2C_FASTMODEPLUS_I2C5 parameter.
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
diff --git a/Src/stm32h7xx_hal_i2s.c b/Src/stm32h7xx_hal_i2s.c
index 864ea4b..fa1a7cb 100644
--- a/Src/stm32h7xx_hal_i2s.c
+++ b/Src/stm32h7xx_hal_i2s.c
@@ -114,6 +114,7 @@
Function HAL_I2S_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : I2S Tx Completed callback
(+) RxCpltCallback : I2S Rx Completed callback
+ (+) TxRxCpltCallback : I2S TxRx Completed callback
(+) TxHalfCpltCallback : I2S Tx Half Completed callback
(+) RxHalfCpltCallback : I2S Rx Half Completed callback
(+) ErrorCallback : I2S Error callback
@@ -130,6 +131,7 @@
This function allows to reset following callbacks:
(+) TxCpltCallback : I2S Tx Completed callback
(+) RxCpltCallback : I2S Rx Completed callback
+ (+) TxRxCpltCallback : I2S TxRx Completed callback
(+) TxHalfCpltCallback : I2S Tx Half Completed callback
(+) RxHalfCpltCallback : I2S Rx Half Completed callback
(+) ErrorCallback : I2S Error callback
@@ -201,6 +203,8 @@
static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma);
+static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMAError(DMA_HandleTypeDef *hdma);
static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s);
static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s);
@@ -290,8 +294,10 @@
/* Init the I2S Callback settings */
hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
if (hi2s->MspInitCallback == NULL)
@@ -558,6 +564,10 @@
hi2s->RxCpltCallback = pCallback;
break;
+ case HAL_I2S_TX_RX_COMPLETE_CB_ID :
+ hi2s->TxRxCpltCallback = pCallback;
+ break;
+
case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
hi2s->TxHalfCpltCallback = pCallback;
break;
@@ -566,6 +576,11 @@
hi2s->RxHalfCpltCallback = pCallback;
break;
+
+ case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
+ hi2s->TxRxHalfCpltCallback = pCallback;
+ break;
+
case HAL_I2S_ERROR_CB_ID :
hi2s->ErrorCallback = pCallback;
break;
@@ -649,6 +664,10 @@
hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
+ case HAL_I2S_TX_RX_COMPLETE_CB_ID :
+ hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
@@ -657,6 +676,10 @@
hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
+ case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
+ hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ break;
+
case HAL_I2S_ERROR_CB_ID :
hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
break;
@@ -741,18 +764,22 @@
(#) Blocking mode functions are :
(++) HAL_I2S_Transmit()
(++) HAL_I2S_Receive()
+ (++) HAL_I2SEx_TransmitReceive()
(#) No-Blocking mode functions with Interrupt are :
(++) HAL_I2S_Transmit_IT()
(++) HAL_I2S_Receive_IT()
+ (++) HAL_I2SEx_TransmitReceive_IT()
(#) No-Blocking mode functions with DMA are :
(++) HAL_I2S_Transmit_DMA()
(++) HAL_I2S_Receive_DMA()
+ (++) HAL_I2SEx_TransmitReceive_DMA()
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_I2S_TxCpltCallback()
(++) HAL_I2S_RxCpltCallback()
+ (++) HAL_I2SEx_TxRxCpltCallback()
(++) HAL_I2S_ErrorCallback()
@endverbatim
@@ -937,7 +964,7 @@
/* Receive data */
while (hi2s->RxXferCount > 0UL)
{
- /* Wait until RXNE flag is set */
+ /* Wait until RXP flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, Timeout) != HAL_OK)
{
/* Set the error code */
@@ -983,6 +1010,159 @@
}
/**
+ * @brief Full-Duplex Transmit/Receive data in blocking mode.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tmp_TxXferCount;
+ uint32_t tmp_RxXferCount;
+ uint32_t tickstart;
+
+#if defined (__GNUC__)
+ __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
+ __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
+#endif /* __GNUC__ */
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->pTxBuffPtr = pTxData;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ hi2s->pRxBuffPtr = pRxData;
+
+ tmp_TxXferCount = hi2s->TxXferCount;
+ tmp_RxXferCount = hi2s->RxXferCount;
+
+ /* Set state and reset error code */
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Start the transfer */
+ SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+ while ((tmp_TxXferCount > 0UL) || (tmp_RxXferCount > 0UL))
+ {
+ if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXP) == SET) && (tmp_TxXferCount != 0UL))
+ {
+ if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
+ {
+ /* Transmit data in 32 Bit mode */
+ hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr);
+ hi2s->pTxBuffPtr += 2;
+ tmp_TxXferCount--;
+ }
+ else
+ {
+ /* Transmit data in 16 Bit mode */
+#if defined (__GNUC__)
+ *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr);
+#else
+ *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
+#endif /* __GNUC__ */
+
+ hi2s->pTxBuffPtr++;
+ tmp_TxXferCount--;
+ }
+
+ /* Check if an underrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Clear underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ }
+ }
+
+ if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXP) == SET) && (tmp_RxXferCount != 0UL))
+ {
+ if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
+ {
+ /* Receive data in 32 Bit mode */
+ *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
+ hi2s->pRxBuffPtr += 2;
+ tmp_RxXferCount--;
+ }
+ else
+ {
+ /* Receive data in 16 Bit mode */
+#if defined (__GNUC__)
+ *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
+#endif /* __GNUC__ */
+ hi2s->pRxBuffPtr++;
+ tmp_RxXferCount--;
+ }
+
+ /* Check if an overrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Clear overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ }
+ }
+
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
@@ -1117,7 +1297,7 @@
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
- /* Enable RXNE and ERR interrupt */
+ /* Enable RXP and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_OVR));
/* Enable TIFRE interrupt if the mode is Slave */
@@ -1134,6 +1314,86 @@
}
/**
+ * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size)
+{
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->pTxBuffPtr = pTxData;
+ hi2s->pRxBuffPtr = pRxData;
+
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+
+ /* Set the function for IT treatment */
+ if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxISR = I2S_Transmit_32Bit_IT;
+ hi2s->RxISR = I2S_Receive_32Bit_IT;
+ }
+ else
+ {
+ hi2s->TxISR = I2S_Transmit_16Bit_IT;
+ hi2s->RxISR = I2S_Receive_16Bit_IT;
+ }
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Enable TXP, RXP, DXP, UDR, OVR interrupts */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_UDR | I2S_IT_OVR));
+
+ /* Enable TIFRE interrupt if the mode is Slave */
+ if (hi2s->Init.Mode == I2S_MODE_SLAVE_FULLDUPLEX)
+ {
+ __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
+ }
+
+ /* Start the transfer */
+ SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+
+}
+
+/**
* @brief Transmit an amount of data in non-blocking mode with DMA
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
@@ -1187,7 +1447,7 @@
/* Enable the Tx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize))
{
- /* Update SPI error code */
+ /* Update I2S error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
hi2s->State = HAL_I2S_STATE_READY;
@@ -1234,7 +1494,7 @@
{
if ((pData == NULL) || (Size == 0UL))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Process Locked */
@@ -1271,7 +1531,112 @@
/* Enable the Rx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
{
- /* Update SPI error code */
+ /* Update I2S error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Check if the I2S Rx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
+ {
+ /* Enable Rx DMA Request */
+ SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
+ }
+
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Start the transfer */
+ SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+ uint16_t Size)
+{
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->pTxBuffPtr = pTxData;
+ hi2s->pRxBuffPtr = pRxData;
+
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+ /* Reset the Tx/Rx DMA bits */
+ CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2SEx_DMATxRxHalfCplt;
+
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2SEx_DMATxRxCplt;
+
+ /* Set the I2S Rx DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize))
+ {
+ /* Update I2S error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Check if the I2S Tx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
+ {
+ /* Enable Tx DMA Request */
+ SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
+ }
+
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
+ {
+ /* Update I2S error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
hi2s->State = HAL_I2S_STATE_READY;
@@ -1310,13 +1675,13 @@
{
/* Process Locked */
__HAL_LOCK(hi2s);
-
+
uint32_t tickstart;
/* Get tick */
tickstart = HAL_GetTick();
-
-
+
+
/* Check if the I2S peripheral is in master mode */
if (IS_I2S_MASTER(hi2s->Init.Mode))
{
@@ -1330,7 +1695,7 @@
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
-
+
SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSUSP);
while (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) != 0UL)
@@ -1339,35 +1704,35 @@
{
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
-
+
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
return HAL_TIMEOUT;
}
}
-
+
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
-
+
hi2s->State = HAL_I2S_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
- else
+ else
{
/* Set error code to not supported */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NOT_SUPPORTED);
hi2s->State = HAL_I2S_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
-
+
return HAL_ERROR;
}
}
@@ -1390,14 +1755,14 @@
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
-
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
+
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
-
+
/* Start the transfer */
SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
@@ -1417,7 +1782,7 @@
{
HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
- to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+ to call the HAL I2S API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
*/
@@ -1464,67 +1829,136 @@
*/
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
{
- uint32_t itsource = hi2s->Instance->IER;
- uint32_t itflag = hi2s->Instance->SR;
- uint32_t trigger = itsource & itflag;
+ uint32_t i2sier = hi2s->Instance->IER;
+ uint32_t i2ssr = hi2s->Instance->SR;
+ uint32_t trigger = i2sier & i2ssr;
- /* I2S in mode Receiver ------------------------------------------------*/
- if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) && HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP))
+ if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
- hi2s->RxISR(hi2s);
- }
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if (HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_OVR))
+ {
+ hi2s->RxISR(hi2s);
+ }
- /* I2S in mode Transmitter -----------------------------------------------*/
- if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) == RESET) && HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP))
- {
- hi2s->TxISR(hi2s);
- }
-
- /* I2S interrupt error ----------------------------------------------------*/
- if ((trigger & (I2S_FLAG_OVR| I2S_FLAG_UDR | I2S_FLAG_FRE)) != 0UL)
- {
- /* I2S Overrun error interrupt occurred ---------------------------------*/
- if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
+ /* I2S Overrun error interrupt occurred -------------------------------------*/
+ if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR))
{
/* Disable RXP and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
+ /* Clear Overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+ hi2s->ErrorCallback(hi2s);
+#else
+ HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
+ }
+
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* I2S in mode Transmitter -----------------------------------------------*/
+ if (HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_UDR))
+ {
+ hi2s->TxISR(hi2s);
}
/* I2S Underrun error interrupt occurred --------------------------------*/
- if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
+ if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR))
{
/* Disable TXP and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
+ /* Clear Underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+ hi2s->ErrorCallback(hi2s);
+#else
+ HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
+ }
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* I2S in mode Transmitter -----------------------------------------------*/
+ if (HAL_IS_BIT_SET(trigger, I2S_FLAG_DXP))
+ {
+ hi2s->TxISR(hi2s);
+ hi2s->RxISR(hi2s);
+ }
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if (HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP))
+ {
+ hi2s->RxISR(hi2s);
+ }
+ /* I2S in mode Transmitter -----------------------------------------------*/
+ if (HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP))
+ {
+ hi2s->TxISR(hi2s);
}
- /* I2S Frame error interrupt occurred -----------------------------------*/
- if (I2S_CHECK_FLAG(itflag, I2S_FLAG_FRE) != RESET)
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR))
{
- /* Disable FRE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_FRE | I2S_IT_ERR));
+ /* Disable TXP and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
+
+ /* Clear Underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
/* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_FRE);
- __HAL_I2S_CLEAR_FREFLAG(hi2s);
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+ hi2s->ErrorCallback(hi2s);
+#else
+ HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
+ /* I2S Overrun error interrupt occurred -------------------------------------*/
+ if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR))
+ {
+ /* Disable RXP and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
- /* Call user error callback */
+ /* Clear Overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+
+ /* Call user error callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
- hi2s->ErrorCallback(hi2s);
+ hi2s->ErrorCallback(hi2s);
#else
- HAL_I2S_ErrorCallback(hi2s);
+ HAL_I2S_ErrorCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
}
}
@@ -1593,6 +2027,38 @@
}
/**
+ * @brief Rx Transfer half completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
* @brief I2S error callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
@@ -1743,6 +2209,42 @@
}
/**
+ * @brief DMA I2S transmit receive process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Call user TxRx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxRxCpltCallback(hi2s);
+#else
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA I2S transmit receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Call user TxRx Half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxRxHalfCpltCallback(hi2s);
+#else
+ HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
* @brief DMA I2S communication error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
@@ -1790,10 +2292,13 @@
if (hi2s->TxXferCount == 0UL)
{
- /* Disable TXE and ERR interrupt */
+ /* Disable TXP and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
- hi2s->State = HAL_I2S_STATE_READY;
+ if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) ||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
/* Call user Tx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
hi2s->TxCpltCallback(hi2s);
@@ -1818,10 +2323,13 @@
if (hi2s->TxXferCount == 0UL)
{
- /* Disable TXE and ERR interrupt */
+ /* Disable TXP and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
- hi2s->State = HAL_I2S_STATE_READY;
+ if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) ||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
/* Call user Tx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
hi2s->TxCpltCallback(hi2s);
@@ -1852,15 +2360,37 @@
if (hi2s->RxXferCount == 0UL)
{
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
+ if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+ {
+ /* Disable TXP, RXP, DXP, ERR interrupts */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR));
+ }
+ else
+ {
+ /* Disable RXP and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
+ }
hi2s->State = HAL_I2S_STATE_READY;
/* Call user Rx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
- hi2s->RxCpltCallback(hi2s);
+ if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+ {
+ hi2s->TxRxCpltCallback(hi2s);
+ }
+ else
+ {
+ hi2s->RxCpltCallback(hi2s);
+ }
#else
- HAL_I2S_RxCpltCallback(hi2s);
+ if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+ {
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+ }
+ else
+ {
+ HAL_I2S_RxCpltCallback(hi2s);
+ }
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
@@ -1880,15 +2410,37 @@
if (hi2s->RxXferCount == 0UL)
{
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
+ if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+ {
+ /* Disable TXP, RXP, DXP, ERR interrupts */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR));
+ }
+ else
+ {
+ /* Disable RXP and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
+ }
hi2s->State = HAL_I2S_STATE_READY;
/* Call user Rx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
- hi2s->RxCpltCallback(hi2s);
+ if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+ {
+ hi2s->TxRxCpltCallback(hi2s);
+ }
+ else
+ {
+ hi2s->RxCpltCallback(hi2s);
+ }
#else
- HAL_I2S_RxCpltCallback(hi2s);
+ if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+ {
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+ }
+ else
+ {
+ HAL_I2S_RxCpltCallback(hi2s);
+ }
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
diff --git a/Src/stm32h7xx_hal_i2s_ex.c b/Src/stm32h7xx_hal_i2s_ex.c
index 794a455..dad1c58 100644
--- a/Src/stm32h7xx_hal_i2s_ex.c
+++ b/Src/stm32h7xx_hal_i2s_ex.c
@@ -5,13 +5,7 @@
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S extension peripheral:
- * + Extension features Functions
- *
- @verbatim
- ==============================================================================
- ##### I2S Extension features #####
- ==============================================================================
- The I2S Full duplex feature is not supported by this HAL Driver
+ * + Extension features Functions
******************************************************************************
* @attention
*
@@ -25,4 +19,15 @@
*
******************************************************************************
*/
+
+/**
+ ******************************************************************************
+ ===== I2S FULL DUPLEX FEATURE =====
+ I2S Full Duplex APIs are available in stm32h7xx_hal_i2s.c/.h
+ ******************************************************************************
+ */
+
+
+
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_iwdg.c b/Src/stm32h7xx_hal_iwdg.c
index 02baf0a..d90bfb1 100644
--- a/Src/stm32h7xx_hal_iwdg.c
+++ b/Src/stm32h7xx_hal_iwdg.c
@@ -16,34 +16,44 @@
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
- (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
- if the main clock fails.
+ (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
+ active even if the main clock fails.
- (+) Once the IWDG is started, the LSI is forced ON and both can not be
+ (+) Once the IWDG is started, the LSI is forced ON and both cannot be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
- the IWDG_RLR value is reloaded in the counter and the watchdog reset is
- prevented.
+ the IWDG_RLR value is reloaded into the counter and the watchdog reset
+ is prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+ in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
+ (+) Debug mode: When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG1() or __HAL_DBGMCU_FREEZE2_IWDG2() and
__HAL_DBGMCU_UnFreeze_IWDG1 or __HAL_DBGMCU_UnFreeze2_IWDG2() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32H7xx
- devices provide the capability to measure the LSI frequency (LSI clock
- connected internally to TIM16 CH1 input capture). The measured value
- can be used to have an IWDG timeout with an acceptable accuracy.
+ The IWDG timeout may vary due to LSI clock frequency dispersion.
+ STM32H7xx devices provide the capability to measure the LSI clock
+ frequency (LSI clock is internally connected to TIM16 CH1 input capture).
+ The measured value can be used to have an IWDG timeout with an
+ acceptable accuracy.
+
+ [..] Default timeout value (necessary for IWDG_SR status register update):
+ Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
+ This frequency being subject to variations as mentioned above, the
+ default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
+ below) may become too short or too long.
+ In such cases, this default timeout value can be tuned by redefining
+ the constant LSI_VALUE at user-application level (based, for instance,
+ on the measured LSI clock frequency as explained above).
##### How to use this driver #####
==============================================================================
@@ -109,10 +119,14 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
- higher prescaler (256), and according to LSI variation, we need to wait at
- least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT 48u
+/* Status register needs up to 5 LSI clock periods divided by the clock
+ prescaler to be updated. The number of LSI clock periods is upper-rounded to
+ 6 for the timeout value calculation.
+ The timeout value is also calculated using the highest prescaler (256) and
+ the LSI_VALUE constant. The value of this constant can be changed by the user
+ to take into account possible LSI clock period variations.
+ The timeout value is multiplied by 1000 to be converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
/**
* @}
*/
diff --git a/Src/stm32h7xx_hal_jpeg.c b/Src/stm32h7xx_hal_jpeg.c
index 223574f..160b0f4 100644
--- a/Src/stm32h7xx_hal_jpeg.c
+++ b/Src/stm32h7xx_hal_jpeg.c
@@ -223,15 +223,15 @@
* @{
*/
+#ifdef HAL_JPEG_MODULE_ENABLED
+
+#if defined (JPEG)
+
/** @defgroup JPEG JPEG
* @brief JPEG HAL module driver.
* @{
*/
-#ifdef HAL_JPEG_MODULE_ENABLED
-
-#if defined (JPEG)
-
/* Private define ------------------------------------------------------------*/
/** @addtogroup JPEG_Private_Constants
* @{
@@ -4186,11 +4186,12 @@
* @}
*/
-#endif /* JPEG */
-#endif /* HAL_JPEG_MODULE_ENABLED */
/**
* @}
*/
+#endif /* JPEG */
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
/**
* @}
diff --git a/Src/stm32h7xx_hal_mmc.c b/Src/stm32h7xx_hal_mmc.c
index 227a1a4..ad69334 100644
--- a/Src/stm32h7xx_hal_mmc.c
+++ b/Src/stm32h7xx_hal_mmc.c
@@ -387,13 +387,17 @@
{
uint32_t errorstate;
MMC_InitTypeDef Init;
+ uint32_t sdmmc_clk;
/* Default SDMMC peripheral configuration for MMC card initialization */
Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
Init.BusWide = SDMMC_BUS_WIDE_1B;
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
- Init.ClockDiv = SDMMC_INIT_CLK_DIV;
+
+ /* Init Clock should be less or equal to 400Khz*/
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+ Init.ClockDiv = sdmmc_clk/(2U*400000U);
/* Initialize SDMMC peripheral interface with default configuration */
(void)SDMMC_Init(hmmc->Instance, Init);
@@ -401,6 +405,19 @@
/* Set Power State to ON */
(void)SDMMC_PowerState_ON(hmmc->Instance);
+ /* wait 74 Cycles: required power up waiting time before starting
+ the MMC initialization sequence */
+ sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv);
+
+ if(sdmmc_clk != 0U)
+ {
+ HAL_Delay(1U+ (74U*1000U/(sdmmc_clk)));
+ }
+ else
+ {
+ HAL_Delay(2U);
+ }
+
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -1330,7 +1347,7 @@
}
/* Send CMD38 ERASE */
- errorstate = SDMMC_CmdErase(hmmc->Instance);
+ errorstate = SDMMC_CmdErase(hmmc->Instance, 0UL);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
@@ -2077,10 +2094,10 @@
*/
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
{
- __IO uint32_t count = 0U;
+ uint32_t count;
SDMMC_InitTypeDef Init;
uint32_t errorstate;
- uint32_t response = 0U, busy = 0U;
+ uint32_t response = 0U;
/* Check the parameters */
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
@@ -2091,102 +2108,79 @@
if(WideMode == SDMMC_BUS_WIDE_8B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
}
else if(WideMode == SDMMC_BUS_WIDE_4B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
}
else if(WideMode == SDMMC_BUS_WIDE_1B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
}
else
{
/* WideMode is not a valid argument*/
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ errorstate = HAL_MMC_ERROR_PARAM;
}
/* Check for switch error and violation of the trial number of sending CMD 13 */
- while(busy == 0U)
+ if(errorstate == HAL_MMC_ERROR_NONE)
{
- if(count == SDMMC_MAX_TRIAL)
- {
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
- return HAL_ERROR;
- }
- count++;
-
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ count = SDMMC_MAX_TRIAL;
+ do
{
- hmmc->ErrorCode |= errorstate;
- }
-
- /* Get command response */
- response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
-
- /* Get operating voltage*/
- busy = (((response >> 7U) == 1U) ? 0U : 1U);
- }
-
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- count = SDMMC_DATATIMEOUT;
- while((response & 0x00000100U) == 0U)
- {
- if(count == 0U)
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ }while(((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
{
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
- return HAL_ERROR;
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ else
+ {
+ /* Configure the SDMMC peripheral */
+ Init.ClockEdge = hmmc->Init.ClockEdge;
+ Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
+ Init.BusWide = WideMode;
+ Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
+ Init.ClockDiv = hmmc->Init.ClockDiv;
+ (void)SDMMC_Init(hmmc->Instance, Init);
+ }
}
- count--;
-
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ else if (count == 0U)
{
- hmmc->ErrorCode |= errorstate;
+ errorstate = SDMMC_ERROR_TIMEOUT;
}
-
- /* Get command response */
- response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
- }
-
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
- /* Configure the SDMMC peripheral */
- Init.ClockEdge = hmmc->Init.ClockEdge;
- Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
- Init.BusWide = WideMode;
- Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
- Init.ClockDiv = hmmc->Init.ClockDiv;
- (void)SDMMC_Init(hmmc->Instance, Init);
+ else
+ {
+ /* Nothing to do */
+ }
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
return HAL_OK;
}
@@ -2449,6 +2443,393 @@
}
/**
+ * @brief Perform specific commands sequence for the different type of erase.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc Pointer to MMC handle
+ * @param EraseType Specifies the type of erase to be performed
+ * This parameter can be one of the following values:
+ * @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36
+ * @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36
+ * @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36
+ * @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified by CMD35 & 36
+ * @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase
+ * @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks previously identified
+ * @param BlockStartAdd Start Block address
+ * @param BlockEndAdd End Block address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+ uint32_t errorstate;
+ uint32_t start_add = BlockStartAdd;
+ uint32_t end_add = BlockEndAdd;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the erase type value is correct */
+ assert_param(IS_MMC_ERASE_TYPE(EraseType));
+
+ /* Check the coherence between start and end address */
+ if(end_add < start_add)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Check that the end address is not out of range of device memory */
+ if(end_add > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ /* Check if the card command class supports erase command */
+ if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ return HAL_ERROR;
+ }
+
+ /* Check the state of the driver */
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Check that the card is not locked */
+ if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* In case of low capacity card, the address is not block number but bytes */
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+ {
+ start_add *= 512U;
+ end_add *= 512U;
+ }
+
+ /* Send CMD35 MMC_ERASE_GRP_START with start address as argument */
+ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Send CMD36 MMC_ERASE_GRP_END with end address as argument */
+ errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Send CMD38 ERASE with erase type as argument */
+ errorstate = SDMMC_CmdErase(hmmc->Instance, EraseType);
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if ((EraseType == HAL_MMC_SECURE_ERASE) || (EraseType == HAL_MMC_SECURE_TRIM_STEP2))
+ {
+ /* Wait that the device is ready by checking the D0 line */
+ while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ if((HAL_GetTick()-tickstart) >= SDMMC_MAXERASETIMEOUT)
+ {
+ errorstate = HAL_MMC_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear the flag corresponding to end D0 bus line */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+ }
+ }
+ }
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Manage errors */
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+
+ if(errorstate != HAL_MMC_ERROR_TIMEOUT)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Perform sanitize operation on the device.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc Pointer to MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate, response = 0U, count;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the state of the driver */
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Index : 165 - Value : 0x01 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03A50100U);
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Wait that the device is ready by checking the D0 line */
+ while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ if((HAL_GetTick()-tickstart) >= SDMMC_MAXERASETIMEOUT)
+ {
+ errorstate = HAL_MMC_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear the flag corresponding to end D0 bus line */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ }while(((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Manage errors */
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+
+ if(errorstate != HAL_MMC_ERROR_TIMEOUT)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure the Secure Removal Type (SRT) in the Extended CSD register.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc Pointer to MMC handle
+ * @param SRTMode Specifies the type of erase to be performed
+ * This parameter can be one of the following values:
+ * @arg HAL_MMC_SRT_ERASE Information removed by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, its complement then a random character
+ * @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode)
+{
+ uint32_t srt, errorstate, response = 0U, count;
+
+ /* Check the erase type value is correct */
+ assert_param(IS_MMC_SRT_TYPE(SRTMode));
+
+ /* Check the state of the driver */
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Get the supported values by the device */
+ if(HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Check the value passed as parameter is supported by the device */
+ if((SRTMode & srt) != 0U)
+ {
+ /* Index : 16 - Value : SRTMode */
+ srt |= ((POSITION_VAL(SRTMode)) << 4U);
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03100000U | (srt << 8U)));
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ }while(((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ else
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+ }
+ else
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+
+ /* Manage errors */
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Gets the supported values of the the Secure Removal Type (SRT).
+ * @param hmmc pointer to MMC handle
+ * @param SupportedSRT pointer for supported SRT value
+ * This parameter is a bit field of the following values:
+ * @arg HAL_MMC_SRT_ERASE Information removed by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, its complement then a random character
+ * @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT)
+{
+ uint32_t srt = 0U;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Check the state of the driver */
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Read the Extended CSD register and get expected value */
+ if(MMC_ReadExtCSD(hmmc, &srt, 16, 0x0FFFFFFFU) == HAL_OK) /* Field SECURE_REMOVAL_TYPE [16] */
+ {
+ *SupportedSRT = (srt & 0x0000000FU); /* Bits [3:0] of field 16 */
+ }
+ else
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Manage errors */
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
* @}
*/
@@ -2814,7 +3195,7 @@
static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t response, count;
+ uint32_t response = 0U, count;
SDMMC_InitTypeDef Init;
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE))
@@ -2831,59 +3212,61 @@
if(errorstate == HAL_MMC_ERROR_NONE)
{
- /* Check for switch error */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate == HAL_MMC_ERROR_NONE)
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
{
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ }while(((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- count = SDMMC_MAX_TRIAL;
- while(((response & 0x100U) == 0U) && (count != 0U))
- {
- count--;
-
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- break;
- }
-
- /* Get command response */
- response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
- }
-
/* Configure high speed */
- if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ Init.ClockEdge = hmmc->Init.ClockEdge;
+ Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
+ Init.BusWide = (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS);
+ Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
+
+ if (state == DISABLE)
{
- Init.ClockEdge = hmmc->Init.ClockEdge;
- Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
- Init.BusWide = (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS);
- Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
+ Init.ClockDiv = hmmc->Init.ClockDiv;
+ (void)SDMMC_Init(hmmc->Instance, Init);
- if (state == DISABLE)
- {
- Init.ClockDiv = hmmc->Init.ClockDiv;
- (void)SDMMC_Init(hmmc->Instance, Init);
-
- CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
- }
- else
- {
- Init.ClockDiv = SDMMC_HSpeed_CLK_DIV;
- (void)SDMMC_Init(hmmc->Instance, Init);
-
- SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
- }
+ CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
+ }
+ else
+ {
+ Init.ClockDiv = SDMMC_HSpeed_CLK_DIV;
+ (void)SDMMC_Init(hmmc->Instance, Init);
+
+ SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
}
}
}
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
return errorstate;
@@ -2898,7 +3281,7 @@
static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state)
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t response, count;
+ uint32_t response = 0U, count;
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE))
{
@@ -2930,48 +3313,50 @@
if(errorstate == HAL_MMC_ERROR_NONE)
{
- /* Check for switch error */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate == HAL_MMC_ERROR_NONE)
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
{
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ }while(((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- count = SDMMC_MAX_TRIAL;
- while(((response & 0x100U) == 0U) && (count != 0U))
- {
- count--;
-
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- break;
- }
-
- /* Get command response */
- response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
- }
-
/* Configure DDR mode */
- if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ if (state == DISABLE)
{
- if (state == DISABLE)
- {
- CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
- }
- else
- {
- SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
- }
+ CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
+ }
+ else
+ {
+ SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
}
}
}
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
return errorstate;
diff --git a/Src/stm32h7xx_hal_mmc_ex.c b/Src/stm32h7xx_hal_mmc_ex.c
index 8e2d905..6c404ca 100644
--- a/Src/stm32h7xx_hal_mmc_ex.c
+++ b/Src/stm32h7xx_hal_mmc_ex.c
@@ -3,10 +3,10 @@
* @file stm32h7xx_hal_mmc_ex.c
* @author MCD Application Team
* @brief MMC card Extended HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
* + Extended features functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -16,7 +16,7 @@
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
(+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
-
+
@endverbatim
******************************************************************************
* @attention
@@ -30,7 +30,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
@@ -57,17 +57,19 @@
* @{
*/
+
+
/** @addtogroup MMCEx_Exported_Functions_Group1
- * @brief Multibuffer functions
+ * @brief Multibuffer functions
*
-@verbatim
+@verbatim
==============================================================================
##### Multibuffer functions #####
==============================================================================
- [..]
- This section provides functions allowing to configure the multibuffer mode and start read and write
+ [..]
+ This section provides functions allowing to configure the multibuffer mode and start read and write
multibuffer mode for MMC HAL driver.
-
+
@endverbatim
* @{
*/
@@ -87,7 +89,7 @@
hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ;
hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ;
hmmc->Instance->IDMABSIZE= (uint32_t) (MMC_BLOCKSIZE * BufferSize);
-
+
return HAL_OK;
}
else
@@ -95,12 +97,12 @@
return HAL_BUSY;
}
}
-
+
/**
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
* @param hmmc: MMC handle
- * @param BlockAdd: Block Address from where data is to be read
+ * @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
@@ -110,7 +112,7 @@
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t errorstate;
uint32_t add = BlockAdd;
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
@@ -118,18 +120,19 @@
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
+
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
-
+
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_BUSY;
@@ -137,8 +140,8 @@
{
add *= 512U;
}
-
- /* Configure the MMC DPSM (Data Path State Machine) */
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
@@ -146,16 +149,16 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
-
+
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
-
+
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
-
- hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+ hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
/* Read Blocks in DMA mode */
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
+
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -164,7 +167,7 @@
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
-
+
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
@@ -173,14 +176,14 @@
{
return HAL_BUSY;
}
-
+
}
/**
* @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
* @param hmmc: MMC handle
- * @param BlockAdd: Block Address from where data is to be read
+ * @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
@@ -190,7 +193,7 @@
uint32_t errorstate;
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t add = BlockAdd;
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
@@ -198,28 +201,29 @@
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
+
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
-
+
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
-
- /* Configure the MMC DPSM (Data Path State Machine) */
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
@@ -227,14 +231,14 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
-
+
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
-
- hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
-
+
+ hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
/* Write Blocks in DMA mode */
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
+
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -243,7 +247,7 @@
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
-
+
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
@@ -251,18 +255,18 @@
else
{
return HAL_BUSY;
- }
+ }
}
-
+
/**
* @brief Change the DMA Buffer0 or Buffer1 address on the fly.
* @param hmmc: pointer to a MMC_HandleTypeDef structure.
- * @param Buffer: the buffer to be changed, This parameter can be one of
+ * @param Buffer: the buffer to be changed, This parameter can be one of
* the following values: MMC_DMA_BUFFER0 or MMC_DMA_BUFFER1
* @param pDataBuffer: The new address
* @note The BUFFER0 address can be changed only when the current transfer use
- * BUFFER1 and the BUFFER1 address can be changed only when the current
+ * BUFFER1 and the BUFFER1 address can be changed only when the current
* transfer use BUFFER0.
* @retval HAL status
*/
@@ -278,7 +282,7 @@
/* change the memory1 address */
hmmc->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
}
-
+
return HAL_OK;
}
diff --git a/Src/stm32h7xx_hal_otfdec.c b/Src/stm32h7xx_hal_otfdec.c
index 1a19404..a54882e 100644
--- a/Src/stm32h7xx_hal_otfdec.c
+++ b/Src/stm32h7xx_hal_otfdec.c
@@ -577,7 +577,7 @@
* the configuration information for OTFDEC module
* @param RegionIndex index of region the keys of which are set
* @param pKey pointer at set of keys
- * @note The API reads the key CRC computed by the peripheral and compares it with thzt
+ * @note The API reads the key CRC computed by the peripheral and compares it with that
* theoretically expected. An error is reported if they are different.
* @retval HAL state
*/
diff --git a/Src/stm32h7xx_hal_pwr.c b/Src/stm32h7xx_hal_pwr.c
index a3d2a1a..88c8d1a 100644
--- a/Src/stm32h7xx_hal_pwr.c
+++ b/Src/stm32h7xx_hal_pwr.c
@@ -26,13 +26,12 @@
peripherals. The D2 domain contains peripherals and a CPU
(Cortex-M4). The D3 domain contains the system control, I/O logic
and low-power peripherals.
- (+) STM32H743, STM32H753, STM32H742 and STM32H750 devices have 3 power
- domains (D1, D2 and D3).
+ (+) STM32H72x, STM32H73x, STM32H742, STM32H743, STM32H750 and STM32H753
+ devices have 3 power domains (D1, D2 and D3).
The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
peripherals. The D2 domain contains peripherals. The D3 domains
contains the system control, I/O logic and low-power peripherals.
- (+) STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx devices have 2
- power domains (CD and SRD).
+ (+) STM32H7Axxx and STM32H7Bxxx devices have 2 power domains (CD and SRD).
The core domain (CD) contains a CPU (Cortex-M7), a Flash
memory and peripherals. The SmartRun domain contains the system
control, I/O logic and low-power peripherals.
@@ -501,6 +500,9 @@
* PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
* PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+ * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH
+ * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes
+ * GPIOI port.
* @retval None.
*/
void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
@@ -527,6 +529,9 @@
* PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
* PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
* PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
+ * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH
+ * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes
+ * GPIOI port.
* @retval None.
*/
void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
@@ -675,6 +680,8 @@
* @note The system enters Standby mode only when all domains are in DSTANDBY.
* @note When the System exit STANDBY mode by issuing an interrupt or a
* wakeup event, the HSI RC oscillator is selected as system clock.
+ * @note It is recommended to disable all regulators before entring STANDBY
+ * mode for power consumption saving purpose.
* @retval None.
*/
void HAL_PWR_EnterSTANDBYMode (void)
diff --git a/Src/stm32h7xx_hal_pwr_ex.c b/Src/stm32h7xx_hal_pwr_ex.c
index 7370c22..77cd337 100644
--- a/Src/stm32h7xx_hal_pwr_ex.c
+++ b/Src/stm32h7xx_hal_pwr_ex.c
@@ -120,7 +120,7 @@
(#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring()
function to get VDDMMC voltage level. This API is used only for
- STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx lines
+ STM32H7Axxx and STM32H7Bxxx lines
(#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured
(event mode and voltage threshold) in order to set up the Analog Voltage
@@ -195,9 +195,14 @@
* @{
*/
/* Wake-Up Pins EXTI register mask */
+#if defined (EXTI_IMR2_IM57)
#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\
EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
+#else
+#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
+ EXTI_IMR2_IM58 | EXTI_IMR2_IM60)
+#endif /* defined (EXTI_IMR2_IM57) */
/* Wake-Up Pins PWR Pin Pull shift offsets */
#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
@@ -385,11 +390,6 @@
/**
* @brief Configure the main internal regulator output voltage.
- * @note For STM32H7x3, STM32H7x5, STM32H7x7, STM32H742 and STM32H750 lines,
- * configuring Voltage Scale 0 is only possible when Vcore is supplied
- * from LDO (Low DropOut). The SYSCFG Clock must be enabled through
- * __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage
- * Scale 0.
* @param VoltageScaling : Specifies the regulator output voltage to achieve
* a tradeoff between performance and power
* consumption.
@@ -402,6 +402,13 @@
* range 2 mode.
* @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
* range 3 mode.
+ * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is
+ * only possible when Vcore is supplied from LDO (Low DropOut). The
+ * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE()
+ * macro before configuring Voltage Scale 0.
+ * To enter low power mode , and if current regulator voltage is
+ * Voltage Scale 0 then first switch to Voltage Scale 1 before entering
+ * low power mode.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
@@ -422,6 +429,7 @@
/* Set the voltage range */
MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
#else
+#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0)
{
if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN)
@@ -476,6 +484,10 @@
/* Set the voltage range */
MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
}
+#else /* STM32H72xxx and STM32H73xxx lines */
+ /* Set the voltage range */
+ MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
+#endif /* defined (SYSCFG_PWRCR_ODEN) */
#endif /* defined (PWR_SRDCR_VOS) */
/* Get tick */
@@ -619,9 +631,9 @@
(+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction
(+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction
(++) Domain:
- (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTOP mode.
+ (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTOP mode.
(+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode.
- (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTOP mode.
+ (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTOP mode.
(+) Exit:
Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
@@ -642,9 +654,9 @@
The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode
(Domain) function with:
(++) Domain:
- (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTANDBY mode.
+ (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTANDBY mode.
(+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode.
- (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTANDBY mode.
+ (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTANDBY mode.
(+) Exit:
WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
@@ -855,9 +867,6 @@
#if defined (PWR_CPUCR_PDDS_D2)
else if (Domain == PWR_D2_DOMAIN)
{
- /* Keep DSTOP mode when D2 domain enters Deepsleep */
- CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
-
#if defined (DUAL_CORE)
/* Check current core */
if (HAL_GetCurrentCPUID () != CM4_CPUID)
@@ -869,6 +878,9 @@
return;
}
+ /* Keep DSTOP mode when D2 domain enters Deepsleep */
+ CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D2);
+
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
@@ -890,13 +902,30 @@
/* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
-#endif /* defined (DUAL_CORE) */
+#else
+ /* Keep DSTOP mode when D2 domain enters Deepsleep */
+ CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+#endif /* defined (DUAL_CORE) */
}
#endif /* defined (PWR_CPUCR_PDDS_D2) */
else
{
+#if defined (DUAL_CORE)
+ /* Check current core */
+ if (HAL_GetCurrentCPUID () == CM7_CPUID)
+ {
+ /* Keep DSTOP mode when D3 domain enters Deepsleep */
+ CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
+ }
+ else
+ {
+ /* Keep DSTOP mode when D3 domain enters Deepsleep */
+ CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3);
+ }
+#else
/* Keep DSTOP mode when D3/SRD domain enters Deepsleep */
CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
+#endif /* defined (DUAL_CORE) */
}
}
@@ -905,6 +934,7 @@
* @note This API clears the pending event in order to enter a given CPU
* to CSLEEP or CSTOP. It should be called just before APIs performing
* enter low power mode using Wait For Event request.
+ * @note Cortex-M7 must be in CRUN mode when calling this API by Cortex-M4.
* @retval None.
*/
void HAL_PWREx_ClearPendingEvent (void)
@@ -1029,11 +1059,11 @@
else
{
/* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
- SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D3);
+ SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
#if defined (DUAL_CORE)
/* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
- SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D3);
+ SET_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3);
#endif /* defined (DUAL_CORE) */
}
}
@@ -1308,6 +1338,8 @@
* @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN.
* @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN.
* @arg PWR_WAKEUP_PIN6 : Disable PC1 wake-up PIN.
+ * @note The PWR_WAKEUP_PIN3 and PWR_WAKEUP_PIN5 are available only for
+ * devices that support GPIOI port.
* @retval None
*/
void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
@@ -1331,6 +1363,8 @@
* @arg PWR_WAKEUP_FLAG6 : Get wakeup event received from PC1.
* @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all
* wake up pins.
+ * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for
+ * devices that support GPIOI port.
* @retval The Wake-Up pin flag.
*/
uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
@@ -1354,6 +1388,8 @@
* @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1.
* @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from
* all wake up pins.
+ * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for
+ * devices that support GPIOI port.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
@@ -1397,6 +1433,7 @@
/* PWR WKUP2 interrupt user callback */
HAL_PWREx_WKUP2_Callback ();
}
+#if defined (PWR_WKUPFR_WKUPF3)
else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U)
{
/* Clear PWR WKUPF3 flag */
@@ -1405,6 +1442,7 @@
/* PWR WKUP3 interrupt user callback */
HAL_PWREx_WKUP3_Callback ();
}
+#endif /* defined (PWR_WKUPFR_WKUPF3) */
else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U)
{
/* Clear PWR WKUPF4 flag */
@@ -1413,6 +1451,7 @@
/* PWR WKUP4 interrupt user callback */
HAL_PWREx_WKUP4_Callback ();
}
+#if defined (PWR_WKUPFR_WKUPF5)
else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U)
{
/* Clear PWR WKUPF5 flag */
@@ -1421,6 +1460,7 @@
/* PWR WKUP5 interrupt user callback */
HAL_PWREx_WKUP5_Callback ();
}
+#endif /* defined (PWR_WKUPFR_WKUPF5) */
else
{
/* Clear PWR WKUPF6 flag */
@@ -1453,6 +1493,7 @@
*/
}
+#if defined (PWR_WKUPFR_WKUPF3)
/**
* @brief PWR WKUP3 interrupt callback.
* @retval None.
@@ -1463,6 +1504,7 @@
the HAL_PWREx_WKUP3Callback can be implemented in the user file
*/
}
+#endif /* defined (PWR_WKUPFR_WKUPF3) */
/**
* @brief PWR WKUP4 interrupt callback.
@@ -1475,6 +1517,7 @@
*/
}
+#if defined (PWR_WKUPFR_WKUPF5)
/**
* @brief PWR WKUP5 interrupt callback.
* @retval None.
@@ -1485,6 +1528,7 @@
the HAL_PWREx_WKUP5Callback can be implemented in the user file
*/
}
+#endif /* defined (PWR_WKUPFR_WKUPF5) */
/**
* @brief PWR WKUP6 interrupt callback.
@@ -2003,14 +2047,14 @@
void HAL_PWREx_PVD_AVD_IRQHandler (void)
{
/* Check if the Programmable Voltage Detector is enabled (PVD) */
- if(READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U)
+ if (READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U)
{
#if defined (DUAL_CORE)
if (HAL_GetCurrentCPUID () == CM7_CPUID)
#endif /* defined (DUAL_CORE) */
{
/* Check PWR D1/CD EXTI flag */
- if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+ if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback ();
diff --git a/Src/stm32h7xx_hal_rcc_ex.c b/Src/stm32h7xx_hal_rcc_ex.c
index 22c9e94..508dd9d 100644
--- a/Src/stm32h7xx_hal_rcc_ex.c
+++ b/Src/stm32h7xx_hal_rcc_ex.c
@@ -37,7 +37,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
-/** @defgroup RCCEx_Private_defines Private Defines
+/** @defgroup RCCEx_Private_defines RCCEx Private Defines
* @{
*/
#define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
@@ -50,12 +50,21 @@
* @}
*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
/* Exported functions --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Functions Exported Functions
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
* @{
*/
@@ -84,7 +93,7 @@
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals
* clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123,
- * USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
+ * USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
* SAI4A*, SAI4B*, SPI6, RTC).
* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
* the RTC clock source; in this case the Backup domain will be reset in
@@ -412,6 +421,13 @@
/* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
/* SAI1 clock source configuration done later after clock selection check */
break;
+
+#if defined(RCC_VER_3_0)
+ case RCC_SAI4ACLKSOURCE_SPDIF:
+ /* SPDIF clock is used as source of SAI4A clock */
+ /* SAI4A clock source configuration done later after clock selection check */
+ break;
+#endif /* RCC_VER_3_0 */
default:
ret = HAL_ERROR;
@@ -464,6 +480,13 @@
/* SAI1 clock source configuration done later after clock selection check */
break;
+#if defined(RCC_VER_3_0)
+ case RCC_SAI4BCLKSOURCE_SPDIF:
+ /* SPDIF clock is used as source of SAI4B clock */
+ /* SAI4B clock source configuration done later after clock selection check */
+ break;
+#endif /* RCC_VER_3_0 */
+
default:
ret = HAL_ERROR;
break;
@@ -1247,7 +1270,25 @@
}
}
- /*------------------------------ I2C1/2/3 Configuration ------------------------*/
+ /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/
+#if defined(I2C5)
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection));
+
+ if ((PeriphClkInit->I2c1235ClockSelection )== RCC_I2C1235CLKSOURCE_PLL3 )
+ {
+ if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection);
+
+ }
+#else
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
{
/* Check the parameters */
@@ -1264,6 +1305,7 @@
__HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
}
+#endif /* I2C5 */
/*------------------------------ I2C4 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
@@ -1471,7 +1513,7 @@
/* Configure the SWPMI1 interface clock source */
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
}
-#if defined(HRTIM)
+#if defined(HRTIM1)
/*------------------------------ HRTIM1 clock Configuration ----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
{
@@ -1481,7 +1523,7 @@
/* Configure the HRTIM1 clock source */
__HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
}
-#endif /*HRTIM*/
+#endif /*HRTIM1*/
/*------------------------------ DFSDM1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
{
@@ -1536,7 +1578,7 @@
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* returns the configuration information for the Extended Peripherals clocks :
* (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123,
- * USART234578, USART16, RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC.
+ * USART234578, USART16, RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC.
* SAI4A*, SAI4B*, SPI6, RTC, TIM).
* @retval None
*
@@ -1554,14 +1596,18 @@
RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM |
RCC_PERIPHCLK_CKPER;
+#if defined(I2C5)
+PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235;
+#else
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
+#endif /*I2C5*/
#if defined(RCC_CDCCIP1R_SAI2ASEL)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A;
#endif /* RCC_CDCCIP1R_SAI2ASEL */
-#if defined(RCC_CDCCIP1R_SAI2BSEL)
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B;
#endif /* RCC_CDCCIP1R_SAI2BSEL */
-#if defined(SAI3)
+#if defined(SAI3)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23;
#endif /* SAI3 */
#if defined(SAI4)
@@ -1577,9 +1623,9 @@
#if defined(OCTOSPI1) || defined(OCTOSPI2)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
#endif /* OCTOSPI1 || OCTOSPI2 */
-#if defined(HRTIM)
+#if defined(HRTIM1)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
-#endif /* HRTIM */
+#endif /* HRTIM1 */
#if defined(LTDC)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;
#endif /* LTDC */
@@ -1611,8 +1657,13 @@
PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE();
/* Get the LPUART1 clock source --------------------------------------------*/
PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
+#if defined(I2C5)
+ /* Get the I2C1/2/3/5 clock source -----------------------------------------*/
+ PeriphClkInit->I2c1235ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+#else
/* Get the I2C1/2/3 clock source -------------------------------------------*/
PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+#endif /*I2C5*/
/* Get the LPTIM1 clock source ---------------------------------------------*/
PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
/* Get the LPTIM2 clock source ---------------------------------------------*/
@@ -3179,7 +3230,7 @@
* @}
*/
-/** @defgroup RCCEx_Private_functions Private Functions
+/** @defgroup RCCEx_Private_functions RCCEx Private Functions
* @{
*/
/**
@@ -3416,7 +3467,7 @@
{
/* NOTE : This function should not be modified, when the callback is needed,
the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
- */
+ */
}
diff --git a/Src/stm32h7xx_hal_rng.c b/Src/stm32h7xx_hal_rng.c
index 42eb178..09aa1e8 100644
--- a/Src/stm32h7xx_hal_rng.c
+++ b/Src/stm32h7xx_hal_rng.c
@@ -110,7 +110,7 @@
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
-/** @defgroup RNG_Private_Defines
+/** @defgroup RNG_Private_Defines RNG Private Defines
* @{
*/
/* Health test control register information to use in CCM algorithm */
diff --git a/Src/stm32h7xx_hal_rng_ex.c b/Src/stm32h7xx_hal_rng_ex.c
index 94c58f9..dad4322 100644
--- a/Src/stm32h7xx_hal_rng_ex.c
+++ b/Src/stm32h7xx_hal_rng_ex.c
@@ -40,7 +40,7 @@
#if defined (RNG_CR_CONDRST)
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Defines
+/** @defgroup RNGEx_Private_Defines RNGEx Private Defines
* @{
*/
/* Health test control register information to use in CCM algorithm */
@@ -55,7 +55,7 @@
*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Constants RNG Private Constants
+/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
* @{
*/
#define RNG_TIMEOUT_VALUE 2U
diff --git a/Src/stm32h7xx_hal_rtc.c b/Src/stm32h7xx_hal_rtc.c
index 970f650..b158d38 100644
--- a/Src/stm32h7xx_hal_rtc.c
+++ b/Src/stm32h7xx_hal_rtc.c
@@ -231,8 +231,6 @@
/* Check RTC handler */
if(hrtc != NULL)
{
- status = HAL_OK;
-
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
@@ -312,18 +310,9 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- status = HAL_ERROR;
- }
- else
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
{
#if defined(RTC_CR_TAMPOE)
/* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */
@@ -340,25 +329,7 @@
hrtc->Instance->PRER = (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos) | (hrtc->Init.SynchPrediv << RTC_PRER_PREDIV_S_Pos);
/* Exit Initialization mode */
-#if defined(RTC_ICSR_INIT)
- CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
-#endif /* RTC_ICSR_INIT */
-#if defined(RTC_ISR_INIT)
- CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
-#endif /* RTC_ISR_INIT */
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
- status = HAL_ERROR;
- }
- }
+ status = RTC_ExitInitMode(hrtc);
if(status == HAL_OK)
{
@@ -371,14 +342,15 @@
hrtc->Instance->OR &= ~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
#endif /* ALARMOUTTYPE && RTC_OR_OUT_RMP */
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
}
}
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
}
/* return status */
@@ -399,8 +371,6 @@
/* Check RTC handler */
if(hrtc != NULL)
{
- status = HAL_OK;
-
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
@@ -409,19 +379,9 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- status = HAL_ERROR;
- }
- else
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
{
/* Reset TR, DR and CR registers */
hrtc->Instance->TR = 0x00000000U;
@@ -436,7 +396,7 @@
while (((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U)
#endif /* RTC_ICSR_WUTWF */
#if defined(RTC_ISR_WUTWF)
- while (((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U)
+ while (((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U)
#endif /* RTC_ISR_WUTWF */
{
if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
@@ -447,53 +407,33 @@
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_TIMEOUT;
- status = HAL_TIMEOUT;
}
}
- if(status == HAL_OK)
- {
- /* Reset all RTC CR register bits */
- hrtc->Instance->CR &= 0x00000000U;
+ /* Exit initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ /* Reset all RTC CR register bits */
+ hrtc->Instance->CR &= 0x00000000U;
- /* Reset other RTC registers */
- hrtc->Instance->WUTR = RTC_WUTR_WUT;
- hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
- hrtc->Instance->ALRMAR = 0x00000000U;
- hrtc->Instance->ALRMBR = 0x00000000U;
- hrtc->Instance->SHIFTR = 0x00000000U;
- hrtc->Instance->CALR = 0x00000000U;
- hrtc->Instance->ALRMASSR = 0x00000000U;
- hrtc->Instance->ALRMBSSR = 0x00000000U;
+ /* Reset other RTC registers */
+ hrtc->Instance->WUTR = RTC_WUTR_WUT;
+ hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
+ hrtc->Instance->ALRMAR = 0x00000000U;
+ hrtc->Instance->ALRMBR = 0x00000000U;
+ hrtc->Instance->SHIFTR = 0x00000000U;
+ hrtc->Instance->CALR = 0x00000000U;
+ hrtc->Instance->ALRMASSR = 0x00000000U;
+ hrtc->Instance->ALRMBSSR = 0x00000000U;
-#if defined(RTC_ICSR_INIT)
- /* Exit initialization mode */
- CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
-#endif /* RTC_ICSR_INIT */
#if defined(RTC_ISR_INIT)
- /* Reset ISR register and exit initialization mode */
- hrtc->Instance->ISR = 0x00000000U;
-
/* Reset Tamper configuration register */
hrtc->Instance->TAMPCR = 0x00000000U;
/* Reset Option register */
hrtc->Instance->OR = 0x00000000U;
#endif /* RTC_ISR_INIT */
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- status = HAL_ERROR;
- }
- }
}
}
@@ -899,6 +839,7 @@
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t tmpreg;
+HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -912,22 +853,9 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
{
if(Format == RTC_FORMAT_BIN)
{
@@ -979,39 +907,21 @@
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
/* Exit Initialization mode */
-#if defined(RTC_ICSR_INIT)
- CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
-#endif /* RTC_ICSR_INIT */
-#if defined(RTC_ISR_INIT)
- CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
-#endif /* RTC_ISR_INIT */
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
+ status = RTC_ExitInitMode(hrtc);
}
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
}
/**
@@ -1082,6 +992,7 @@
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
uint32_t datetmpreg;
+ HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -1124,60 +1035,33 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
{
/* Set the RTC_DR register */
hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
+
/* Exit Initialization mode */
-#if defined(RTC_ICSR_INIT)
- CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
-#endif /* RTC_ISR_INIT */
-#if defined(RTC_ISR_INIT)
- CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
-#endif /* RTC_ISR_INIT */
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY ;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
+ status = RTC_ExitInitMode(hrtc);
}
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+
+
}
/**
@@ -2056,7 +1940,7 @@
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart;
-
+ HAL_StatusTypeDef status = HAL_OK;
/* Check if the Initialization mode is set */
#if defined(RTC_ICSR_INITF)
if((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U)
@@ -2070,7 +1954,8 @@
{
if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ status = HAL_TIMEOUT;
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
}
}
}
@@ -2087,15 +1972,61 @@
{
if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ status = HAL_TIMEOUT;
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
}
}
}
#endif /* RTC_ISR_INITF */
- return HAL_OK;
+ return status;
}
+/**
+ * @brief Exit the RTC Initialization mode.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check if the Initialization mode is set */
+#if defined(RTC_ICSR_INITF)
+
+ /* Exit Initialization mode */
+ CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
+
+#elif defined(RTC_ISR_INITF)
+
+ /* Exit Initialization mode */
+ CLEAR_BIT(RTC->ISR, RTC_ISR_INITF);
+
+#endif /* RTC_ISR_INITF */
+ /* If CR_BYPSHAD bit = 0, wait for synchro */
+ if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
+ {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ status = HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ /* Clear BYPSHAD bit */
+ CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ status = HAL_TIMEOUT;
+ }
+ /* Restore BYPSHAD bit */
+ SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+ }
+
+ return status;
+}
/**
* @brief Convert a 2 digit decimal to BCD format.
diff --git a/Src/stm32h7xx_hal_rtc_ex.c b/Src/stm32h7xx_hal_rtc_ex.c
index 05d8195..e1a0d3a 100644
--- a/Src/stm32h7xx_hal_rtc_ex.c
+++ b/Src/stm32h7xx_hal_rtc_ex.c
@@ -1121,8 +1121,11 @@
/* Active Tampers must not be already enabled */
if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) != 0U)
{
- /* Disable all actives tampers with HAL_RTCEx_DeactivateActiveTampers and try again */
- return HAL_ERROR;
+ /* Disable all active tampers with HAL_RTCEx_DeactivateActiveTampers */
+ if (HAL_RTCEx_DeactivateActiveTampers(hrtc) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
}
/* Set TimeStamp on tamper detection */
@@ -1984,67 +1987,48 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Check RTC WUTWF flag is reset only when wake up timer enabled */
- if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
- {
- tickstart = HAL_GetTick();
+ /* Clear WUTE in RTC_CR to disable the wakeup timer */
+ CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- #if defined(RTC_ICSR_WUTWF)
- while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) != 0U)
- #endif /* RTC_ICSR_WUTWF */
- #if defined(RTC_ISR_WUTWF)
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U)
- #endif /* RTC_ISR_WUTWF */
+ /* Poll WUTWF until it is set in RTC_ICSR / RTC_ISR to make sure the access to wakeup autoreload
+ counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
+ calendar initialization mode. */
+#if defined(RTC_ISR_INITF)
+ if (READ_BIT(RTC->ISR, RTC_ISR_INITF) == 0U)
+#endif /* RTC_ISR_INITF */
+#if defined(RTC_ICSR_INITF)
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+#endif /* RTC_ICSR_INITF */
{
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ tickstart = HAL_GetTick();
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+#if defined(RTC_ICSR_WUTWF)
+ while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
+#endif /* RTC_ICSR_WUTWF */
+#if defined(RTC_ISR_WUTWF)
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
+#endif /* RTC_ISR_WUTWF */
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
}
- }
-
- __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- #if defined(RTC_ICSR_WUTWF)
- while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
- #endif /* RTC_ICSR_WUTWF */
- #if defined(RTC_ISR_WUTWF)
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
- #endif /* RTC_ISR_WUTWF */
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
/* Clear the Wakeup Timer clock source bits and configure the clock source in CR register */
- {
- uint32_t CR_tmp = hrtc->Instance->CR;
- CR_tmp &= (uint32_t)~RTC_CR_WUCKSEL;
- CR_tmp |= (uint32_t)WakeUpClock;
- hrtc->Instance->CR = CR_tmp;
- }
+ uint32_t CR_tmp = hrtc->Instance->CR;
+ CR_tmp &= (uint32_t)~RTC_CR_WUCKSEL;
+ CR_tmp |= (uint32_t)WakeUpClock;
+ hrtc->Instance->CR = CR_tmp;
/* Configure the Wakeup Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
@@ -2086,62 +2070,42 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Check RTC WUTWF flag is reset only when wake up timer enabled */
- if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
- {
- tickstart = HAL_GetTick();
+ /* Clear WUTE in RTC_CR to disable the wakeup timer */
+ CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- #if defined(RTC_ICSR_WUTWF)
- while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) != 0U)
- #endif /* RTC_ICSR_WUTWF */
- #if defined(RTC_ISR_WUTWF)
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U)
- #endif /* RTC_ISR_WUTWF */
+ /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
+ counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
+ calendar initialization mode. */
+#if defined(RTC_ISR_INITF)
+ if (READ_BIT(RTC->ISR, RTC_ISR_INITF) == 0U)
+#endif /* RTC_ISR_INITF */
+#if defined(RTC_ICSR_INITF)
+ if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+#endif /* RTC_ICSR_INITF */
{
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ tickstart = HAL_GetTick();
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+#if defined(RTC_ICSR_WUTWF)
+ while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
+#endif /* RTC_ICSR_WUTWF */
+#if defined(RTC_ISR_WUTWF)
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
+#endif /* RTC_ISR_WUTWF */
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
}
- }
- /* Disable the Wake-Up timer */
- __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
- /* Clear flag Wake-Up */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- #if defined(RTC_ICSR_WUTWF)
- while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
- #endif /* RTC_ICSR_WUTWF */
- #if defined(RTC_ISR_WUTWF)
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
- #endif /* RTC_ISR_WUTWF */
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
/* Configure the Wakeup Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
@@ -2732,6 +2696,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef * hrtc)
{
+ HAL_StatusTypeDef status;
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -2740,39 +2705,23 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
{
__HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
/* Exit Initialization mode */
-#if defined(RTC_ICSR_INIT)
- hrtc->Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT;
-#endif /* RTC_ICSR_INIT */
-#if defined(RTC_ISR_INIT)
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-#endif /* RTC_ISR_INIT */
+ status = RTC_ExitInitMode(hrtc);
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
+ if (status == HAL_OK)
+ {
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
@@ -2786,6 +2735,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef * hrtc)
{
+ HAL_StatusTypeDef status;
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -2794,38 +2744,25 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
{
__HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
/* Exit Initialization mode */
-#if defined(RTC_ICSR_INIT)
- hrtc->Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT;
-#endif /* RTC_ICSR_INIT */
-#if defined(RTC_ISR_INIT)
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-#endif /* RTC_ISR_INIT */
+ status = RTC_ExitInitMode(hrtc);
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
+ if (status == HAL_OK)
+ {
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ }
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
@@ -2901,11 +2838,15 @@
/**
* @brief Increment Monotonic counter.
* @param hrtc RTC handle
+ * @param Instance Monotonic counter Instance
+ * This parameter can be can be one of the following values :
+ * @arg RTC_MONOTONIC_COUNTER_1
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc)
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance)
{
UNUSED(hrtc);
+ UNUSED(Instance);
/* This register is read-only only and is incremented by one when a write access is done to this
register. This register cannot roll-over and is frozen when reaching the maximum value. */
CLEAR_REG(TAMP->COUNTR);
@@ -2916,12 +2857,16 @@
/**
* @brief Monotonic counter incrementation.
* @param hrtc RTC handle
+ * @param Instance Monotonic counter Instance
+ * This parameter can be can be one of the following values :
+ * @arg RTC_MONOTONIC_COUNTER_1
* @param Counter monotonic counter value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter)
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance)
{
UNUSED(hrtc);
+ UNUSED(Instance);
/* This register is read-only only and is incremented by one when a write access is done to this
register. This register cannot roll-over and is frozen when reaching the maximum value. */
*Counter = READ_REG(TAMP->COUNTR);
diff --git a/Src/stm32h7xx_hal_sai.c b/Src/stm32h7xx_hal_sai.c
index 36e7ee9..bdbdb62 100644
--- a/Src/stm32h7xx_hal_sai.c
+++ b/Src/stm32h7xx_hal_sai.c
@@ -244,7 +244,6 @@
/** @defgroup SAI_Private_Constants SAI Private Constants
* @{
*/
-#define SAI_FIFO_SIZE 8U
#define SAI_DEFAULT_TIMEOUT 4U
#define SAI_LONG_TIMEOUT 1000U
/**
@@ -617,8 +616,26 @@
if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE)
{
/* NODIV = 1 */
+ uint32_t tmpframelength;
+
+ if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
+ {
+ /* For SPDIF protocol, frame length is set by hardware to 64 */
+ tmpframelength = 64U;
+ }
+ else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL)
+ {
+ /* For AC97 protocol, frame length is set by hardware to 256 */
+ tmpframelength = 256U;
+ }
+ else
+ {
+ /* For free protocol, frame length is set by user */
+ tmpframelength = hsai->FrameInit.FrameLength;
+ }
+
/* (freq x 10) to keep Significant digits */
- tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength);
+ tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmpframelength);
}
else
{
@@ -635,8 +652,17 @@
{
hsai->Init.Mckdiv += 1U;
}
+
+ /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */
+ if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
+ {
+ hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1;
+ }
}
+ /* Check the SAI Block master clock divider parameter */
+ assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv));
+
/* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
{
@@ -2506,7 +2532,7 @@
*/
static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
{
- register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U);
+ uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Disable the SAI instance */
diff --git a/Src/stm32h7xx_hal_sd.c b/Src/stm32h7xx_hal_sd.c
index 700660d..b2467ca 100644
--- a/Src/stm32h7xx_hal_sd.c
+++ b/Src/stm32h7xx_hal_sd.c
@@ -472,7 +472,10 @@
Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
Init.BusWide = SDMMC_BUS_WIDE_1B;
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
- Init.ClockDiv = SDMMC_INIT_CLK_DIV;
+
+ /* Init Clock should be less or equal to 400Khz*/
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+ Init.ClockDiv = sdmmc_clk/(2U*400000U);
#if (USE_SD_TRANSCEIVER != 0U)
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
@@ -491,9 +494,9 @@
/* Set Power State to ON */
(void)SDMMC_PowerState_ON(hsd->Instance);
- /* wait 74 Cycles: required power up waiting time before starting
+ /* wait 74 Cycles: required power up waiting time before starting
the SD initialization sequence */
- sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC)/(2U*SDMMC_INIT_CLK_DIV);
+ sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv);
if(sdmmc_clk != 0U)
{
@@ -1477,7 +1480,7 @@
}
/* Send CMD38 ERASE */
- errorstate = SDMMC_CmdErase(hsd->Instance);
+ errorstate = SDMMC_CmdErase(hsd->Instance, 0UL);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
@@ -2127,7 +2130,7 @@
* @brief Returns information the information of the card which are stored on
* the CID register.
* @param hsd: Pointer to SD handle
- * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that
+ * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that
* contains all CID register parameters
* @retval HAL status
*/
@@ -2160,7 +2163,7 @@
* @brief Returns information the information of the card which are stored on
* the CSD register.
* @param hsd: Pointer to SD handle
- * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
+ * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
* contains all CSD register parameters
* @retval HAL status
*/
@@ -2274,7 +2277,7 @@
/**
* @brief Gets the SD status info.
* @param hsd: Pointer to SD handle
- * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
+ * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
* will contain the SD card status information
* @retval HAL status
*/
diff --git a/Src/stm32h7xx_hal_sd_ex.c b/Src/stm32h7xx_hal_sd_ex.c
index 7c4da99..d18122d 100644
--- a/Src/stm32h7xx_hal_sd_ex.c
+++ b/Src/stm32h7xx_hal_sd_ex.c
@@ -120,6 +120,7 @@
DmaBase0_reg = hsd->Instance->IDMABASE0;
DmaBase1_reg = hsd->Instance->IDMABASE1;
+
if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
diff --git a/Src/stm32h7xx_hal_smartcard.c b/Src/stm32h7xx_hal_smartcard.c
index 91b6bcb..2440595 100644
--- a/Src/stm32h7xx_hal_smartcard.c
+++ b/Src/stm32h7xx_hal_smartcard.c
@@ -107,8 +107,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
- Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
+ Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) ErrorCallback : Error Callback.
@@ -123,9 +123,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
@@ -140,13 +140,13 @@
(+) MspDeInitCallback : SMARTCARD MspDeInit.
[..]
- By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
+ By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
+ examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
- and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
+ and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -155,8 +155,8 @@
in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
- or @ref HAL_SMARTCARD_Init() function.
+ using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
+ or HAL_SMARTCARD_Init() function.
[..]
When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
@@ -725,62 +725,62 @@
(+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
[..]
- (+) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
+ (#) There are two modes of transfer:
+ (##) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) Non-Blocking mode: The communication is performed using Interrupts
+ (##) Non-Blocking mode: The communication is performed using Interrupts
or DMA, the relevant API's return the HAL status.
The end of the data processing will be indicated through the
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
- (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
will be executed respectively at the end of the Transmit or Receive process
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
error is detected.
- (+) Blocking mode APIs are :
- (++) HAL_SMARTCARD_Transmit()
- (++) HAL_SMARTCARD_Receive()
+ (#) Blocking mode APIs are :
+ (##) HAL_SMARTCARD_Transmit()
+ (##) HAL_SMARTCARD_Receive()
- (+) Non Blocking mode APIs with Interrupt are :
- (++) HAL_SMARTCARD_Transmit_IT()
- (++) HAL_SMARTCARD_Receive_IT()
- (++) HAL_SMARTCARD_IRQHandler()
+ (#) Non Blocking mode APIs with Interrupt are :
+ (##) HAL_SMARTCARD_Transmit_IT()
+ (##) HAL_SMARTCARD_Receive_IT()
+ (##) HAL_SMARTCARD_IRQHandler()
- (+) Non Blocking mode functions with DMA are :
- (++) HAL_SMARTCARD_Transmit_DMA()
- (++) HAL_SMARTCARD_Receive_DMA()
+ (#) Non Blocking mode functions with DMA are :
+ (##) HAL_SMARTCARD_Transmit_DMA()
+ (##) HAL_SMARTCARD_Receive_DMA()
- (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_SMARTCARD_TxCpltCallback()
- (++) HAL_SMARTCARD_RxCpltCallback()
- (++) HAL_SMARTCARD_ErrorCallback()
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (##) HAL_SMARTCARD_TxCpltCallback()
+ (##) HAL_SMARTCARD_RxCpltCallback()
+ (##) HAL_SMARTCARD_ErrorCallback()
[..]
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (++) HAL_SMARTCARD_Abort()
- (++) HAL_SMARTCARD_AbortTransmit()
- (++) HAL_SMARTCARD_AbortReceive()
- (++) HAL_SMARTCARD_Abort_IT()
- (++) HAL_SMARTCARD_AbortTransmit_IT()
- (++) HAL_SMARTCARD_AbortReceive_IT()
+ (##) HAL_SMARTCARD_Abort()
+ (##) HAL_SMARTCARD_AbortTransmit()
+ (##) HAL_SMARTCARD_AbortReceive()
+ (##) HAL_SMARTCARD_Abort_IT()
+ (##) HAL_SMARTCARD_AbortTransmit_IT()
+ (##) HAL_SMARTCARD_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (++) HAL_SMARTCARD_AbortCpltCallback()
- (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
- (++) HAL_SMARTCARD_AbortReceiveCpltCallback()
+ (##) HAL_SMARTCARD_AbortCpltCallback()
+ (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (##) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
- If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+ (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -824,14 +824,23 @@
/* Disable the Peripheral first to update mode for TX master */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
@@ -851,15 +860,23 @@
{
return HAL_TIMEOUT;
}
- /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+
+ /* Disable the Peripheral first to update mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
- /* Disable the Peripheral first to update modes */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+ for Transmit phase. Disable this receiver block. */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+ }
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* At end of Tx process, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -980,14 +997,23 @@
/* Disable the Peripheral first to update mode for TX master */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
/* Configure Tx interrupt processing */
if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE)
{
@@ -1128,14 +1154,23 @@
/* Disable the Peripheral first to update mode for TX master */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
/* Set the SMARTCARD DMA transfer complete callback */
hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
@@ -2966,15 +3001,22 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
}
- /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ /* Disable the Peripheral first to update mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
- /* Disable the Peripheral first to update modes */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+ for Transmit phase. Disable this receiver block. */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+ }
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Tx process is ended, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
diff --git a/Src/stm32h7xx_hal_smartcard_ex.c b/Src/stm32h7xx_hal_smartcard_ex.c
index ac0e473..7043575 100644
--- a/Src/stm32h7xx_hal_smartcard_ex.c
+++ b/Src/stm32h7xx_hal_smartcard_ex.c
@@ -59,10 +59,10 @@
* @{
*/
/* UART RX FIFO depth */
-#define RX_FIFO_DEPTH 8U
+#define RX_FIFO_DEPTH 16U
/* UART TX FIFO depth */
-#define TX_FIFO_DEPTH 8U
+#define TX_FIFO_DEPTH 16U
/**
* @}
*/
diff --git a/Src/stm32h7xx_hal_smbus.c b/Src/stm32h7xx_hal_smbus.c
index 99ab885..6840ad9 100644
--- a/Src/stm32h7xx_hal_smbus.c
+++ b/Src/stm32h7xx_hal_smbus.c
@@ -203,18 +203,18 @@
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
-static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
-static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
/**
* @}
*/
@@ -1801,7 +1801,7 @@
* @param StatusFlags Value of Interrupt Flags.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
{
uint16_t DevAddress;
@@ -2085,7 +2085,7 @@
* @param StatusFlags Value of Interrupt Flags.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
{
uint8_t TransferDirection;
uint16_t SlaveAddrCode;
@@ -2341,7 +2341,7 @@
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
{
uint32_t tmpisr = 0UL;
@@ -2381,7 +2381,7 @@
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
{
uint32_t tmpisr = 0UL;
uint32_t tmpstate = hsmbus->State;
@@ -2453,7 +2453,7 @@
* @param hsmbus SMBUS handle.
* @retval None
*/
-static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus)
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
{
uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
@@ -2554,7 +2554,7 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
@@ -2603,7 +2603,7 @@
* @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -2620,7 +2620,7 @@
* @param hsmbus SMBUS handle.
* @retval None
*/
-static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus)
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
{
/* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
/* it request implicitly to generate a restart condition */
diff --git a/Src/stm32h7xx_hal_spdifrx.c b/Src/stm32h7xx_hal_spdifrx.c
index c68750c..1f78727 100644
--- a/Src/stm32h7xx_hal_spdifrx.c
+++ b/Src/stm32h7xx_hal_spdifrx.c
@@ -853,7 +853,7 @@
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+ uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
@@ -938,7 +938,7 @@
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+ uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
@@ -1023,7 +1023,7 @@
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+ uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
@@ -1124,7 +1124,7 @@
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+ uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
diff --git a/Src/stm32h7xx_hal_spi.c b/Src/stm32h7xx_hal_spi.c
index a4eeae4..90efc7a 100644
--- a/Src/stm32h7xx_hal_spi.c
+++ b/Src/stm32h7xx_hal_spi.c
@@ -1321,20 +1321,20 @@
hspi->RxXferCount --;
initial_RxXferCount = hspi->RxXferCount;
}
- }
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_ERROR;
+ }
}
}
/* Transmit and Receive data in 16 Bit mode */
diff --git a/Src/stm32h7xx_hal_tim.c b/Src/stm32h7xx_hal_tim.c
index f1165b4..678efc9 100644
--- a/Src/stm32h7xx_hal_tim.c
+++ b/Src/stm32h7xx_hal_tim.c
@@ -199,7 +199,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup TIM_Private_Functions
@@ -221,6 +221,7 @@
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
@@ -306,6 +307,13 @@
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -339,6 +347,13 @@
HAL_TIM_Base_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -391,6 +406,12 @@
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
@@ -401,9 +422,6 @@
__HAL_TIM_ENABLE(htim);
}
- /* Change the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -418,13 +436,10 @@
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the TIM state*/
+ /* Set the TIM state */
htim->State = HAL_TIM_STATE_READY;
/* Return function status */
@@ -443,6 +458,15 @@
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
@@ -466,12 +490,16 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
+
/* Disable the TIM Update interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
@@ -490,6 +518,7 @@
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+ /* Set the TIM state */
if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
@@ -507,7 +536,7 @@
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
/* Set the DMA Period elapsed callbacks */
@@ -555,7 +584,7 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
+ /* Set the TIM state */
htim->State = HAL_TIM_STATE_READY;
/* Return function status */
@@ -638,6 +667,13 @@
/* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -671,6 +707,13 @@
HAL_TIM_OC_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -730,6 +773,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
@@ -780,6 +832,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -802,6 +857,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -918,6 +982,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -942,11 +1009,12 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -954,12 +1022,12 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
switch (Channel)
@@ -1132,8 +1200,8 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1215,6 +1283,13 @@
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -1248,6 +1323,13 @@
HAL_TIM_PWM_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1307,6 +1389,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
@@ -1357,8 +1448,8 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1381,6 +1472,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -1497,6 +1597,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1521,11 +1624,12 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -1533,12 +1637,12 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
switch (Channel)
@@ -1710,8 +1814,8 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1793,6 +1897,13 @@
/* Init the base time for the input capture */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -1826,6 +1937,13 @@
HAL_TIM_IC_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1879,10 +1997,23 @@
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
@@ -1919,6 +2050,10 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1937,10 +2072,23 @@
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2044,6 +2192,10 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -2064,16 +2216,21 @@
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2081,12 +2238,13 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
switch (Channel)
@@ -2202,6 +2360,9 @@
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2240,14 +2401,12 @@
break;
}
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -2284,6 +2443,9 @@
* requires a timer reset to avoid unexpected direction
* due to DIR bit readonly in center aligned mode.
* Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+ * @note When the timer instance is initialized in One Pulse mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
* @param htim TIM One Pulse handle
* @param OnePulseMode Select the One pulse mode.
* This parameter can be one of the following values:
@@ -2339,6 +2501,15 @@
/* Configure the OPM Mode */
htim->Instance->CR1 |= OnePulseMode;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -2372,6 +2543,15 @@
HAL_TIM_OnePulse_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2422,9 +2602,29 @@
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2479,6 +2679,12 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -2494,9 +2700,29 @@
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2562,6 +2788,12 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -2600,6 +2832,9 @@
* @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
* Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
* using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+ * @note When the timer instance is initialized in Encoder mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
* @param htim TIM Encoder Interface handle
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
@@ -2697,6 +2932,15 @@
/* Write to TIMx CCER */
htim->Instance->CCER = tmpccer;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -2731,6 +2975,15 @@
HAL_TIM_Encoder_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2782,9 +3035,59 @@
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Check the parameters */
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+
/* Enable the encoder interface channels */
switch (Channel)
{
@@ -2856,6 +3159,20 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
/* Return function status */
return HAL_OK;
}
@@ -2872,9 +3189,59 @@
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Check the parameters */
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
switch (Channel)
@@ -2954,8 +3321,19 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
return HAL_OK;
@@ -2977,27 +3355,95 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Check the parameters */
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
{
- return HAL_BUSY;
- }
- else if (htim->State == HAL_TIM_STATE_READY)
- {
- if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
- return HAL_ERROR;
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData1 == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ return HAL_ERROR;
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData2 == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
}
}
else
{
- /* nothing to do */
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
}
switch (Channel)
@@ -3095,6 +3541,7 @@
default:
break;
}
+
/* Return function status */
return HAL_OK;
}
@@ -3147,8 +3594,19 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
return HAL_OK;
@@ -3417,8 +3875,6 @@
/* Process Locked */
__HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
-
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -3485,8 +3941,6 @@
break;
}
- htim->State = HAL_TIM_STATE_READY;
-
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -3517,8 +3971,6 @@
/* Process Locked */
__HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
-
if (Channel == TIM_CHANNEL_1)
{
/* TI1 Configuration */
@@ -3582,8 +4034,6 @@
htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
}
- htim->State = HAL_TIM_STATE_READY;
-
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -3617,8 +4067,6 @@
/* Process Locked */
__HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
-
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -3727,8 +4175,6 @@
break;
}
- htim->State = HAL_TIM_STATE_READY;
-
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -3963,11 +4409,11 @@
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -3975,7 +4421,7 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
}
}
else
@@ -4112,8 +4558,6 @@
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -4178,6 +4622,9 @@
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
}
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
/* Return function status */
return status;
}
@@ -4291,11 +4738,11 @@
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -4303,7 +4750,7 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
}
}
else
@@ -4441,8 +4888,6 @@
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -4507,6 +4952,9 @@
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
}
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
/* Return function status */
return status;
}
@@ -5797,6 +6245,54 @@
}
/**
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM handle
+ * @retval Active channel
+ */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
+{
+ return htim->Channel;
+}
+
+/**
+ * @brief Return actual state of the TIM channel.
+ * @param htim TIM handle
+ * @param Channel TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5
+ * @arg TIM_CHANNEL_6: TIM Channel 6
+ * @retval TIM Channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+ return channel_state;
+}
+
+/**
+ * @brief Return actual state of a DMA burst operation.
+ * @param htim TIM handle
+ * @retval DMA burst state
+ */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+ return htim->DMABurstState;
+}
+
+/**
* @}
*/
@@ -5817,13 +6313,38 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
@@ -5835,23 +6356,41 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else
{
@@ -5876,8 +6415,6 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
@@ -5917,23 +6454,45 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else
{
@@ -5958,8 +6517,6 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
@@ -5999,7 +6556,10 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
+ if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
@@ -6017,8 +6577,6 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedHalfCpltCallback(htim);
#else
@@ -6035,7 +6593,10 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
+ if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
@@ -6053,8 +6614,6 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerHalfCpltCallback(htim);
#else
diff --git a/Src/stm32h7xx_hal_tim_ex.c b/Src/stm32h7xx_hal_tim_ex.c
index 6851f88..d1cb18c 100644
--- a/Src/stm32h7xx_hal_tim_ex.c
+++ b/Src/stm32h7xx_hal_tim_ex.c
@@ -55,7 +55,7 @@
the commutation event).
(#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
@@ -91,9 +91,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
/* Exported functions --------------------------------------------------------*/
@@ -124,6 +126,9 @@
*/
/**
* @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+ * @note When the timer instance is initialized in Hall Sensor Interface mode,
+ * timer channels 1 and channel 2 are reserved and cannot be used for
+ * other purpose.
* @param htim TIM Hall Sensor Interface handle
* @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
@@ -209,6 +214,15 @@
htim->Instance->CR2 &= ~TIM_CR2_MMS;
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -242,6 +256,15 @@
HAL_TIMEx_HallSensor_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -289,12 +312,31 @@
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
@@ -325,6 +367,12 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -337,10 +385,29 @@
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the capture compare Interrupts 1 event */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@@ -379,6 +446,12 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -393,29 +466,36 @@
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if (((uint32_t)pData == 0U) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
+
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
@@ -464,9 +544,14 @@
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -513,6 +598,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@@ -555,6 +649,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -577,6 +674,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -685,6 +791,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -709,24 +818,25 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if (((uint32_t)pData == 0U) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
switch (Channel)
@@ -734,11 +844,11 @@
case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
@@ -753,11 +863,11 @@
case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
@@ -772,11 +882,11 @@
case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
@@ -864,8 +974,8 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -922,6 +1032,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@@ -963,6 +1082,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -985,6 +1107,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -1093,6 +1224,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1117,35 +1251,37 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if (((uint32_t)pData == 0U) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
@@ -1160,11 +1296,11 @@
case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
@@ -1179,11 +1315,11 @@
case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
@@ -1271,8 +1407,8 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1312,11 +1448,27 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
+ HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
- /* Enable the complementary One Pulse output */
+ /* Check the TIM channels state */
+ if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -1337,12 +1489,14 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
- /* Disable the complementary One Pulse output */
+ /* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1350,6 +1504,10 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1366,17 +1524,33 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
+ HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+ /* Check the TIM channels state */
+ if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- /* Enable the complementary One Pulse output */
+ /* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -1397,6 +1571,8 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
@@ -1406,8 +1582,9 @@
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- /* Disable the complementary One Pulse output */
+ /* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1415,6 +1592,10 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -2233,6 +2414,27 @@
}
/**
+ * @brief Return actual state of the TIM complementary channel.
+ * @param htim TIM handle
+ * @param ChannelN TIM Complementary channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @retval TIM Complementary channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
+{
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+
+ channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+
+ return channel_state;
+}
+/**
* @}
*/
@@ -2285,6 +2487,103 @@
/**
+ * @brief TIM DMA Delay Pulse complete callback (complementary channel).
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA error callback (complementary channel)
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
+ HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral
* @param Channel specifies the TIM Channel
diff --git a/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c b/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c
index 3e5aaa9..61213a7 100644
--- a/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c
+++ b/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c
@@ -228,11 +228,11 @@
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
- HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
- HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
+ HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
+ HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
uwTickPrio = TickPriority;
- return HAL_OK;
+ return HAL_OK;
}
else
{
diff --git a/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c b/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c
index da35f78..fca84e1 100644
--- a/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c
+++ b/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c
@@ -215,11 +215,11 @@
/* Configure the HAL Tick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
- HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U);
- HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
+ HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U);
+ HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
uwTickPrio = TickPriority;
- return HAL_OK;
+ return HAL_OK;
}
else
{
diff --git a/Src/stm32h7xx_hal_timebase_tim_template.c b/Src/stm32h7xx_hal_timebase_tim_template.c
index 9e424d5..5ac80a2 100644
--- a/Src/stm32h7xx_hal_timebase_tim_template.c
+++ b/Src/stm32h7xx_hal_timebase_tim_template.c
@@ -65,10 +65,10 @@
/*Configure the TIM6 IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
- HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
+ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
- /* Enable the TIM6 global Interrupt */
- HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
+ /* Enable the TIM6 global Interrupt */
+ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
uwTickPrio = TickPriority;
}
else
diff --git a/Src/stm32h7xx_hal_uart.c b/Src/stm32h7xx_hal_uart.c
index 2e0a4c6..0810120 100644
--- a/Src/stm32h7xx_hal_uart.c
+++ b/Src/stm32h7xx_hal_uart.c
@@ -191,6 +191,8 @@
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions
* @{
@@ -1065,6 +1067,8 @@
pdata16bits = NULL;
}
+ __HAL_UNLOCK(huart);
+
while (huart->TxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
@@ -1092,8 +1096,6 @@
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
else
@@ -1159,6 +1161,8 @@
pdata16bits = NULL;
}
+ __HAL_UNLOCK(huart);
+
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
@@ -1182,8 +1186,6 @@
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
else
@@ -2857,9 +2859,9 @@
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
- uint32_t usartdiv = 0x00000000U;
+ uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
- uint32_t lpuart_ker_ck_pres = 0x00000000U;
+ uint32_t lpuart_ker_ck_pres;
PLL2_ClocksTypeDef pll2_clocks;
PLL3_ClocksTypeDef pll3_clocks;
uint32_t pclk;
@@ -2928,41 +2930,45 @@
switch (clocksource)
{
case UART_CLOCKSOURCE_D3PCLK1:
- lpuart_ker_ck_pres = (HAL_RCCEx_GetD3PCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = HAL_RCCEx_GetD3PCLK1Freq();
break;
case UART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- lpuart_ker_ck_pres = (pll2_clocks.PLL2_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = pll2_clocks.PLL2_Q_Frequency;
break;
case UART_CLOCKSOURCE_PLL3:
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- lpuart_ker_ck_pres = (pll3_clocks.PLL3_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = pll3_clocks.PLL3_Q_Frequency;
break;
case UART_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
{
- lpuart_ker_ck_pres = ((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
}
else
{
- lpuart_ker_ck_pres = ((uint32_t) HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = (uint32_t) HSI_VALUE;
}
break;
case UART_CLOCKSOURCE_CSI:
- lpuart_ker_ck_pres = ((uint32_t)CSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = (uint32_t) CSI_VALUE;
break;
case UART_CLOCKSOURCE_LSE:
- lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = (uint32_t) LSE_VALUE;
break;
default:
+ pclk = 0U;
ret = HAL_ERROR;
break;
}
- /* if proper clock source reported */
- if (lpuart_ker_ck_pres != 0U)
+ /* If proper clock source reported */
+ if (pclk != 0U)
{
- /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+ /* Compute clock after Prescaler */
+ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
+
+ /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
{
@@ -2970,42 +2976,9 @@
}
else
{
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_D3PCLK1:
- pclk = HAL_RCCEx_GetD3PCLK1Freq();
- usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- break;
- case UART_CLOCKSOURCE_PLL2:
- HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- usartdiv = (uint32_t)(UART_DIV_LPUART(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- break;
- case UART_CLOCKSOURCE_PLL3:
- HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- usartdiv = (uint32_t)(UART_DIV_LPUART(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- break;
- case UART_CLOCKSOURCE_HSI:
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- {
- usartdiv = (uint32_t)(UART_DIV_LPUART((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
- }
- else
- {
- usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- }
- break;
- case UART_CLOCKSOURCE_CSI:
- usartdiv = (uint32_t)(UART_DIV_LPUART(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- break;
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- break;
- default:
- ret = HAL_ERROR;
- break;
- }
-
- /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */
+ /* Check computed UsartDiv value is in allocated range
+ (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
+ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, (uint64_t)huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
{
huart->Instance->BRR = usartdiv;
@@ -3014,8 +2987,8 @@
{
ret = HAL_ERROR;
}
- } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
- } /* if (lpuart_ker_ck_pres != 0) */
+ } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+ } /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
@@ -3024,51 +2997,54 @@
{
case UART_CLOCKSOURCE_D2PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_D2PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = pll2_clocks.PLL2_Q_Frequency;
break;
case UART_CLOCKSOURCE_PLL3:
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = pll3_clocks.PLL3_Q_Frequency;
break;
case UART_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
{
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
}
else
{
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t) HSI_VALUE;
}
break;
case UART_CLOCKSOURCE_CSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t) CSI_VALUE;
break;
case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t) LSE_VALUE;
break;
default:
+ pclk = 0U;
ret = HAL_ERROR;
break;
}
/* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ if (pclk != 0U)
{
- brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- huart->Instance->BRR = brrtemp;
- }
- else
- {
- ret = HAL_ERROR;
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ huart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
}
}
else
@@ -3077,49 +3053,52 @@
{
case UART_CLOCKSOURCE_D2PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_D2PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = pll2_clocks.PLL2_Q_Frequency;
break;
case UART_CLOCKSOURCE_PLL3:
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = pll3_clocks.PLL3_Q_Frequency;
break;
case UART_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
{
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
}
else
{
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t) HSI_VALUE;
}
break;
case UART_CLOCKSOURCE_CSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t) CSI_VALUE;
break;
case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t) LSE_VALUE;
break;
default:
+ pclk = 0U;
ret = HAL_ERROR;
break;
}
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ if (pclk != 0U)
{
- huart->Instance->BRR = usartdiv;
- }
- else
- {
- ret = HAL_ERROR;
+ /* USARTDIV must be greater than or equal to 0d16 */
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ huart->Instance->BRR = usartdiv;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
}
}
@@ -3292,7 +3271,7 @@
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
-
+
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
@@ -3300,10 +3279,10 @@
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
huart->ErrorCode = HAL_UART_ERROR_RTO;
-
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
+
return HAL_TIMEOUT;
}
}
diff --git a/Src/stm32h7xx_hal_uart_ex.c b/Src/stm32h7xx_hal_uart_ex.c
index d667310..3a899a1 100644
--- a/Src/stm32h7xx_hal_uart_ex.c
+++ b/Src/stm32h7xx_hal_uart_ex.c
@@ -60,10 +60,10 @@
* @{
*/
/* UART RX FIFO depth */
-#define RX_FIFO_DEPTH 8U
+#define RX_FIFO_DEPTH 16U
/* UART TX FIFO depth */
-#define TX_FIFO_DEPTH 8U
+#define TX_FIFO_DEPTH 16U
/**
* @}
*/
diff --git a/Src/stm32h7xx_hal_usart.c b/Src/stm32h7xx_hal_usart.c
index 8f9d2b6..caf70aa 100644
--- a/Src/stm32h7xx_hal_usart.c
+++ b/Src/stm32h7xx_hal_usart.c
@@ -2150,7 +2150,7 @@
/* USART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
{
- __HAL_UART_CLEAR_FLAG(husart, UART_CLEAR_RTOF);
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
husart->ErrorCode |= HAL_USART_ERROR_RTO;
}
diff --git a/Src/stm32h7xx_hal_usart_ex.c b/Src/stm32h7xx_hal_usart_ex.c
index f38b03d..ac5bade 100644
--- a/Src/stm32h7xx_hal_usart_ex.c
+++ b/Src/stm32h7xx_hal_usart_ex.c
@@ -58,10 +58,10 @@
* @{
*/
/* USART RX FIFO depth */
-#define RX_FIFO_DEPTH 8U
+#define RX_FIFO_DEPTH 16U
/* USART TX FIFO depth */
-#define TX_FIFO_DEPTH 8U
+#define TX_FIFO_DEPTH 16U
/**
* @}
*/
diff --git a/Src/stm32h7xx_hal_wwdg.c b/Src/stm32h7xx_hal_wwdg.c
index d37af40..94db743 100644
--- a/Src/stm32h7xx_hal_wwdg.c
+++ b/Src/stm32h7xx_hal_wwdg.c
@@ -31,11 +31,21 @@
(+) WWDG Counter refresh is allowed between the following limits :
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
- (+) Typical values:
- (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
- max timeout before reset: approximately 73.14µs
- (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
- max timeout before reset: approximately 599.18ms
+ (+) Typical values (case of STM32H74x/5x devices):
+ (++) Counter min (T[5;0] = 0x00) @100MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 40.96µs
+ (++) Counter max (T[5;0] = 0x3F) @100MHz (PCLK1) with prescaler dividing by 128:
+ max timeout before reset: approximately 335.54ms
+ (+) Typical values (case of STM32H7Ax/Bx devices):
+ (++) Counter min (T[5;0] = 0x00) @140MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 29.25µs
+ (++) Counter max (T[5;0] = 0x3F) @140MHz (PCLK1) with prescaler dividing by 128:
+ max timeout before reset: approximately 239.67ms
+ (+) Typical values (case of STM32H72x/3x devices):
+ (++) Counter min (T[5;0] = 0x00) @125MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 32.76µs
+ (++) Counter max (T[5;0] = 0x3F) @125MHz (PCLK1) with prescaler dividing by 128:
+ max timeout before reset: approximately 268.43ms
==============================================================================
##### How to use this driver #####
diff --git a/Src/stm32h7xx_ll_adc.c b/Src/stm32h7xx_ll_adc.c
index 151c9f6..df01887 100644
--- a/Src/stm32h7xx_ll_adc.c
+++ b/Src/stm32h7xx_ll_adc.c
@@ -333,7 +333,7 @@
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
- if(ADCxy_COMMON == ADC12_COMMON)
+ if (ADCxy_COMMON == ADC12_COMMON)
{
/* Force reset of ADC clock (core clock) */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12);
@@ -608,19 +608,19 @@
/* Reset register CFGR */
CLEAR_BIT(ADCx->CFGR,
- ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
+ (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
| ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
| ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
| ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
| ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_RES
- | ADC_CFGR_DMNGT )
+ | ADC_CFGR_DMNGT)
);
SET_BIT(ADCx->CFGR, ADC_CFGR_JQDIS);
/* Reset register CFGR2 */
CLEAR_BIT(ADCx->CFGR2,
- ( ADC_CFGR2_LSHIFT | ADC_CFGR2_OVSR | ADC_CFGR2_RSHIFT1
+ (ADC_CFGR2_LSHIFT | ADC_CFGR2_OVSR | ADC_CFGR2_RSHIFT1
| ADC_CFGR2_RSHIFT4 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT2
| ADC_CFGR2_RSHIFT1 | ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS
| ADC_CFGR2_OVSS | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
@@ -642,6 +642,29 @@
);
/* Reset register TR1 */
+#if defined(ADC_VER_V5_V90)
+ if (ADCx == ADC3)
+ {
+ /* Reset register TR1 */
+ MODIFY_REG(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT | ADC3_TR1_HT1 | ADC3_TR1_LT1, ADC3_TR1_HT1);
+
+ /* Reset register TR2 */
+ MODIFY_REG(ADCx->HTR1_TR2, ADC3_TR2_HT2 | ADC3_TR2_LT2, ADC3_TR2_HT2);
+
+ /* Reset register TR3 */
+ MODIFY_REG(ADCx->RES1_TR3, ADC3_TR3_HT3 | ADC3_TR3_LT3, ADC3_TR3_HT3);
+ }
+ else
+ {
+ CLEAR_BIT(ADCx->LTR1_TR1, ADC_LTR_LT);
+ SET_BIT(ADCx->HTR1_TR2, ADC_HTR_HT);
+
+ CLEAR_BIT(ADCx->LTR2_DIFSEL, ADC_LTR_LT);
+ SET_BIT(ADCx->HTR2_CALFACT, ADC_HTR_HT);
+ CLEAR_BIT(ADCx->LTR3_RES10, ADC_LTR_LT);
+ SET_BIT(ADCx->HTR3_RES11, ADC_HTR_HT);
+ }
+#else
CLEAR_BIT(ADCx->LTR1, ADC_LTR_LT);
SET_BIT(ADCx->HTR1, ADC_HTR_HT);
@@ -649,6 +672,7 @@
SET_BIT(ADCx->HTR2, ADC_HTR_HT);
CLEAR_BIT(ADCx->LTR3, ADC_LTR_LT);
SET_BIT(ADCx->HTR3, ADC_HTR_HT);
+#endif
/* Reset register SQR1 */
CLEAR_BIT(ADCx->SQR1,
@@ -701,6 +725,25 @@
CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
/* Reset register DIFSEL */
+#if defined(ADC_VER_V5_V90)
+ if (ADCx == ADC3)
+ {
+ CLEAR_BIT(ADCx->LTR2_DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(ADCx->HTR2_CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+ }
+ else
+ {
+ CLEAR_BIT(ADCx->DIFSEL_RES12, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(ADCx->CALFACT_RES13, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+ /* Reset register CALFACT2 */
+ CLEAR_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT);
+ }
+#else
CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
/* Reset register CALFACT */
@@ -708,6 +751,7 @@
/* Reset register CALFACT2 */
CLEAR_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT);
+#endif
}
else
{
diff --git a/Src/stm32h7xx_ll_cordic.c b/Src/stm32h7xx_ll_cordic.c
new file mode 100644
index 0000000..da5b22b
--- /dev/null
+++ b/Src/stm32h7xx_ll_cordic.c
@@ -0,0 +1,105 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_ll_cordic.c
+ * @author MCD Application Team
+ * @brief CORDIC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_cordic.h"
+#include "stm32h7xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32H7xx_LL_Driver
+ * @{
+ */
+
+#if defined(CORDIC)
+
+/** @addtogroup CORDIC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORDIC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORDIC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-Initialize CORDIC peripheral registers to their default reset values.
+ * @param CORDICx CORDIC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: CORDIC registers are de-initialized
+ * - ERROR: CORDIC registers are not de-initialized
+ */
+ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_CORDIC_ALL_INSTANCE(CORDICx));
+
+ if (CORDICx == CORDIC)
+ {
+ /* Force CORDIC reset */
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_CORDIC);
+
+ /* Release CORDIC reset */
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_CORDIC);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CORDIC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_dma.c b/Src/stm32h7xx_ll_dma.c
index 5d309ee..9db91e9 100644
--- a/Src/stm32h7xx_ll_dma.c
+++ b/Src/stm32h7xx_ll_dma.c
@@ -68,11 +68,13 @@
#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
-#if defined(ADC3)
+#if defined(TIM24)
+#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_TIM24_TRIG))
+#elif defined(ADC3)
#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_ADC3))
#else
#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_USART10_TX))
-#endif /* ADC3 */
+#endif /* TIM24 */
#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
diff --git a/Src/stm32h7xx_ll_fmac.c b/Src/stm32h7xx_ll_fmac.c
new file mode 100644
index 0000000..337d4f7
--- /dev/null
+++ b/Src/stm32h7xx_ll_fmac.c
@@ -0,0 +1,167 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_ll_fmac.c
+ * @author MCD Application Team
+ * @brief FMAC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_fmac.h"
+#include "stm32h7xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32H7xx_LL_Driver
+ * @{
+ */
+
+#if defined(FMAC)
+
+/** @addtogroup FMAC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup FMAC_LL_Private_Macros
+ * @{
+ */
+
+/** @brief Check if the watermark value is a valid one.
+ * @param __VALUE__ Watermak value.
+ * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid)
+ */
+#define IS_LL_FMAC_WM(__VALUE__) (((__VALUE__) == LL_FMAC_WM_0_THRESHOLD_1) \
+ || ((__VALUE__) == LL_FMAC_WM_1_THRESHOLD_2) \
+ || ((__VALUE__) == LL_FMAC_WM_2_THRESHOLD_4) \
+ || ((__VALUE__) == LL_FMAC_WM_3_THRESHOLD_8))
+
+/** @brief Check if the function ID is a valid one.
+ * @param __VALUE__ Function ID.
+ * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid)
+ */
+#define IS_LL_FMAC_FUNC(__VALUE__) (((__VALUE__) == LL_FMAC_FUNC_LOAD_X1) \
+ || ((__VALUE__) == LL_FMAC_FUNC_LOAD_X2) \
+ || ((__VALUE__) == LL_FMAC_FUNC_LOAD_Y) \
+ || ((__VALUE__) == LL_FMAC_FUNC_CONVO_FIR) \
+ || ((__VALUE__) == LL_FMAC_FUNC_IIR_DIRECT_FORM_1))
+
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMAC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMAC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Initialize FMAC peripheral registers to their default reset values.
+ * @param FMACx FMAC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: FMAC registers are initialized
+ * - ERROR: FMAC registers are not initialized
+ */
+ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_FMAC_ALL_INSTANCE(FMACx));
+
+ if (FMACx == FMAC)
+ {
+ /* Perform the reset */
+ LL_FMAC_EnableReset(FMACx);
+
+ /* Wait until flag is reset */
+ while (LL_FMAC_IsEnabledReset(FMACx) != 0UL)
+ {
+ }
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief De-Initialize FMAC peripheral registers to their default reset values.
+ * @param FMACx FMAC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: FMAC registers are de-initialized
+ * - ERROR: FMAC registers are not de-initialized
+ */
+ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_FMAC_ALL_INSTANCE(FMACx));
+
+ if (FMACx == FMAC)
+ {
+ /* Force FMAC reset */
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_FMAC);
+
+ /* Release FMAC reset */
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_FMAC);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(FMAC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_i2c.c b/Src/stm32h7xx_ll_i2c.c
index a1eac83..09e20cb 100644
--- a/Src/stm32h7xx_ll_i2c.c
+++ b/Src/stm32h7xx_ll_i2c.c
@@ -31,7 +31,7 @@
* @{
*/
-#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
+#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) || defined (I2C5)
/** @defgroup I2C_LL I2C
* @{
@@ -124,6 +124,16 @@
/* Release reset of I2C clock */
LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_I2C4);
}
+#if defined(I2C5)
+ else if (I2Cx == I2C5)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C5);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C5);
+ }
+#endif
else
{
status = ERROR;
@@ -232,7 +242,7 @@
* @}
*/
-#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
+#endif /* I2C1 || I2C2 || I2C3 || I2C4 || I2C5 */
/**
* @}
diff --git a/Src/stm32h7xx_ll_mdma.c b/Src/stm32h7xx_ll_mdma.c
index 5e3ab2b..1c33f82 100644
--- a/Src/stm32h7xx_ll_mdma.c
+++ b/Src/stm32h7xx_ll_mdma.c
@@ -254,7 +254,7 @@
((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
-#else /* STM32H7A3/B3 devices */
+#elif defined (OCTOSPI1) && defined (JPEG) /* STM32H7A3/B3 devices */
#define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
@@ -287,7 +287,34 @@
((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END) || \
((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH) || \
((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC))
-
+#else /* STM32H723/25/33/35 devices */
+#define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
+ ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_FIFO_TH) || \
+ ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
+ ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
+ ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
+ ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
+ ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END) || \
+ ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH) || \
+ ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC))
#endif /* QUADSPI && JPEG && DSI */
/**
* @}
diff --git a/Src/stm32h7xx_ll_pwr.c b/Src/stm32h7xx_ll_pwr.c
index 31045a9..28ce161 100644
--- a/Src/stm32h7xx_ll_pwr.c
+++ b/Src/stm32h7xx_ll_pwr.c
@@ -55,9 +55,13 @@
*/
ErrorStatus LL_PWR_DeInit(void)
{
+#if defined (PWR_WKUPCR_WKUPC3)
WRITE_REG(PWR->WKUPCR, (PWR_WKUPCR_WKUPC1 | PWR_WKUPCR_WKUPC2 | PWR_WKUPCR_WKUPC3 | \
PWR_WKUPCR_WKUPC4 | PWR_WKUPCR_WKUPC5 | PWR_WKUPCR_WKUPC6));
-
+#else
+ WRITE_REG(PWR->WKUPCR, (PWR_WKUPCR_WKUPC1 | PWR_WKUPCR_WKUPC2 | \
+ PWR_WKUPCR_WKUPC4 | PWR_WKUPCR_WKUPC6));
+#endif /* defined (PWR_WKUPCR_WKUPC3) */
return SUCCESS;
}
diff --git a/Src/stm32h7xx_ll_rcc.c b/Src/stm32h7xx_ll_rcc.c
index 9dd56c5..282b9ab 100644
--- a/Src/stm32h7xx_ll_rcc.c
+++ b/Src/stm32h7xx_ll_rcc.c
@@ -56,16 +56,20 @@
|| ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE))
-#if defined(LL_RCC_SAI4A_CLKSOURCE)
+#if defined(SAI3)
#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SAI23_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
+#elif defined(SAI4)
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
#else
#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SAI2A_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SAI2B_CLKSOURCE))
-#endif /* LL_RCC_SAI4A_CLKSOURCE */
+#endif /* SAI3 */
#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
@@ -115,6 +119,13 @@
*/
void LL_RCC_DeInit(void)
{
+ /* Increasing the CPU frequency */
+ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
/* Set HSION bit */
SET_BIT(RCC->CR, RCC_CR_HSION);
@@ -199,6 +210,14 @@
/* Clear reset source flags */
SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
}
/**
@@ -810,14 +829,14 @@
#if defined(SAI3)
case LL_RCC_SAI23_CLKSOURCE_PLL1Q:
#endif /* SAI3 */
+#if defined(SAI4)
+ case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
+ case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
+#endif /* SAI4 */
#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
case LL_RCC_SAI2A_CLKSOURCE_PLL1Q:
case LL_RCC_SAI2B_CLKSOURCE_PLL1Q:
-#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
-#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
- case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
- case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
-#endif /* (SAI4_Block_A) || (SAI4_Block_B) */
+#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
if (LL_RCC_PLL1_IsReady() != 0U)
{
LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
@@ -829,14 +848,14 @@
#if defined(SAI3)
case LL_RCC_SAI23_CLKSOURCE_PLL2P:
#endif /* SAI3 */
+#if defined(SAI4)
+ case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
+ case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
+#endif /* SAI4 */
#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
case LL_RCC_SAI2A_CLKSOURCE_PLL2P:
case LL_RCC_SAI2B_CLKSOURCE_PLL2P:
-#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
-#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
- case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
- case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
-#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
if (LL_RCC_PLL2_IsReady() != 0U)
{
LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
@@ -848,14 +867,14 @@
#if defined(SAI3)
case LL_RCC_SAI23_CLKSOURCE_PLL3P:
#endif /* SAI3 */
+#if defined(SAI4)
+ case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
+ case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
+#endif /* SAI4 */
#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
case LL_RCC_SAI2A_CLKSOURCE_PLL3P:
case LL_RCC_SAI2B_CLKSOURCE_PLL3P:
-#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
-#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
- case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
- case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
-#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
if (LL_RCC_PLL3_IsReady() != 0U)
{
LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
@@ -867,14 +886,14 @@
#if defined(SAI3)
case LL_RCC_SAI23_CLKSOURCE_I2S_CKIN:
#endif /* SAI3 */
+#if defined(SAI4)
+ case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
+ case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
+#endif /* SAI4 */
#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
case LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN:
case LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN:
-#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
-#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
- case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
- case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
-#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
sai_frequency = EXTERNAL_CLOCK_VALUE;
break;
@@ -882,14 +901,14 @@
#if defined(SAI3)
case LL_RCC_SAI23_CLKSOURCE_CLKP:
#endif /* SAI3 */
+#if defined(SAI4)
+ case LL_RCC_SAI4A_CLKSOURCE_CLKP:
+ case LL_RCC_SAI4B_CLKSOURCE_CLKP:
+#endif /* SAI4 */
#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
case LL_RCC_SAI2A_CLKSOURCE_CLKP:
case LL_RCC_SAI2B_CLKSOURCE_CLKP:
-#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
-#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
- case LL_RCC_SAI4A_CLKSOURCE_CLKP:
- case LL_RCC_SAI4B_CLKSOURCE_CLKP:
-#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
break;
@@ -1558,7 +1577,7 @@
#if defined(OCTOSPI1) || defined(OCTOSPI2)
/**
* @brief Return OSPI clock frequency
- * @param QSPIxSource This parameter can be one of the following values:
+ * @param OSPIxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_OSPI_CLKSOURCE
* @retval OSPI clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
diff --git a/Src/stm32h7xx_ll_sdmmc.c b/Src/stm32h7xx_ll_sdmmc.c
index 5d39b9f..4c2e72d 100644
--- a/Src/stm32h7xx_ll_sdmmc.c
+++ b/Src/stm32h7xx_ll_sdmmc.c
@@ -728,16 +728,17 @@
/**
* @brief Send the Erase command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param EraseType Type of erase to be performed
* @retval HAL status
*/
-uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Set Block Size for Card */
- sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.Argument = EraseType;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
@@ -1204,7 +1205,7 @@
{
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
@@ -1234,7 +1235,7 @@
/* 8 is the number of required instructions cycles for the below loop statement.
The Timeout is expressed in ms */
- register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
+ uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
do
{
@@ -1367,7 +1368,7 @@
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
@@ -1411,7 +1412,7 @@
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
@@ -1453,7 +1454,7 @@
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
@@ -1524,7 +1525,7 @@
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
diff --git a/Src/stm32h7xx_ll_tim.c b/Src/stm32h7xx_ll_tim.c
index a11ca83..688f0c1 100644
--- a/Src/stm32h7xx_ll_tim.c
+++ b/Src/stm32h7xx_ll_tim.c
@@ -32,7 +32,7 @@
* @{
*/
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
/** @addtogroup TIM_LL
* @{
@@ -1369,7 +1369,7 @@
* @}
*/
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 */
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 || TIM23 || TIM24 */
/**
* @}
diff --git a/Src/stm32h7xx_ll_usb.c b/Src/stm32h7xx_ll_usb.c
index 18ed741..986ba4f 100644
--- a/Src/stm32h7xx_ll_usb.c
+++ b/Src/stm32h7xx_ll_usb.c
@@ -612,6 +612,12 @@
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
+ if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
+ }
+
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
@@ -622,6 +628,12 @@
}
else
{
+ if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
+ }
+
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
@@ -647,11 +659,23 @@
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
+ if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
+ }
+
USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
}
else
{
+ if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
+ }
+
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
}
@@ -1324,7 +1348,7 @@
if ((USBx->CID & (0x1U << 8)) != 0U)
{
- if (cfg.speed == USB_OTG_SPEED_FULL)
+ if (cfg.speed == USBH_FSLS_SPEED)
{
/* Force Device Enumeration to FS/LS mode only */
USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
diff --git a/Src/stm32h7xx_ll_utils.c b/Src/stm32h7xx_ll_utils.c
index a039e79..a24c6be 100644
--- a/Src/stm32h7xx_ll_utils.c
+++ b/Src/stm32h7xx_ll_utils.c
@@ -41,16 +41,21 @@
/** @addtogroup UTILS_LL_Private_Constants
* @{
*/
-#if (POWER_DOMAINS_NUMBER == 3U)
-#define UTILS_MAX_FREQUENCY_SCALE1 400000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
+#if (STM32H7_DEV_ID == 0x450UL)
+#define UTILS_MAX_FREQUENCY_SCALE1 480000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
#define UTILS_MAX_FREQUENCY_SCALE2 300000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
#define UTILS_MAX_FREQUENCY_SCALE3 200000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
-#else
+#elif (STM32H7_DEV_ID == 0x480UL)
#define UTILS_MAX_FREQUENCY_SCALE0 280000000U /*!< Maximum frequency for system clock at power scale0, in Hz */
#define UTILS_MAX_FREQUENCY_SCALE1 225000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
#define UTILS_MAX_FREQUENCY_SCALE2 160000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
#define UTILS_MAX_FREQUENCY_SCALE3 88000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
-#endif /*POWER_DOMAINS_NUMBER == 3U*/
+#elif (STM32H7_DEV_ID == 0x483UL)
+#define UTILS_MAX_FREQUENCY_SCALE0 550000000U /*!< Maximum frequency for system clock at power scale0, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE1 200000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2 150000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE3 85000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
+#endif /*STM32H7_DEV_ID == 0x450UL*/
/* Defines used for PLL range */
#define UTILS_PLLVCO_INPUT_MIN1 1000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
@@ -79,7 +84,7 @@
#define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */
/* Defines used for FLASH latency according to HCLK Frequency */
-#if (POWER_DOMAINS_NUMBER == 2U)
+#if (STM32H7_DEV_ID == 0x480UL)
#define UTILS_SCALE0_LATENCY0_FREQ 44000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */
#define UTILS_SCALE0_LATENCY1_FREQ 88000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */
#define UTILS_SCALE0_LATENCY2_FREQ 132000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */
@@ -106,11 +111,11 @@
#define UTILS_SCALE3_LATENCY2_FREQ 66000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
#define UTILS_SCALE3_LATENCY3_FREQ 88000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
-#else
+#elif (STM32H7_DEV_ID == 0x450UL)
#define UTILS_SCALE1_LATENCY0_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */
#define UTILS_SCALE1_LATENCY1_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
-#define UTILS_SCALE1_LATENCY2_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+#define UTILS_SCALE1_LATENCY2_FREQ 240000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
#define UTILS_SCALE2_LATENCY0_FREQ 55000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */
#define UTILS_SCALE2_LATENCY1_FREQ 110000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
@@ -122,7 +127,27 @@
#define UTILS_SCALE3_LATENCY2_FREQ 135000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
#define UTILS_SCALE3_LATENCY3_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
#define UTILS_SCALE3_LATENCY4_FREQ 225000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
-#endif /*POWER_DOMAINS_NUMBER == 2U*/
+
+#elif (STM32H7_DEV_ID == 0x483UL)
+
+#define UTILS_SCALE0_LATENCY0_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */
+#define UTILS_SCALE0_LATENCY1_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */
+#define UTILS_SCALE0_LATENCY2_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */
+#define UTILS_SCALE0_LATENCY3_FREQ 275000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */
+
+#define UTILS_SCALE1_LATENCY0_FREQ 67000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */
+#define UTILS_SCALE1_LATENCY1_FREQ 133000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define UTILS_SCALE1_LATENCY2_FREQ 200000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
+
+#define UTILS_SCALE2_LATENCY0_FREQ 50000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */
+#define UTILS_SCALE2_LATENCY1_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define UTILS_SCALE2_LATENCY2_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
+
+#define UTILS_SCALE3_LATENCY0_FREQ 35000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */
+#define UTILS_SCALE3_LATENCY1_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define UTILS_SCALE3_LATENCY2_FREQ 85000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
+
+#endif /*STM32H7_DEV_ID == 0x480UL*/
/**
* @}
*/
@@ -201,7 +226,7 @@
(((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \
(((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE)))
-#if (POWER_DOMAINS_NUMBER == 3U)
+#if (STM32H7_DEV_ID == 0x450UL)
#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
@@ -210,7 +235,7 @@
(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
-#endif /*POWER_DOMAINS_NUMBER == 3U*/
+#endif /* STM32H7_DEV_ID == 0x450UL */
#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
|| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
@@ -304,6 +329,7 @@
* @}
*/
+#if (STM32H7_DEV_ID == 0x450UL)
/** @addtogroup UTILS_EF_SYSTEM
* @brief System Configuration functions
*
@@ -314,9 +340,8 @@
[..]
System, AHB and APB buses clocks configuration
-#if (POWER_DOMAINS_NUMBER == 3U)
- (+) The maximum frequency of the SYSCLK is 400 MHz and HCLK is 200 MHz.
- (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 100 MHz.
+ (+) The maximum frequency of the SYSCLK is 480 MHz(*) and HCLK is 240 MHz.
+ (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 120 MHz.
@endverbatim
@internal
Depending on the device voltage range, the maximum frequency should be
@@ -331,14 +356,29 @@
(++) |----------------|-------------------|-------------------|-------------------|
(++) |1WS(2CPU cycle) | 70 < HCLK <= 140 | 55 < HCLK <= 110 | 45 < HCLK <= 90 |
(++) |----------------|-------------------|-------------------|-------------------|
- (++) |2WS(3CPU cycle) | 140 < HCLK <= 210 | 110 < HCLK <= 165 | 90 < HCLK <= 135 |
+ (++) |2WS(3CPU cycle) | 140 < HCLK <= 240 | 110 < HCLK <= 165 | 90 < HCLK <= 135 |
(++) |----------------|-------------------|-------------------|-------------------|
(++) |3WS(4CPU cycle) | -- | 165 < HCLK <= 220 | 135 < HCLK <= 180 |
(++) |----------------|-------------------|-------------------|-------------------|
(++) |4WS(5CPU cycle) | -- | -- | 180 < HCLK <= 225 |
(++) +----------------------------------------------------------------------------+
-#else
+ (*) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
+ @endinternal
+ * @{
+ */
+
+#elif (STM32H7_DEV_ID == 0x480UL)
+/** @addtogroup UTILS_EF_SYSTEM
+ * @brief System Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### System Configuration functions #####
+ ===============================================================================
+ [..]
+ System, AHB and APB buses clocks configuration
+
(+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 280 MHz.
(+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 140 MHz.
@endverbatim
@@ -368,10 +408,48 @@
(++) |7WS(8CPU cycle) | -- | -- | -- | -- |
(++) +------------------------------------------------------------------------------------------------+
-#endif
@endinternal
* @{
*/
+
+#elif (STM32H7_DEV_ID == 0x483UL)
+/** @addtogroup UTILS_EF_SYSTEM
+ * @brief System Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### System Configuration functions #####
+ ===============================================================================
+ [..]
+ System, AHB and APB buses clocks configuration
+
+ (+) The maximum frequency of the SYSCLK is 550 MHz(*) and HCLK is 275 MHz.
+ (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 137.5 MHz.
+ @endverbatim
+ @internal
+ Depending on the device voltage range, the maximum frequency should be
+ adapted accordingly:
+ (++) +------------------------------------------------------------------------------------------------+
+ (++) | Wait states | HCLK clock frequency (MHz) |
+ (++) | |-------------------------------------------------------------------------------|
+ (++) | (Latency) | voltage range 0 | voltage range 1 | voltage range 2 | voltage range 3 |
+ (++) | | 1.26V - 1.40V | 1.15V - 1.26V | 1.05V - 1.15V | 0.95V - 1.05V |
+ (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+ (++) |0WS(1CPU cycle) | 0 < HCLK <= 70 | 0 < HCLK <= 67 | 0 < HCLK <= 50 | 0 < HCLK <= 35 |
+ (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+ (++) |1WS(2CPU cycle) | 70 < HCLK <= 140 | 67 < HCLK <= 133 | 50 < HCLK <= 100 | 35 < HCLK <= 70 |
+ (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+ (++) |2WS(3CPU cycle) | 140 < HCLK <= 210 | 133 < HCLK <= 200 | 100 < HCLK <= 150 | 70 < HCLK <= 85 |
+ (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+ (++) |3WS(4CPU cycle) | 210 < HCLK <= 275 | -- | -- | -- |
+ (++) +----------------|-------------------|-------------------|-------------------|-------------------|
+
+ (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
+ @endinternal
+ * @{
+ */
+#endif /* STM32H7_DEV_ID == 0x450UL */
+
#if defined (DUAL_CORE)
/**
* @brief This function sets directly SystemCoreClock CMSIS variable.
@@ -405,8 +483,8 @@
* @note Function is based on the following formula:
* - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
* - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
- * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN)
- * - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz is reach (PLLVCO_output / PLLP)
+ * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(***) (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLP: ensure that max frequency at 550000000 Hz(*), 480000000 Hz(**) or 280000000 Hz(***) is reach (PLLVCO_output / PLLP)
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
@@ -415,7 +493,9 @@
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*
- * (*) : For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
+ * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
+ * (**) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
+ * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
*
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
@@ -495,8 +575,8 @@
* @note Function is based on the following formula:
* - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
- * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN)
- * - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz(*) is reached (PLLVCO_output / PLLP)
+ * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(***) (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLP: ensure that max frequency at 550000000 Hz(*), 480000000 Hz(**) or 280000000 Hz(***) is reached (PLLVCO_output / PLLP)
* @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
* @param HSEBypass This parameter can be one of the following values:
* @arg @ref LL_UTILS_HSEBYPASS_ON
@@ -509,7 +589,9 @@
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*
- * (*) : For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
+ * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
+ * (**) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
+ * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
*
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
@@ -622,9 +704,10 @@
}
else
{
-#if (POWER_DOMAINS_NUMBER == 2U)
+#if (STM32H7_DEV_ID == 0x480UL) || (STM32H7_DEV_ID == 0x483UL)
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0)
{
+#if (STM32H7_DEV_ID == 0x480UL)
if((HCLK_Frequency > UTILS_SCALE0_LATENCY5_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ))
{
/* 264 < HCLK <= 280 => 6WS (7 CPU cycles) */
@@ -641,6 +724,9 @@
latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
+#elif (STM32H7_DEV_ID == 0x483UL)
+ if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
+#endif /* STM32H7_DEV_ID == 0x480UL */
{
/* 132 < HCLK <= 176 => 3WS (4 CPU cycles) */
latency = LL_FLASH_LATENCY_3;
@@ -664,6 +750,7 @@
status = ERROR;
}
}
+#if (STM32H7_DEV_ID == 0x480UL)
else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
{
if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ))
@@ -686,7 +773,12 @@
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
{
if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
-#endif /*POWER_DOMAINS_NUMBER == 2U*/
+#endif /* STM32H7_DEV_ID == 0x480UL */
+#else
+ if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+ {
+ if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
+#endif /* STM32H7_DEV_ID == 0x480UL || STM32H7_DEV_ID == 0x483UL */
{
/* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */
latency = LL_FLASH_LATENCY_2;
@@ -707,7 +799,8 @@
}
else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
{
-#if (POWER_DOMAINS_NUMBER == 2U)
+#if (STM32H7_DEV_ID == 0x480UL) || (STM32H7_DEV_ID == 0x450UL)
+#if (STM32H7_DEV_ID == 0x480UL)
if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ))
{
/* 136 < HCLK <= 160 => 4WS (5 CPU cycles) */
@@ -716,12 +809,15 @@
else if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
#else
if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
-#endif /*POWER_DOMAINS_NUMBER == 2U*/
+#endif /* STM32H7_DEV_ID == 0x480UL */
{
/* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */
latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
+#else
+ if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
+#endif /* STM32H7_DEV_ID == 0x480UL || STM32H7_DEV_ID == 0x450UL */
{
/* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */
latency = LL_FLASH_LATENCY_2;
@@ -742,7 +838,8 @@
}
else /* Scale 3 */
{
-#if (POWER_DOMAINS_NUMBER == 3U)
+#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL)
+#if (STM32H7_DEV_ID == 0x450UL)
if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ))
{
/* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */
@@ -751,12 +848,15 @@
else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
#else
if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
-#endif /*POWER_DOMAINS_NUMBER == 3U*/
+#endif /*STM32H7_DEV_ID == 0x450UL*/
{
/* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */
latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
+#else
+ if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
+#endif /* STM32H7_DEV_ID == 0x450UL || STM32H7_DEV_ID == 0x480UL */
{
/* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */
latency = LL_FLASH_LATENCY_2;
@@ -795,7 +895,6 @@
status = ERROR;
}
}
-
}
return status;
@@ -891,12 +990,12 @@
/* Calculate the new HCLK frequency */
new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
- /* Increasing the number of wait states because of higher CPU frequency */
+ /* Increasing the number of wait states because of higher CPU frequency */
if (SystemD2Clock < new_hclk_frequency)
- {
+ {
/* Set FLASH latency to highest latency */
status = LL_SetFlashLatency(new_hclk_frequency);
- }
+ }
/* Update system clock configuration */
if(status == SUCCESS)
@@ -934,27 +1033,27 @@
LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
/* Decreasing the number of wait states because of lower CPU frequency */
- if (SystemD2Clock > new_hclk_frequency)
- {
- /* Set FLASH latency to lowest latency */
- status = LL_SetFlashLatency(new_hclk_frequency);
- }
+ if (SystemD2Clock > new_hclk_frequency)
+ {
+ /* Set FLASH latency to lowest latency */
+ status = LL_SetFlashLatency(new_hclk_frequency);
+ }
- /* Update the SystemD2Clock global variable */
+ /* Update the SystemD2Clock global variable */
#if defined(RCC_D1CFGR_HPRE)
- SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+ SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
- SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+ SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
- /* Update SystemCoreClock variable */
+ /* Update SystemCoreClock variable */
#if defined(DUAL_CORE) && defined(CORE_CM4)
- LL_SetSystemCoreClock(SystemD2Clock);
+ LL_SetSystemCoreClock(SystemD2Clock);
#else
- LL_SetSystemCoreClock(SYSCLK_Frequency);
+ LL_SetSystemCoreClock(SYSCLK_Frequency);
#endif /* DUAL_CORE && CORE_CM4 */
- }
+ }
return status;
