Release v1.3.0
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index c91daa7..71534e7 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -37,14 +37,16 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5)
+#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
+#if defined(STM32U5)
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
+#endif /* STM32U5 || STM32H7 || STM32MP1 */
/**
* @}
*/
@@ -110,6 +112,7 @@
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
#endif /* STM32U5 */
+
/**
* @}
*/
@@ -211,6 +214,11 @@
#endif
#endif
+
+#if defined(STM32U5)
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
+#endif
+
/**
* @}
*/
@@ -231,9 +239,11 @@
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
+#if defined(STM32C0)
+#else
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
-
+#endif
/**
* @}
*/
@@ -263,7 +273,7 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
@@ -500,7 +510,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-#if defined(STM32G0)
+#if defined(STM32G0) || defined(STM32C0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
@@ -525,6 +535,9 @@
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
+#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
+#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
+#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
/**
@@ -667,6 +680,8 @@
#if defined(STM32U5)
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
#endif /* STM32U5 */
/**
* @}
@@ -677,7 +692,9 @@
*/
#if defined(STM32U5)
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
#endif /* STM32U5 */
+
/**
* @}
*/
@@ -996,7 +1013,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -1080,8 +1097,8 @@
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@@ -1092,15 +1109,22 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32F7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 */
+
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
+#if defined(STM32F7) || defined(STM32H7)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
-#endif /* STM32H7 */
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 */
/**
* @}
@@ -1267,7 +1291,7 @@
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
-#if defined(STM32U5) || defined(STM32MP2)
+#if defined(STM32U5)
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
#endif
@@ -1705,7 +1729,6 @@
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
-#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
@@ -2944,6 +2967,11 @@
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
+#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
+#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@@ -3408,7 +3436,7 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3521,8 +3549,8 @@
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
#if defined(STM32U5)
-#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
-#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@@ -3538,15 +3566,20 @@
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
-#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
-#endif
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
/**
* @}
@@ -3564,7 +3597,8 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || \
+ defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32C0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3628,7 +3662,7 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
@@ -3965,6 +3999,16 @@
* @}
*/
+/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32F7)
+#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
+#endif /* STM32F7 */
+/**
+ * @}
+ */
+
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/
diff --git a/Inc/stm32wlxx_hal.h b/Inc/stm32wlxx_hal.h
index 3dcb318..a823722 100644
--- a/Inc/stm32wlxx_hal.h
+++ b/Inc/stm32wlxx_hal.h
@@ -23,7 +23,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32wlxx_hal_conf.h"
@@ -52,6 +52,7 @@
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
+
/**
* @}
*/
@@ -70,10 +71,34 @@
uint32_t InterruptMask2; /*!< The SYSCFG Interrupt Mask to be configured.
This parameter can be a combination of @ref SYSCFG_IM_GRP2 */
} SYSCFG_InterruptTypeDef;
+
/**
* @}
*/
-#endif
+#endif /* DUAL_CORE */
+
+#if defined(STM32WL5Mxx)
+/** @defgroup HAL_RADIO_SWITCH_CONFIG RADIO Switch Config
+ * @{
+ */
+typedef enum
+{
+ RADIO_SWITCH_OFF = 0,
+ RADIO_SWITCH_RX = 1,
+ RADIO_SWITCH_RFO_LP = 2,
+ RADIO_SWITCH_RFO_HP = 3,
+} HAL_RADIO_SwitchConfig_TypeDef;
+
+typedef enum
+{
+ RADIO_RFO_LP_MAXPOWER = 0,
+ RADIO_RFO_HP_MAXPOWER,
+} HAL_RADIO_RFOMaxPowerConfig_TypeDef;
+
+/**
+ * @}
+ */
+#endif /* STM32WL5Mxx */
/**
* @}
@@ -184,8 +209,8 @@
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
/**
- * @}
- */
+ * @}
+ */
#if defined(DUAL_CORE)
/** @defgroup SYSCFG_IM_GRP1 SYSCFG INTERRUPT MASK GROUP1
@@ -294,6 +319,29 @@
*/
#endif /* DUAL_CORE */
+#if defined(STM32WL5Mxx)
+/** @defgroup RADIO_Exported_Constants RADIO Exported Constants
+ * @{
+ */
+#define RADIO_CONF_TCXO_NOT_SUPPORTED 0U
+#define RADIO_CONF_TCXO_SUPPORTED 1U
+
+#define RADIO_CONF_DCDC_NOT_SUPPORTED 0U
+#define RADIO_CONF_DCDC_SUPPORTED 1U
+
+#define RADIO_CONF_RFO_HP_MAX_22_dBm ((int32_t) 22)
+#define RADIO_CONF_RFO_HP_MAX_20_dBm ((int32_t) 20)
+#define RADIO_CONF_RFO_HP_MAX_17_dBm ((int32_t) 17)
+#define RADIO_CONF_RFO_HP_MAX_14_dBm ((int32_t) 14)
+#define RADIO_CONF_RFO_LP_MAX_15_dBm ((int32_t) 15)
+#define RADIO_CONF_RFO_LP_MAX_14_dBm ((int32_t) 14)
+#define RADIO_CONF_RFO_LP_MAX_10_dBm ((int32_t) 10)
+
+/**
+ * @}
+ */
+#endif /* STM32WL5Mxx */
+
/**
* @}
*/
@@ -535,7 +583,8 @@
* @arg @ref SYSCFG_FLAG_PKASRAM_BUSY PKA SRAM Erase Ongoing
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_FLAG_SRAM2_PE)? SYSCFG->CFGR2 : SYSCFG->SCSR) & (__FLAG__))!= 0) ? 1 : 0)
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_FLAG_SRAM2_PE)? SYSCFG->CFGR2 : SYSCFG->SCSR) &\
+ (__FLAG__))!= 0) ? 1 : 0)
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
*/
@@ -588,73 +637,73 @@
#if defined(DUAL_CORE)
#if defined(CORE_CM0PLUS)
#define IS_SYSCFG_IM_GRP1(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED) && \
- ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) == HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_RTCALARM ) == HAL_SYSCFG_GRP1_RTCALARM ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_RTCWKUP ) == HAL_SYSCFG_GRP1_RTCWKUP ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_RCC ) == HAL_SYSCFG_GRP1_RCC ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_FLASH ) == HAL_SYSCFG_GRP1_FLASH ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_PKA ) == HAL_SYSCFG_GRP1_PKA ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_AES ) == HAL_SYSCFG_GRP1_AES ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_COMP ) == HAL_SYSCFG_GRP1_COMP ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_ADC ) == HAL_SYSCFG_GRP1_ADC ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_DAC ) == HAL_SYSCFG_GRP1_DAC ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI0 ) == HAL_SYSCFG_GRP1_EXTI0 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI1 ) == HAL_SYSCFG_GRP1_EXTI1 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI2 ) == HAL_SYSCFG_GRP1_EXTI2 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI3 ) == HAL_SYSCFG_GRP1_EXTI3 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI4 ) == HAL_SYSCFG_GRP1_EXTI4 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 )))
+ ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) == HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_RTCALARM ) == HAL_SYSCFG_GRP1_RTCALARM ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_RTCWKUP ) == HAL_SYSCFG_GRP1_RTCWKUP ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_RCC ) == HAL_SYSCFG_GRP1_RCC ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_FLASH ) == HAL_SYSCFG_GRP1_FLASH ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_PKA ) == HAL_SYSCFG_GRP1_PKA ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_AES ) == HAL_SYSCFG_GRP1_AES ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_COMP ) == HAL_SYSCFG_GRP1_COMP ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_ADC ) == HAL_SYSCFG_GRP1_ADC ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_DAC ) == HAL_SYSCFG_GRP1_DAC ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI0 ) == HAL_SYSCFG_GRP1_EXTI0 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI1 ) == HAL_SYSCFG_GRP1_EXTI1 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI2 ) == HAL_SYSCFG_GRP1_EXTI2 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI3 ) == HAL_SYSCFG_GRP1_EXTI3 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI4 ) == HAL_SYSCFG_GRP1_EXTI4 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 )))
#define IS_SYSCFG_IM_GRP2(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED) && \
- ((((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH1) == HAL_SYSCFG_GRP2_DMA1CH1) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH2) == HAL_SYSCFG_GRP2_DMA1CH2) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH3) == HAL_SYSCFG_GRP2_DMA1CH3) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH4) == HAL_SYSCFG_GRP2_DMA1CH4) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH5) == HAL_SYSCFG_GRP2_DMA1CH5) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH6) == HAL_SYSCFG_GRP2_DMA1CH6) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH7) == HAL_SYSCFG_GRP2_DMA1CH7) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH1) == HAL_SYSCFG_GRP2_DMA2CH1) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH2) == HAL_SYSCFG_GRP2_DMA2CH2) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH3) == HAL_SYSCFG_GRP2_DMA2CH3) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH4) == HAL_SYSCFG_GRP2_DMA2CH4) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH5) == HAL_SYSCFG_GRP2_DMA2CH5) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH6) == HAL_SYSCFG_GRP2_DMA2CH6) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH7) == HAL_SYSCFG_GRP2_DMA2CH7) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_DMAMUX1) == HAL_SYSCFG_GRP2_DMAMUX1) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_PVM3 ) == HAL_SYSCFG_GRP2_PVM3 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD )))
+ ((((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH1) == HAL_SYSCFG_GRP2_DMA1CH1) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH2) == HAL_SYSCFG_GRP2_DMA1CH2) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH3) == HAL_SYSCFG_GRP2_DMA1CH3) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH4) == HAL_SYSCFG_GRP2_DMA1CH4) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH5) == HAL_SYSCFG_GRP2_DMA1CH5) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH6) == HAL_SYSCFG_GRP2_DMA1CH6) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH7) == HAL_SYSCFG_GRP2_DMA1CH7) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH1) == HAL_SYSCFG_GRP2_DMA2CH1) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH2) == HAL_SYSCFG_GRP2_DMA2CH2) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH3) == HAL_SYSCFG_GRP2_DMA2CH3) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH4) == HAL_SYSCFG_GRP2_DMA2CH4) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH5) == HAL_SYSCFG_GRP2_DMA2CH5) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH6) == HAL_SYSCFG_GRP2_DMA2CH6) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH7) == HAL_SYSCFG_GRP2_DMA2CH7) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_DMAMUX1) == HAL_SYSCFG_GRP2_DMAMUX1) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_PVM3 ) == HAL_SYSCFG_GRP2_PVM3 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD )))
#else /* !CORE_CM0PLUS */
#define IS_SYSCFG_IM_GRP1(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED) && \
- ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) == HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \
- (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 )))
+ ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) == HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 )))
#define IS_SYSCFG_IM_GRP2(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED) && \
- ((((__VALUE__) & HAL_SYSCFG_GRP2_PVM3) == HAL_SYSCFG_GRP2_PVM3) || \
- (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD )))
+ ((((__VALUE__) & HAL_SYSCFG_GRP2_PVM3) == HAL_SYSCFG_GRP2_PVM3) || \
+ (((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD )))
#endif /* CORE_CM0PLUS */
#endif /* DUAL_CORE */
@@ -774,6 +823,24 @@
* @}
*/
+#if defined( STM32WL5Mxx)
+/** @addtogroup HAL_Exported_Functions_Group5 HAL Radio Configuration functions
+ * @{
+ */
+
+/* RADIO Control functions ****************************************************/
+HAL_StatusTypeDef HAL_RADIO_Init(void);
+HAL_StatusTypeDef HAL_RADIO_DeInit(void);
+HAL_StatusTypeDef HAL_RADIO_SetSwitchConfig(HAL_RADIO_SwitchConfig_TypeDef Config);
+uint8_t HAL_RADIO_IsTCXO(void);
+uint8_t HAL_RADIO_IsDCDC(void);
+int32_t HAL_RADIO_GetRFOMaxPowerConfig(HAL_RADIO_RFOMaxPowerConfig_TypeDef Config);
+
+/**
+ * @}
+ */
+#endif /* STM32WL5Mxx */
+
/**
* @}
*/
@@ -788,6 +855,6 @@
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* __STM32WLxx_HAL_H */
diff --git a/Inc/stm32wlxx_hal_adc.h b/Inc/stm32wlxx_hal_adc.h
index 698439c..1552cdb 100644
--- a/Inc/stm32wlxx_hal_adc.h
+++ b/Inc/stm32wlxx_hal_adc.h
@@ -62,27 +62,33 @@
/**
* @brief Structure definition of ADC instance and ADC group regular.
* @note Parameters of this structure are shared within 2 scopes:
- * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
+ * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC
+ * groups regular and injected): ClockPrescaler, Resolution, DataAlign,
* ScanConvMode, EOCSelection, LowPowerAutoWait.
* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled
- * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
+ * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on
+ * group regular.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behavior in case of intended action to update another parameter
- * (which fulfills the ADC state condition) on the fly).
+ * without error reporting (as it can be the expected behavior in case of intended action to update another
+ * parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
- uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
+ uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous
+ clock derived from system clock or PLL (Refer to reference manual for list of
+ clocks available)) and clock prescaler.
This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
Note: The ADC clock configuration is common to all ADC instances.
- Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
- if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
- must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
- Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
+ Note: In case of synchronous clock mode based on HCLK/1, the configuration must
+ be enabled only if the system clock has a 50% duty clock cycle (APB
+ prescaler configured inside RCC must be bypassed and PCLK clock must have
+ 50% duty cycle). Refer to reference manual for details.
+ Note: In case of usage of asynchronous clock, the selected clock must be
+ preliminarily enabled at RCC top level.
Note: This parameter can be modified only if all ADC instances are disabled. */
uint32_t Resolution; /*!< Configure the ADC resolution.
@@ -93,15 +99,16 @@
This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular.
- On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are
- available:
+ On this STM32 series, ADC group regular sequencer both modes "fully configurable"
+ or "not fully configurable" are available:
- sequencer configured to fully configurable:
sequencer length and each rank affectation to a channel are configurable.
- Sequence length: Set number of ranks in the scan sequence.
- Sequence direction: Unless specified in parameters, sequencer
scan direction is forward (from rank 1 to rank n).
- sequencer configured to not fully configurable:
- sequencer length and each rank affectation to a channel are fixed by channel HW number.
+ sequencer length and each rank affectation to a channel are fixed by channel
+ HW number.
- Sequence length: Number of ranks in the scan sequence is
defined by number of channels set in the sequence,
rank of each channel is fixed by channel HW number.
@@ -109,101 +116,156 @@
- Sequence direction: Unless specified in parameters, sequencer
scan direction is forward (from lowest channel number to
highest channel number).
- This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
- Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have
+ main sequence subdivided in successive parts. Sequencer is automatically enabled
+ if several channels are set (sequencer cannot be disabled, as it can be the case
+ on other STM32 devices):
If only 1 channel is set: Conversion is performed in single mode.
If several channels are set: Conversions are performed in sequence mode.
This parameter can be a value of @ref ADC_Scan_mode */
- uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
+ uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
+ interruption: end of unitary conversion or end of sequence conversions.
This parameter can be a value of @ref ADC_EOCSelection. */
- FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
- conversion (for ADC group regular) has been retrieved by user software,
+ FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the
+ previous conversion (for ADC group regular) has been retrieved by user software,
using function HAL_ADC_GetValue().
- This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
- for low frequency applications.
+ This feature automatically adapts the frequency of ADC conversions triggers to
+ the speed of the system that reads the data. Moreover, this avoids risk of
+ overrun for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
- Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
- Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
- Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
- use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
+ Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
+ HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC
+ flag (by CPU to free the IRQ pending event or by DMA).
+ Auto wait will work but fort a very short time, discarding its intended
+ benefit (except specific case of high load of CPU or DMA transfers which
+ can justify usage of auto wait).
+ Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
+ when ADC conversion data is needed:
+ use HAL_ADC_PollForConversion() to ensure that conversion is completed and
+ HAL_ADC_GetValue() to retrieve conversion result and trig another
+ conversion start. */
- FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
- This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
- This parameter can be set to ENABLE or DISABLE. */
+ FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a
+ conversion and automatically wakes-up when a new conversion is triggered
+ (with startup time between trigger and start of sampling).
+ This feature can be combined with automatic wait mode
+ (parameter 'LowPowerAutoWait').
+ This parameter can be set to ENABLE or DISABLE. */
- FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
- after the first ADC conversion start trigger occurred (software start or external trigger).
- This parameter can be set to ENABLE or DISABLE. */
+ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
+ or continuous mode for ADC group regular, after the first ADC conversion
+ start trigger occurred (software start or external trigger). This parameter
+ can be set to ENABLE or DISABLE. */
- uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
+ uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group
+ sequencer.
This parameter is dependent on ScanConvMode:
- sequencer configured to fully configurable:
Number of ranks in the scan sequence is configurable using this parameter.
- Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
- Afterwards, when all needed sequencer ranks are set, parameter 'NbrOfConversion' can be updated without modifying configuration of sequencer ranks
- (sequencer ranks above 'NbrOfConversion' are discarded).
+ Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to
+ parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
+ Afterwards, when all needed sequencer ranks are set, parameter
+ 'NbrOfConversion' can be updated without modifying configuration of
+ sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
- sequencer configured to not fully configurable:
- Number of ranks in the scan sequence is defined by number of channels set in the sequence. This parameter is discarded.
+ Number of ranks in the scan sequence is defined by number of channels set in
+ the sequence. This parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8.
- Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+ Note: This parameter must be modified when no conversion is on going on regular
+ group (ADC disabled, or ADC enabled without continuous mode or external
+ trigger that could launch a conversion). */
- FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
- (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE.
- Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
+ FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed
+ in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
+ successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter
+ 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled.
+ If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: On this STM32 series, ADC group regular number of discontinuous
+ ranks increment is fixed to one-by-one. */
- uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
- If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
+ uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion
+ start.
+ If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger
+ is used instead.
This parameter can be a value of @ref ADC_regular_external_trigger_source.
Caution: external trigger source is common to all ADC instances. */
- uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
+ uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
- FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
- or in continuous mode (DMA transfer unlimited, whatever number of conversions).
- This parameter can be set to ENABLE or DISABLE.
- Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
+ FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA
+ transfer stops when number of conversions is reached) or in continuous
+ mode (DMA transfer unlimited, whatever number of conversions).
+ This parameter can be set to ENABLE or DISABLE.
+ Note: In continuous mode, DMA must be configured in circular mode.
+ Otherwise an overrun will be triggered when DMA buffer maximum
+ pointer is reached. */
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
- Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
- end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
- HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
+ Note: In case of overrun set to data preserved and usage with programming model
+ with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
+ conversion flags, this induces the release of the preserved data. If
+ needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
+ placed in user program code (called before end of conversion flags clear)
Note: Error reporting with respect to the conversion mode:
- - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
- overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
+ - Usage with ADC conversion by polling for event or interruption: Error is
+ reported only if overrun is set to data preserved. If overrun is set to
+ data overwritten, user can willingly not read all the converted data,
+ this is not considered as an erroneous case.
+ - Usage with ADC conversion by DMA: Error is reported whatever overrun
+ setting (DMA is expected to process all data from data register). */
uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels.
Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
- Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
+ Conversion time is the addition of sampling time and processing time
+ (12.5 ADC clock cycles at ADC resolution 12 bits,
+ 10.5 cycles at 10 bits,
+ 8.5 cycles at 8 bits,
+ 6.5 cycles at 6 bits).
+ Note: On this STM32 family, two different sampling time settings are available,
+ each channel can use one of these two settings. On some other STM32 devices
+ this parameter in channel wise and is located into ADC channel
+ initialization structure.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor)
+ sampling time constraints must be respected (sampling time can be adjusted
+ in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint,
+ TS_vbat, TS_temp (values rough order: few tens of microseconds). */
uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible.
Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
- Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
+ Conversion time is the addition of sampling time and processing time
+ (12.5 ADC clock cycles at ADC resolution 12 bits,
+ 10.5 cycles at 10 bits,
+ 8.5 cycles at 8 bits,
+ 6.5 cycles at 6 bits).
+ Note: On this STM32 family, two different sampling time settings are available,
+ each channel can use one of these two settings. On some other STM32 devices
+ this parameter in channel wise and is located into ADC channel
+ initialization structure.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor)
+ sampling time constraints must be respected (sampling time can be adjusted
+ in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint,
+ TS_vbat, TS_temp (values rough order: few tens of microseconds). */
FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
- Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
+ Note: This parameter can be modified only if there is no conversion is
+ ongoing on ADC group regular. */
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
- Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
+ Caution: this setting overwrites the previous oversampling configuration
+ if oversampling is already enabled. */
uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode.
This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ.
@@ -224,16 +286,19 @@
* ADC state can be either:
* - For all parameters: ADC disabled or enabled without conversion on going on regular group.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
- * on the fly).
+ * without error reporting (as it can be the expected behavior in case of intended action to update another
+ * parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
- Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
+ Note: Depending on devices and ADC instances, some channels may not be available
+ on device package pins. Refer to device datasheet for channels
+ availability. */
- uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank.
+ uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its
+ conversion rank.
This parameter is dependent on ScanConvMode:
- sequencer configured to fully configurable:
Channels ordering into each rank of scan sequence:
@@ -241,18 +306,26 @@
- sequencer configured to not fully configurable:
rank of each channel is fixed by channel HW number.
(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
- Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
+ Despite the channel rank is fixed, this parameter allow an additional
+ possibility: to remove the selected rank (selected channel) from sequencer.
This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time
- (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ (12.5 ADC clock cycles at ADC resolution 12 bits,
+ 10.5 cycles at 10 bits,
+ 8.5 cycles at 8 bits,
+ 6.5 cycles at 6 bits).
This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON
- Note: On this STM32 family, two different sampling time settings are available (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), each channel can use one of these two settings.
+ Note: On this STM32 family, two different sampling time settings are available
+ (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"),
+ each channel can use one of these two settings.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/
+ TempSensor), sampling time constraints must be respected (sampling time
+ can be adjusted in function of ADC clock frequency and sampling time
+ setting)
Refer to device datasheet for timings values. */
} ADC_ChannelConfTypeDef;
@@ -261,48 +334,62 @@
* @brief Structure definition of ADC analog watchdog
* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
* ADC state can be either:
- * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular.
+ * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion
+ on going on ADC groups regular.
* - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular.
*/
typedef struct
{
uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
- For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
- For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+ For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels
+ by setting parameter 'WatchdogMode')
+ For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls
+ of 'HAL_ADC_AnalogWDGConfig()' for each channel)
This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
- For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular.
- For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure.
+ For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all
+ channels, ADC group regular.
+ For Analog Watchdog 2 and 3: Several channels can be monitored by applying
+ successively the AWD init structure.
This parameter can be a value of @ref ADC_analog_watchdog_mode. */
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
- For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
- For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
+ For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
+ is configured on single channel (only 1 channel can be
+ monitored).
+ For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
+ call successively the function HAL_ADC_AnalogWDGConfig()
+ for each channel to be added (or removed with value
+ 'ADC_ANALOGWATCHDOG_NONE').
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
- between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
- Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
- the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
- Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
+ number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
+ respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
+ resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
+ LSB are ignored. */
+ /*!< Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
impacted: the comparison of analog watchdog thresholds is done on
oversampling final computation (after ratio and shift application):
ADC data register bitfield [15:4] (12 most significant bits). */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
- between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
- Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
- the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
- Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
+ number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
+ respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
+ resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
+ LSB are ignored.*/
+ /*!< Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
impacted: the comparison of analog watchdog thresholds is done on
oversampling final computation (after ratio and shift application):
- ADC data register bitfield [15:4] (12 most significant bits). */
+ ADC data register bitfield [15:4] (12 most significant bits).*/
} ADC_AnalogWDGConfTypeDef;
/** @defgroup ADC_States ADC States
@@ -320,7 +407,7 @@
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */
+#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to internal process (ex : calibration) */
#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
/* States of ADC errors */
@@ -329,17 +416,25 @@
#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
- external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur
+ (either by continuous mode, external trigger, low power
+ auto power-on (if feature available), multimode ADC master
+ control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag
+ raised */
/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
- external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))*/
-#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow occurrence */
+#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group
+ injected is ongoing or can occur (either by auto-injection
+ mode, external trigger, low power auto power-on (if feature
+ available), multimode ADC master control (if feature
+ available))*/
+#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data
+ available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow
+ occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
@@ -347,7 +442,9 @@
#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave state, controlled by another ADC master (when feature available) */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave
+ state, controlled by another ADC master (when feature
+ available) */
/**
@@ -363,17 +460,20 @@
typedef struct
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
{
- ADC_TypeDef *Instance; /*!< Register base address */
- ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
- DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
- HAL_LockTypeDef Lock; /*!< ADC locking object */
- __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
- __IO uint32_t ErrorCode; /*!< ADC Error code */
+ ADC_TypeDef *Instance; /*!< Register base address */
+ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
- uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */
+ uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks
+ setting, used in mode "fully configurable" (refer to
+ parameter 'ScanConvMode') */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
- void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
+ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer
+ callback */
void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
@@ -437,22 +537,38 @@
/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
-#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */
-#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock
+ without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler
+ configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock
+ with prescaler division by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock
+ with prescaler division by 4 */
-#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
-#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
-#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
-#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
-#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
-#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
-#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
-#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
-#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
-#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
-#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
-#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
+#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without
+ prescaler */
+#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler
+ division by 2 */
+#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler
+ division by 4 */
+#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler
+ division by 6 */
+#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler
+ division by 8 */
+#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler
+ division by 10 */
+#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler
+ division by 12 */
+#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler
+ division by 16 */
+#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler
+ division by 32 */
+#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler
+ division by 64 */
+#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler
+ division by 128 */
+#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler
+ division by 256 */
/**
* @}
*/
@@ -471,8 +587,10 @@
/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
* @{
*/
-#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
+#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned
+ (alignment on data register LSB bit 0)*/
+#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned
+ (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -493,14 +611,23 @@
/* as default setting equivalent to scan enable. */
/* In case of migration from another STM32 device, the user will be */
/* warned of change of setting choices with assert check. */
-#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */
-#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */
+/* Sequencer set to fully configurable */
+#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable:
+ only the rank 1 is enabled (no scan sequence on several ranks) */
+#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable:
+ sequencer length and each rank affectation to a channel are configurable. */
-#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */
-#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */
+/* Sequencer set to not fully configurable */
+#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable:
+ sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0,
+ channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */
+#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT \
+ | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable:
+ sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0,
+ channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */
-#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */
-#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */
+#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 series */
+#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */
/**
* @}
*/
@@ -509,13 +636,27 @@
* @{
*/
/* ADC group regular trigger sources for all ADC instances */
-#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
-#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T2_CC4 (LL_ADC_REG_TRIG_EXT_TIM2_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< Software start. */
+/** ADC group regular conversion trigger from external peripheral */
+#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< TIM1 TRGO. Trigger edge set to
+ rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< TIM1 channel 4 event (capture
+ compare: input capture or output
+ capture). Trigger edge set to
+ rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< TIM2 TRGO. Trigger edge set to
+ rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_CC4 (LL_ADC_REG_TRIG_EXT_TIM2_CH4) /*!< TIM2 channel 4 event (capture
+ compare: input capture or output
+ capture). Trigger edge set to
+ rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< TIM2 channel 3 event (capture
+ compare: input capture or output
+ capture). Trigger edge set to
+ rising edge (default setting). */
+#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< External interrupt line 11. Trigger
+ edge set to rising edge (default
+ setting). */
/**
* @}
*/
@@ -523,10 +664,15 @@
/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
* @{
*/
-#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */
-#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger
+ detection disabled (SW start)*/
+#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular trigger
+ polarity set to rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular trigger
+ polarity set to falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular trigger
+ polarity set to both rising and
+ falling edges */
/**
* @}
*/
@@ -543,8 +689,13 @@
/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
* @{
*/
-#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
-#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+ * @brief ADC group regular behavior in case of overrun
+ */
+#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of
+ overrun: data preserved */
+#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of
+ overrun: data overwritten */
/**
* @}
*/
@@ -552,17 +703,24 @@
/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
-#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
-#define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */
+#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Enable the rank of the selected channels. Number of ranks in
+ the sequence is defined by number of channels enabled, rank
+ of each channel is defined by channel number (channel 0 fixed
+ on rank 0, channel 1 fixed on rank1, ...).
+ Setting relevant if parameter "ScanConvMode" is set to
+ sequencer not fully configurable. */
+#define ADC_RANK_NONE (0x00000002U) /*!< Disable the selected rank (selected channel) from sequencer.
+ Setting relevant if parameter "ScanConvMode" is set to
+ sequencer not fully configurable. */
-#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
-#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
-#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
-#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
-#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
-#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
-#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
-#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
+#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
/**
* @}
*/
@@ -570,8 +728,10 @@
/** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
* @{
*/
-#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
-#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
+#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of
+ channels: sampling time nb 1 */
+#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of
+ channels: sampling time nb 2 */
/**
* @}
*/
@@ -579,14 +739,14 @@
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
-#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */
-#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */
-#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */
-#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
-#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */
-#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */
-#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */
-#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */
+#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */
+#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
+#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */
+#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */
+#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */
+#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */
/**
* @}
*/
@@ -594,28 +754,30 @@
/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
* @{
*/
-#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
-#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
-#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
-#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
-#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
-#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
-#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
-#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
-#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
-#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
-#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
-#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
-#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
-#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
-#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
-#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
-#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
-#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
-#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
-#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */
-#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
-#define ADC_CHANNEL_DACCH1 (LL_ADC_CHANNEL_DACCH1) /*!< ADC internal channel connected to DAC channel 1. */
+#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */
+#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */
+#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */
+#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */
+#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */
+#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */
+#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */
+#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */
+#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */
+#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */
+#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */
+#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */
+#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */
+#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */
+#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */
+#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */
+#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */
+#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */
+#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel Internal voltage reference*/
+#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor */
+#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3:
+ Vbat voltage through a divider ladder of
+ factor 1/3 to have Vbat always below Vdda. */
+#define ADC_CHANNEL_DACCH1 (LL_ADC_CHANNEL_DACCH1) /*!< Internal channel DAC channel 1. */
/**
* @}
*/
@@ -633,9 +795,11 @@
/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
* @{
*/
-#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
-#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
-#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
+#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a
+ regular group, single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to
+ regular group, all channels */
/**
* @}
*/
@@ -643,14 +807,18 @@
/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
* @{
*/
-#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+/**
+ * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed
+ * to result as the ADC oversampling conversion data (before potential shift)
+ */
+#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */
+#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */
+#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */
+#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */
+#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */
+#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */
+#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */
+#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */
/**
* @}
*/
@@ -658,15 +826,19 @@
/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
* @{
*/
-#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+/**
+ * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling
+ * conversion data)
+ */
+#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */
+#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */
+#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */
+#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */
+#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */
+#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */
+#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */
+#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */
+#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */
/**
* @}
*/
@@ -674,8 +846,12 @@
/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
*/
-#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
-#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode:
+ continuous mode (all conversions of
+ OVS ratio are done from 1 trigger) */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode:
+ discontinuous mode (each conversion of
+ OVS ratio needs a trigger) */
/**
* @}
*/
@@ -683,8 +859,15 @@
/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
* @{
*/
-#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
-#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+
+/**
+ * @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion
+ * start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion
+ * start trigger event).
+ * Duration value: Refer to device datasheet, parameter "tIdle".
+ */
+#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< Trigger frequency mode set to high frequency. */
+#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< Trigger frequency mode set to low frequency. */
/**
* @}
*/
@@ -692,28 +875,33 @@
/** @defgroup ADC_Event_type ADC Event type
* @{
*/
+/**
+ * @note Analog watchdog 1 is available on all stm32 series
+ * Analog watchdog 2 and 3 are not available on all series
+ */
#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
-#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
-#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
-#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */
+#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
+#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
/**
* @}
*/
-#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
+#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility
+ with other STM32 devices having only one analog watchdog */
/** @defgroup ADC_interrupts_definition ADC interrupts definition
* @{
*/
#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
#define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */
-#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
-#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
-#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
-#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
-#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
-#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
-#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
+#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< End of sampling interrupt source */
+#define ADC_IT_EOC ADC_IER_EOCIE /*!< End of regular conversion interrupt source */
+#define ADC_IT_EOS ADC_IER_EOSIE /*!< End of regular sequence of conversions interrupt source */
+#define ADC_IT_OVR ADC_IER_OVRIE /*!< overrun interrupt source */
+#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< Analog watchdog 1 interrupt source (main analog watchdog) */
+#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< Analog watchdog 2 interrupt source (additional analog watchdog) */
+#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< Analog watchdog 3 interrupt source (additional analog watchdog) */
/**
* @}
*/
@@ -1004,7 +1192,8 @@
/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
-#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */
+/* Internal definition to differentiate sequencer setting fixed or configurable */
+#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U
/**
* @}
@@ -1264,7 +1453,8 @@
* (1) On STM32WL, parameter can be set in ADC group sequencer
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
- * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
+ * (channel connected to a GPIO pin).
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/
#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
@@ -1564,11 +1754,14 @@
* @note ADC measurement data must correspond to a resolution of 12bits
* (full scale digital value 4095). If not the case, the data must be
* preliminarily rescaled to an equivalent resolution of 12 bits.
- * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
+ (unit: uV/DegCelsius).
* On STM32WL, refer to device datasheet parameter "Avg_Slope".
- * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
- * On STM32WL, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
- * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at
+ temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32WL, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see
+ parameter above) is corresponding (unit: mV)
* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
diff --git a/Inc/stm32wlxx_hal_comp.h b/Inc/stm32wlxx_hal_comp.h
index 1209343..b121537 100644
--- a/Inc/stm32wlxx_hal_comp.h
+++ b/Inc/stm32wlxx_hal_comp.h
@@ -691,7 +691,7 @@
* @{
*/
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
+uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp);
/* Callback in interrupt mode */
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
/**
@@ -702,8 +702,8 @@
/** @addtogroup COMP_Exported_Functions_Group4
* @{
*/
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
-uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
+HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp);
+uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp);
/**
* @}
*/
diff --git a/Inc/stm32wlxx_hal_cortex.h b/Inc/stm32wlxx_hal_cortex.h
index f45b063..2a0ef1b 100644
--- a/Inc/stm32wlxx_hal_cortex.h
+++ b/Inc/stm32wlxx_hal_cortex.h
@@ -178,7 +178,7 @@
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
-#define MPU_TEX_LEVEL4 ((uint8_t)0x04)
+
/**
* @}
*/
@@ -362,8 +362,7 @@
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \
- ((TYPE) == MPU_TEX_LEVEL2) || \
- ((TYPE) == MPU_TEX_LEVEL4))
+ ((TYPE) == MPU_TEX_LEVEL2))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \
diff --git a/Inc/stm32wlxx_hal_cryp.h b/Inc/stm32wlxx_hal_cryp.h
index d16c6e4..b1ee036 100644
--- a/Inc/stm32wlxx_hal_cryp.h
+++ b/Inc/stm32wlxx_hal_cryp.h
@@ -196,6 +196,29 @@
} CRYP_HandleTypeDef;
+/**
+ * @brief CRYP Context Structure definition
+ */
+
+typedef struct
+{
+ uint32_t DataType; /*!< This parameter can be a value of @ref CRYP_Data_Type */
+ uint32_t KeySize; /*!< This parameter can be a value of @ref CRYP_Key_Size */
+ uint32_t *pKey; /*!< The key used for encryption/decryption */
+ uint32_t *pInitVect; /*!< The initialization vector, counter with CBC and CTR Algorithm */
+ uint32_t Algorithm; /*!< This parameter can be a value of @ref CRYP_Algorithm_Mode */
+ uint32_t DataWidthUnit; /*!< This parameter can be value of @ref CRYP_Data_Width_Unit */
+ uint32_t KeyIVConfigSkip; /*!< This parameter can be a value of @ref CRYP_Configuration_Skip */
+ uint32_t Phase; /*!< CRYP peripheral phase */
+ uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag */
+ uint32_t CR_Reg; /*!< CRYP CR register */
+ uint32_t IVR0_Reg; /*!< CRYP IVR0 register */
+ uint32_t IVR1_Reg; /*!< CRYP IVR1 register */
+ uint32_t IVR2_Reg; /*!< CRYP IVR2 register */
+ uint32_t IVR3_Reg; /*!< CRYP IVR3 register */
+
+} CRYP_ContextTypeDef;
+
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
* @brief HAL CRYP Callback ID enumeration definition
@@ -351,6 +374,7 @@
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
+#define CRYP_IVCONFIG_ONCE 0x00000004U /*!< Peripheral IV configuration do once for interleave mode */
/**
* @}
@@ -511,6 +535,9 @@
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
+HAL_StatusTypeDef HAL_CRYP_SaveContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont);
+HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont);
+
/**
* @}
*/
@@ -576,7 +603,8 @@
((DATATYPE) == CRYP_DATATYPE_1B))
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
- ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
+ ((CONFIG) == CRYP_KEYIVCONFIG_ONCE) || \
+ ((CONFIG) == CRYP_IVCONFIG_ONCE))
#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
(((((ALGO) == CRYP_AES_CTR)) && \
diff --git a/Inc/stm32wlxx_hal_dac.h b/Inc/stm32wlxx_hal_dac.h
index 921f1e4..908ef5e 100644
--- a/Inc/stm32wlxx_hal_dac.h
+++ b/Inc/stm32wlxx_hal_dac.h
@@ -63,7 +63,7 @@
typedef struct __DAC_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
{
DAC_TypeDef *Instance; /*!< Register base address */
@@ -78,13 +78,13 @@
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
- void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
+ void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef;
@@ -121,7 +121,7 @@
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
- uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
+ uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
@@ -131,9 +131,7 @@
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
-
} DAC_ChannelConfTypeDef;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -277,6 +275,20 @@
* @}
*/
+/* Delay for DAC channel voltage settling time from DAC channel startup */
+/* (transition from disable to enable). */
+/* Note: DAC channel startup time depends on board application environment: */
+/* impedance connected to DAC channel output. */
+/* The delay below is specified under conditions: */
+/* - voltage maximum transition (lowest to highest value) */
+/* - until voltage reaches final value +-1LSB */
+/* - DAC channel output buffer enabled */
+/* - load impedance of 5kOhm (min), 50pF (max) */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tWAKEUP"). */
+/* Unit: us */
+#define DAC_DELAY_STARTUP_US (8UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Macros DAC Exported Macros
@@ -351,7 +363,8 @@
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @retval State of interruption (SET or RESET)
*/
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__ specifies the DAC handle.
@@ -425,12 +438,10 @@
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
-
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
-
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
@@ -453,9 +464,9 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
-
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
+ const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
*/
@@ -464,8 +475,8 @@
* @{
*/
/* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
+uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
/**
* @}
@@ -500,5 +511,4 @@
#endif
-#endif /*STM32WLxx_HAL_DAC_H */
-
+#endif /* STM32WLxx_HAL_DAC_H */
diff --git a/Inc/stm32wlxx_hal_dac_ex.h b/Inc/stm32wlxx_hal_dac_ex.h
index 5b51c82..ea7d549 100644
--- a/Inc/stm32wlxx_hal_dac_ex.h
+++ b/Inc/stm32wlxx_hal_dac_ex.h
@@ -81,6 +81,7 @@
* @}
*/
+
/**
* @}
*/
@@ -175,7 +176,7 @@
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue);
-uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
+uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
/**
* @}
@@ -199,4 +200,4 @@
}
#endif
-#endif /*STM32WLxx_HAL_DAC_EX_H */
+#endif /* STM32WLxx_HAL_DAC_EX_H */
diff --git a/Inc/stm32wlxx_hal_exti.h b/Inc/stm32wlxx_hal_exti.h
index c45f37d..20cbd8d 100644
--- a/Inc/stm32wlxx_hal_exti.h
+++ b/Inc/stm32wlxx_hal_exti.h
@@ -126,7 +126,7 @@
#else
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_RESERVED | EXTI_REG2 | 0x05u)
-#endif
+#endif /* DUAL_CORE */
#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06u)
#if defined (DUAL_CORE)
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07u)
@@ -136,7 +136,7 @@
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#define EXTI_LINE_41 (EXTI_RESERVED | EXTI_REG2 | 0x09u)
-#endif
+#endif /* DUAL_CORE */
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu)
@@ -246,14 +246,14 @@
* @{
*/
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
- ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
- (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
- (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
- (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
- (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
+ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
+ (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
- (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
diff --git a/Inc/stm32wlxx_hal_i2c.h b/Inc/stm32wlxx_hal_i2c.h
index eae2190..5037fbf 100644
--- a/Inc/stm32wlxx_hal_i2c.h
+++ b/Inc/stm32wlxx_hal_i2c.h
@@ -217,6 +217,10 @@
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
+ __IO uint32_t Devaddress; /*!< I2C Target device address */
+
+ __IO uint32_t Memaddress; /*!< I2C Target memory address */
+
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
diff --git a/Inc/stm32wlxx_hal_irda.h b/Inc/stm32wlxx_hal_irda.h
index 0c7d54c..a531b8c 100644
--- a/Inc/stm32wlxx_hal_irda.h
+++ b/Inc/stm32wlxx_hal_irda.h
@@ -853,8 +853,8 @@
*/
/* Peripheral State and Error functions ***************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
/**
* @}
diff --git a/Inc/stm32wlxx_hal_lptim.h b/Inc/stm32wlxx_hal_lptim.h
index 35990a7..0bc2b78 100644
--- a/Inc/stm32wlxx_hal_lptim.h
+++ b/Inc/stm32wlxx_hal_lptim.h
@@ -394,7 +394,7 @@
* @retval None
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
@@ -691,9 +691,9 @@
* @{
*/
/* Reading operation functions ************************************************/
-uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
-uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
-uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
@@ -824,11 +824,13 @@
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\
+ ((__AUTORELOAD__) <= 0x0000FFFFUL))
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
-#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
+#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\
+ ((__PERIOD__) <= 0x0000FFFFUL))
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
diff --git a/Inc/stm32wlxx_hal_rcc.h b/Inc/stm32wlxx_hal_rcc.h
index e27614d..64d9836 100644
--- a/Inc/stm32wlxx_hal_rcc.h
+++ b/Inc/stm32wlxx_hal_rcc.h
@@ -51,7 +51,8 @@
#define RCC_FLAG_MASK 0x1FU
/* Defines Oscillator Masks */
-#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */
+#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
+ RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */
/** @defgroup RCC_Timeout_Value Timeout Values
* @{
@@ -117,8 +118,7 @@
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
((__PLL__) == RCC_PLL_ON))
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
- ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_MSI) || \
((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
((__SOURCE__) == RCC_PLLSOURCE_HSE))
@@ -234,7 +234,7 @@
This parameter must be a value of @ref RCC_PLLM_Clock_Divider */
uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
- This parameter must be a number between Min_Data = 6 and Max_Data = 127 */
+ This parameter must be a number between Min_Data = 6 and Max_Data = 127 */
uint32_t PLLP; /*!< PLLP: Division factor for ADC clock.
This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
@@ -649,7 +649,8 @@
#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */
/* @endcond */
-#define RCC_MCO1_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)
+#define RCC_MCO1_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \
+ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)
#define RCC_MCO1 RCC_MCO1_PA8
#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO */
@@ -660,16 +661,16 @@
/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
* @{
*/
-#define RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK /*!< MCO1 output disabled, no clock on MCO1 */
-#define RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK /*!< SYSCLK selected as MCO1 source */
-#define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI /*!< MSI selected as MCO1 source */
-#define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI /*!< HSI selected as MCO1 source */
-#define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE /*!< HSE after stabilization selected as MCO1 source */
-#define RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK /*!< Main PLLRCLK selected as MCO1 source */
-#define RCC_MCO1SOURCE_LSI LL_RCC_MCO1SOURCE_LSI /*!< LSI selected as MCO1 source */
-#define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selected as MCO1 source */
-#define RCC_MCO1SOURCE_PLLPCLK LL_RCC_MCO1SOURCE_PLLPCLK /*!< Main PLLPCLK selected as MCO1 source */
-#define RCC_MCO1SOURCE_PLLQCLK LL_RCC_MCO1SOURCE_PLLQCLK /*!< Main PLLQCLK selected as MCO1 source */
+#define RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK /*!< MCO1 output disabled, no clock on MCO1 */
+#define RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK /*!< SYSCLK selected as MCO1 source */
+#define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI /*!< MSI selected as MCO1 source */
+#define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI /*!< HSI selected as MCO1 source */
+#define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE /*!< HSE after stabilization selected as MCO1 source */
+#define RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK /*!< Main PLLRCLK selected as MCO1 source */
+#define RCC_MCO1SOURCE_LSI LL_RCC_MCO1SOURCE_LSI /*!< LSI selected as MCO1 source */
+#define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selected as MCO1 source */
+#define RCC_MCO1SOURCE_PLLPCLK LL_RCC_MCO1SOURCE_PLLPCLK /*!< Main PLLPCLK selected as MCO1 source */
+#define RCC_MCO1SOURCE_PLLQCLK LL_RCC_MCO1SOURCE_PLLQCLK /*!< Main PLLQCLK selected as MCO1 source */
/**
* @}
*/
@@ -677,7 +678,7 @@
/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
* @{
*/
-#define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1 /*!< MCO not divided */
+#define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1 /*!< MCO not divided */
#define RCC_MCODIV_2 LL_RCC_MCO1_DIV_2 /*!< MCO divided by 2 */
#define RCC_MCODIV_4 LL_RCC_MCO1_DIV_4 /*!< MCO divided by 4 */
#define RCC_MCODIV_8 LL_RCC_MCO1_DIV_8 /*!< MCO divided by 8 */
@@ -2225,7 +2226,7 @@
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
diff --git a/Inc/stm32wlxx_hal_rcc_ex.h b/Inc/stm32wlxx_hal_rcc_ex.h
index c0ac139..b02b788 100644
--- a/Inc/stm32wlxx_hal_rcc_ex.h
+++ b/Inc/stm32wlxx_hal_rcc_ex.h
@@ -346,7 +346,7 @@
/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
* @{
*/
-#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */
+#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */
/**
* @}
*/
@@ -354,7 +354,7 @@
/** @defgroup RCCEx_EXTI_LINE_HSECSS RCC HSE CSS external interrupt line
* @{
*/
-#define RCC_EXTI_LINE_HSECSS EXTI_IMR2_IM43 /*!< External interrupt line 43 connected to the HSE CSS EXTI Line */
+#define RCC_EXTI_LINE_HSECSS EXTI_IMR2_IM43 /*!< External interrupt line 43 connected to the HSE CSS EXTI Line */
/**
* @}
*/
diff --git a/Inc/stm32wlxx_hal_rtc.h b/Inc/stm32wlxx_hal_rtc.h
index 9bb4a86..2c3db28 100644
--- a/Inc/stm32wlxx_hal_rtc.h
+++ b/Inc/stm32wlxx_hal_rtc.h
@@ -710,6 +710,13 @@
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) : \
(RTC->SCR = (RTC_CLEAR_ALRBF)))
+/**
+ * @brief Check whether if the RTC Calendar is initialized.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)
+
#if defined(CORE_CM0PLUS)
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
diff --git a/Inc/stm32wlxx_hal_smartcard.h b/Inc/stm32wlxx_hal_smartcard.h
index 40bfac9..4a1abab 100644
--- a/Inc/stm32wlxx_hal_smartcard.h
+++ b/Inc/stm32wlxx_hal_smartcard.h
@@ -1126,8 +1126,8 @@
* @{
*/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
diff --git a/Inc/stm32wlxx_hal_subghz.h b/Inc/stm32wlxx_hal_subghz.h
index 1cfa34e..895a443 100644
--- a/Inc/stm32wlxx_hal_subghz.h
+++ b/Inc/stm32wlxx_hal_subghz.h
@@ -61,6 +61,7 @@
HAL_SUBGHZ_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
HAL_SUBGHZ_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_SUBGHZ_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_SUBGHZ_STATE_RESET_RF_READY = 0x03U, /*!< Peripheral not Initialized but RF is */
} HAL_SUBGHZ_StateTypeDef;
/**
@@ -103,6 +104,7 @@
void (* RxTxTimeoutCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Rx Tx Timeout callback */
void (* MspInitCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Msp Init callback */
void (* MspDeInitCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Msp DeInit callback */
+ void (* LrFhssHopCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ LR FHSS Hop callback */
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
} SUBGHZ_HandleTypeDef;
@@ -121,8 +123,8 @@
HAL_SUBGHZ_CRC_ERROR_CB_ID = 0x06U, /*!< SUBGHZ CRC error callback ID */
HAL_SUBGHZ_RX_TX_TIMEOUT_CB_ID = 0x07U, /*!< SUBGHZ Rx Tx timeout callback ID */
HAL_SUBGHZ_MSPINIT_CB_ID = 0x08U, /*!< SUBGHZ Msp Init callback ID */
- HAL_SUBGHZ_MSPDEINIT_CB_ID = 0x09U /*!< SUBGHZ Msp DeInit callback ID */
-
+ HAL_SUBGHZ_MSPDEINIT_CB_ID = 0x09U, /*!< SUBGHZ Msp DeInit callback ID */
+ HAL_SUBGHZ_LR_FHSS_HOP_CB_ID = 0x0AU, /*!< SUBGHZ LR FHSS Hop callback ID */
} HAL_SUBGHZ_CallbackIDTypeDef;
/**
@@ -243,7 +245,7 @@
#define SUBGHZ_IT_CAD_DONE 0x0080U
#define SUBGHZ_IT_CAD_ACTIVITY_DETECTED 0x0100U
#define SUBGHZ_IT_RX_TX_TIMEOUT 0x0200U
-
+#define SUBGHZ_IT_LR_FHSS_HOP 0x4000U
/**
* @brief SUBGHZ Radio Read/Write Command definition
*/
@@ -266,13 +268,22 @@
* @retval None
*/
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
-#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0U)
+#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+
+#define __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET_RF_READY; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
#else
-#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET)
+#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET)
+#define __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY(__HANDLE__) ((__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET_RF_READY)
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
/**
* @}
@@ -297,6 +308,7 @@
* @arg SUBGHZ_IT_CAD_DONE
* @arg SUBGHZ_IT_CAD_ACTIVITY_DETECTED
* @arg SUBGHZ_IT_RX_TX_TIMEOUT
+ * @arg SUBGHZ_IT_LR_FHSS_HOP
* @retval SET or RESET.
*/
#define SUBGHZ_CHECK_IT_SOURCE(__SUBGHZ_IRQ__, __INTERRUPT__) \
@@ -378,6 +390,7 @@
void HAL_SUBGHZ_CRCErrorCallback(SUBGHZ_HandleTypeDef *hsubghz);
void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus);
void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz);
+void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz);
/**
* @}
*/
diff --git a/Inc/stm32wlxx_hal_tim.h b/Inc/stm32wlxx_hal_tim.h
index cbfb59a..406da13 100644
--- a/Inc/stm32wlxx_hal_tim.h
+++ b/Inc/stm32wlxx_hal_tim.h
@@ -790,16 +790,16 @@
/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
-#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
-#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
-#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
-#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
-#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
/**
* @}
*/
@@ -1802,7 +1802,7 @@
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
- ((__MODE__) == TIM_UIFREMAP_ENALE))
+ ((__MODE__) == TIM_UIFREMAP_ENABLE))
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
@@ -1862,20 +1862,23 @@
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
+ ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
+
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
((__CHANNEL__) == TIM_CHANNEL_3))
#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
@@ -1992,13 +1995,13 @@
((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF))
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
@@ -2163,7 +2166,7 @@
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
@@ -2185,7 +2188,8 @@
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+ uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@@ -2207,7 +2211,8 @@
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+ uint16_t Length);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@@ -2292,21 +2297,25 @@
* @{
*/
/* Control functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
+ uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+ const TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
@@ -2316,7 +2325,7 @@
uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
@@ -2353,17 +2362,17 @@
* @{
*/
/* Peripheral State functions ************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
/* Peripheral Channel state functions ************************************************/
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
/**
* @}
*/
@@ -2377,9 +2386,9 @@
/** @defgroup TIM_Private_Functions TIM Private Functions
* @{
*/
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
diff --git a/Inc/stm32wlxx_hal_tim_ex.h b/Inc/stm32wlxx_hal_tim_ex.h
index 06d370d..a1b4a0b 100644
--- a/Inc/stm32wlxx_hal_tim_ex.h
+++ b/Inc/stm32wlxx_hal_tim_ex.h
@@ -85,35 +85,35 @@
/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
-#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is not connected to I/O */
-#define TIM_TIM1_ETR_ADC_AWD1 TIM1_OR1_ETR_ADC_RMP_0 /* !< TIM1_ETR is connected to ADC AWD1 */
-#define TIM_TIM1_ETR_ADC_AWD2 TIM1_OR1_ETR_ADC_RMP_1 /* !< TIM1_ETR is connected to ADC AWD2 */
-#define TIM_TIM1_ETR_ADC_AWD3 (TIM1_OR1_ETR_ADC_RMP_0 | TIM1_OR1_ETR_ADC_RMP_1) /* !< TIM1_ETR is connected to ADC AWD3 */
-#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
-#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
+#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< TIM1_ETR is not connected to I/O */
+#define TIM_TIM1_ETR_ADC_AWD1 TIM1_OR1_ETR_ADC_RMP_0 /*!< TIM1_ETR is connected to ADC AWD1 */
+#define TIM_TIM1_ETR_ADC_AWD2 TIM1_OR1_ETR_ADC_RMP_1 /*!< TIM1_ETR is connected to ADC AWD2 */
+#define TIM_TIM1_ETR_ADC_AWD3 (TIM1_OR1_ETR_ADC_RMP_0 | TIM1_OR1_ETR_ADC_RMP_1) /*!< TIM1_ETR is connected to ADC AWD3 */
+#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */
+#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */
-#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 Input capture 1 is connected to I/0 */
-#define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 Input capture 1is connected to COMP1 OUT */
+#define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1 Input capture 1 is connected to I/0 */
+#define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /*!< TIM1 Input capture 1is connected to COMP1 OUT */
-#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2 External trigger ETR is connected to I/O */
-#define TIM_TIM2_ETR_LSE TIM2_OR1_ETR_RMP /* !< TIM2 External trigger ETR is connected to LSE */
-#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
-#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
+#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< TIM2 External trigger ETR is connected to I/O */
+#define TIM_TIM2_ETR_LSE TIM2_OR1_ETR_RMP /*!< TIM2 External trigger ETR is connected to LSE */
+#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */
+#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */
-#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to I/O */
-#define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2_TI4 is connected to COMP1 OUT */
-#define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2_TI4 is connected to COMP1 OUT */
-#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_TI4_RMP_1) /* !< TIM2_TI4 is connected to COMP1 and COMP2 OUT */
+#define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2_TI4 is connected to I/O */
+#define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /*!< TIM2_TI4 is connected to COMP1 OUT */
+#define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /*!< TIM2_TI4 is connected to COMP1 OUT */
+#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_TI4_RMP_1) /*!< TIM2_TI4 is connected to COMP1 and COMP2 OUT */
-#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to I/O */
-#define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16_TI1 is connected to LSI Clock */
-#define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16_TI1 is connected to LSE Clock */
-#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_TI1_RMP_1) /* !< TIM16_TI1 is connected to RTC */
+#define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16_TI1 is connected to I/O */
+#define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /*!< TIM16_TI1 is connected to LSI Clock */
+#define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /*!< TIM16_TI1 is connected to LSE Clock */
+#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_TI1_RMP_1) /*!< TIM16_TI1 is connected to RTC */
-#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to I/O */
-#define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17_TI1 is connected to MSI */
-#define TIM_TIM17_TI1_HSE TIM17_OR1_TI1_RMP_1 /* !< TIM17_TI1 is connected to HSE/32 */
-#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_TI1_RMP_1) /* !< TIM17_TI1 is connected to MCO */
+#define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17_TI1 is connected to I/O */
+#define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /*!< TIM17_TI1 is connected to MSI */
+#define TIM_TIM17_TI1_HSE TIM17_OR1_TI1_RMP_1 /*!< TIM17_TI1 is connected to HSE/32 */
+#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_TI1_RMP_1) /*!< TIM17_TI1 is connected to MCO */
/**
* @}
*/
@@ -130,9 +130,9 @@
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
* @{
*/
-#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
-#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */
+#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */
/**
* @}
*/
@@ -212,7 +212,7 @@
* @{
*/
/* Timer Hall Sensor functions **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
@@ -245,7 +245,8 @@
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+ uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@@ -264,7 +265,8 @@
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+ uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@@ -298,11 +300,11 @@
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig);
+ const TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+ const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
- TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+ const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
@@ -330,8 +332,8 @@
* @{
*/
/* Extended Peripheral State functions ***************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/
diff --git a/Inc/stm32wlxx_hal_uart.h b/Inc/stm32wlxx_hal_uart.h
index 8e04dbb..912f6ff 100644
--- a/Inc/stm32wlxx_hal_uart.h
+++ b/Inc/stm32wlxx_hal_uart.h
@@ -194,7 +194,7 @@
/**
* @brief HAL UART Reception type definition
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
- * It is expected to admit following values :
+ * This parameter can be a value of @ref UART_Reception_Type_Values :
* HAL_UART_RECEPTION_STANDARD = 0x00U,
* HAL_UART_RECEPTION_TOIDLE = 0x01U,
* HAL_UART_RECEPTION_TORTO = 0x02U,
@@ -203,6 +203,17 @@
typedef uint32_t HAL_UART_RxTypeTypeDef;
/**
+ * @brief HAL UART Rx Event type definition
+ * @note HAL UART Rx Event type value aims to identify which type of Event has occurred
+ * leading to call of the RxEvent callback.
+ * This parameter can be a value of @ref UART_RxEvent_Type_Values :
+ * HAL_UART_RXEVENT_TC = 0x00U,
+ * HAL_UART_RXEVENT_HT = 0x01U,
+ * HAL_UART_RXEVENT_IDLE = 0x02U,
+ */
+typedef uint32_t HAL_UART_RxEventTypeTypeDef;
+
+/**
* @brief UART handle Structure definition
*/
typedef struct __UART_HandleTypeDef
@@ -236,6 +247,8 @@
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
+ __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */
+
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
@@ -804,7 +817,7 @@
* @}
*/
-/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
+/** @defgroup UART_Reception_Type_Values UART Reception type values
* @{
*/
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
@@ -815,6 +828,16 @@
* @}
*/
+/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values
+ * @{
+ */
+#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */
+#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */
+#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -1671,8 +1694,8 @@
*/
/* Peripheral State and Errors functions **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart);
/**
* @}
diff --git a/Inc/stm32wlxx_hal_uart_ex.h b/Inc/stm32wlxx_hal_uart_ex.h
index 6819fff..c45cdef 100644
--- a/Inc/stm32wlxx_hal_uart_ex.h
+++ b/Inc/stm32wlxx_hal_uart_ex.h
@@ -177,6 +177,8 @@
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
+
/**
* @}
diff --git a/Inc/stm32wlxx_hal_usart.h b/Inc/stm32wlxx_hal_usart.h
index 258bfcb..1902c11 100644
--- a/Inc/stm32wlxx_hal_usart.h
+++ b/Inc/stm32wlxx_hal_usart.h
@@ -940,8 +940,8 @@
*/
/* Peripheral State and Error functions ***************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart);
/**
* @}
diff --git a/Inc/stm32wlxx_hal_wwdg.h b/Inc/stm32wlxx_hal_wwdg.h
index 4d13c36..a170189 100644
--- a/Inc/stm32wlxx_hal_wwdg.h
+++ b/Inc/stm32wlxx_hal_wwdg.h
@@ -192,7 +192,7 @@
/**
* @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__: WWDG handle
+ * @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
diff --git a/Inc/stm32wlxx_ll_adc.h b/Inc/stm32wlxx_ll_adc.h
index 78cc1ea..65788a6 100644
--- a/Inc/stm32wlxx_ll_adc.h
+++ b/Inc/stm32wlxx_ll_adc.h
@@ -68,7 +68,9 @@
/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
/* - regular trigger source */
/* - regular trigger edge */
-#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for
+ compatibility with some ADC on other STM32 families
+ having this setting set by HW default value) */
/* Mask containing trigger source masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
@@ -100,12 +102,17 @@
/* GPIO pins) and internal channels (connected to internal paths) */
#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
-#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
-#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
+#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to
+ ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
+ if set to mode "fully configurable", can contain channels with a restricted channel number.
+ Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
+ position in register */
#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
ADC_CHANNEL_ID_INTERNAL_CH_MASK)
/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
-#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
+ >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
/* Channel differentiation between external and internal channels */
#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
@@ -193,17 +200,22 @@
#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
-#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
+#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
+ in ADC_AWD_CRX_REGOFFSET_MASK */
/* Internal register offset for ADC analog watchdog threshold configuration */
#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
-#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
-#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
-#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
-#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
+#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
+ in ADC_AWD_TRX_REGOFFSET_MASK */
+#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
+ threshold high: mask of bit */
+#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
+ threshold high: position of bit */
+#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
+ position to perform a shift of 4 ranks */
#define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
@@ -237,19 +249,31 @@
/* ADC registers bits groups */
-#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
+#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
+ | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
+ HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
/* ADC internal channels related definitions */
/* Internal voltage reference VrefInt */
-#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) voltage with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference,
+ address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC),
+ Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value
+ with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/* Temperature sensor */
-#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32WL, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75C8UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32WL, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32WL,
+ temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V
+ (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75C8UL)) /* Address of parameter TS_CAL2: On STM32WL,
+ temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V
+ (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor
+ has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Temperature at which temperature sensor
+ has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) value
+ with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/**
* @}
@@ -297,8 +321,8 @@
{
uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetCommonClock(). */
} LL_ADC_CommonInitTypeDef;
@@ -324,27 +348,29 @@
{
uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
- @note On this STM32 series, this parameter has some clock ratio constraints:
- ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
- (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
+ @note On this STM32 series, this parameter has some clock ratio constraints:
+ ADC clock synchronous (from PCLK) with prescaler 1 must be enabled
+ only if PCLK has a 50% duty clock cycle (APB prescaler configured
+ inside the RCC must be bypassed and the system clock must by 50% duty
+ cycle).
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetClock().
For more details, refer to description of this function. */
uint32_t Resolution; /*!< Set ADC resolution.
This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetResolution(). */
uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetDataAlignment(). */
uint32_t LowPowerMode; /*!< Set ADC low power mode.
This parameter can be a value of @ref ADC_LL_EC_LP_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetLowPowerMode(). */
} LL_ADC_InitTypeDef;
@@ -369,43 +395,57 @@
*/
typedef struct
{
- uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
+ uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
+ from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
- (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
- In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+ @note On this STM32 series, setting trigger source to external trigger also
+ set trigger polarity to rising edge(default setting for compatibility
+ with some ADC on other STM32 families having this setting set by HW
+ default value).
+ In case of need to modify trigger edge, use function
+ @ref LL_ADC_REG_SetTriggerEdge().
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetTriggerSource(). */
uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
- @note This parameter has an effect only if group regular sequencer is set to mode "fully configurable". Refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+ @note This parameter has an effect only if group regular sequencer is set
+ to mode "fully configurable". Refer to function
+ @ref LL_ADC_REG_SetSequencerConfigurable().
This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetSequencerLength(). */
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
-
- uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
+ and scan conversions interrupted every selected number of ranks.
This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
- @note This parameter has an effect only if group regular sequencer is enabled
- (depending on the sequencer mode: scan length of 2 ranks or more, or several ADC channels enabled in group regular sequencer. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
+ @note This parameter has an effect only if group regular sequencer is
+ enabled (depending on the sequencer mode: scan length of 2 ranks or
+ more, or several ADC channels enabled in group regular sequencer.
+ Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetSequencerDiscont(). */
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
-
- uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
+ conversions are performed in single mode (one conversion per trigger) or in
+ continuous mode (after the first trigger, following conversions launched
+ successively automatically).
This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
- Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+ Note: It is not possible to enable both ADC group regular continuous mode
+ and discontinuous mode.
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetContinuousMode(). */
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
-
- uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
+ by DMA, and DMA requests mode.
This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetDMATransfer(). */
uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
data preserved or overwritten.
This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetOverrun(). */
} LL_ADC_REG_InitTypeDef;
@@ -461,7 +501,12 @@
/* List of ADC registers intended to be used (most commonly) with */
/* DMA transfer. */
/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
-#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
+ (corresponding to register DR) to be used with ADC
+ configured in independent mode. Without DMA transfer,
+ register accessed by LL function
+ @ref LL_ADC_REG_ReadConversionData32() and other
+ functions @ref LL_ADC_REG_ReadConversionDatax() */
/**
* @}
*/
@@ -766,9 +811,9 @@
/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
* @{
*/
-#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
-#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
-#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
+#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1 ) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */
+#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
/**
* @}
*/
@@ -825,7 +870,11 @@
/** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
* @{
*/
-#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on calibration parameters. This value is coded on 16 bits (to fit on signed word or double word) and corresponds to an inconsistent temperature value. */
+#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
+ @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
+ calibration parameters. This value is coded on 16 bits
+ (to fit on signed word or double word) and corresponds
+ to an inconsistent temperature value. */
/**
* @}
*/
@@ -1090,7 +1139,8 @@
* (1) On STM32WL, parameter can be set in ADC group sequencer
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
- * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
+ connected to a GPIO pin).
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/
#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
@@ -1313,8 +1363,9 @@
* @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
-#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
- (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
+#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
+ (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
+ & LL_ADC_AWD_THRESHOLD_LOW)
/**
* @brief Helper macro to select the ADC common instance
@@ -1540,12 +1591,15 @@
* @note ADC measurement data must correspond to a resolution of 12 bits
* (full scale digital value 4095). If not the case, the data must be
* preliminarily rescaled to an equivalent resolution of 12 bits.
- * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
+ (unit: uV/DegCelsius).
* On STM32WL, refer to device datasheet parameter "Avg_Slope".
- * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
- * On STM32WL, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
- * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
- * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
+ (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32WL, refer to datasheet parameter "V30" (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
+ (see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
* This parameter can be one of the following values:
@@ -1631,7 +1685,8 @@
* @}
*/
-/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
+ * ADC instances
* @{
*/
@@ -2756,7 +2811,8 @@
/* other bits reserved for other purpose. */
MODIFY_REG(ADCx->CHSELR,
ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
- ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
/**
@@ -3519,8 +3575,9 @@
/* Retrieve sampling time bit corresponding to the selected channel */
/* and shift it to position 0. */
uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
- >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) &
- 0x1FUL));
+ >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ + ADC_SMPR_SMPSEL0_BITOFFSET_POS)
+ & 0x1FUL));
/* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
@@ -3618,7 +3675,8 @@
}
else
{
- preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
+ preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR,
+ ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
}
MODIFY_REG(*preg,
@@ -3705,8 +3763,10 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
{
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
- + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,
+ ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
+ * ADC_AWD_CR12_REGOFFSETGAP_VAL));
uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
@@ -3805,12 +3865,12 @@
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
- * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
- * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
- * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
- * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
- * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
- * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
+ * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n
+ * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n
+ * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n
+ * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n
+ * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n
+ * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
@@ -3828,10 +3888,15 @@
/* "AWDy". */
/* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
/* containing other bits reserved for other purpose. */
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
+ (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
+ >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
+ + ((ADC_AWD_CR3_REGOFFSET & AWDy)
+ >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))
+ );
MODIFY_REG(*preg,
- ADC_TR1_HT1 | ADC_TR1_LT1,
+ ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
(AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
}
@@ -3881,12 +3946,12 @@
* ADC state:
* ADC can be disabled, enabled with or without conversion on going
* on ADC group regular.
- * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
- * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
- * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
- * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
- * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
- * TR3 LT3 LL_ADC_SetAnalogWDThresholds
+ * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n
+ * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n
+ * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n
+ * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n
+ * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n
+ * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
@@ -3906,9 +3971,11 @@
/* "AWDThresholdsHighLow" and "AWDy". */
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
- (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
- + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
+ (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
+ >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
+ + ((ADC_AWD_CR3_REGOFFSET & AWDy)
+ >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
MODIFY_REG(*preg,
AWDThresholdsHighLow,
@@ -3926,12 +3993,12 @@
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
- * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
- * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
- * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
- * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
- * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
- * TR3 LT3 LL_ADC_GetAnalogWDThresholds
+ * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n
+ * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n
+ * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n
+ * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n
+ * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n
+ * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
@@ -3950,14 +4017,16 @@
/* "AWDThresholdsHighLow" and "AWDy". */
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
- (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
- + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
+ (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
+ >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
+ + ((ADC_AWD_CR3_REGOFFSET & AWDy)
+ >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
return (uint32_t)(READ_BIT(*preg,
- (AWDThresholdsHighLow | ADC_TR1_LT1))
+ (AWDThresholdsHighLow | ADC_AWD1TR_LT1))
>> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
- & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
+ & ~(AWDThresholdsHighLow & ADC_AWD1TR_LT1)));
}
/**
diff --git a/Inc/stm32wlxx_ll_comp.h b/Inc/stm32wlxx_ll_comp.h
index 5d4b6dc..bb679ab 100644
--- a/Inc/stm32wlxx_ll_comp.h
+++ b/Inc/stm32wlxx_ll_comp.h
@@ -318,7 +318,7 @@
* @arg @ref LL_COMP_WINDOWMODE_DISABLE
* @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
*/
-__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON)
{
return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WINMODE));
}
@@ -355,7 +355,7 @@
* @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
* @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
*/
-__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE));
}
@@ -449,7 +449,7 @@
*
* (*) Parameter not available on all devices.
*/
-__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
}
@@ -512,7 +512,7 @@
* @arg @ref LL_COMP_INPUT_MINUS_IO3
* @arg @ref LL_COMP_INPUT_MINUS_IO4
*/
-__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
}
@@ -543,7 +543,7 @@
* @arg @ref LL_COMP_HYSTERESIS_MEDIUM
* @arg @ref LL_COMP_HYSTERESIS_HIGH
*/
-__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
}
@@ -578,7 +578,7 @@
* @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
* @arg @ref LL_COMP_OUTPUTPOL_INVERTED
*/
-__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
}
@@ -621,7 +621,7 @@
* (1) Parameter availability depending on timer availability
* on the selected device.
*/
-__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING));
}
@@ -666,7 +666,7 @@
* @param COMPx Comparator instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx)
{
return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL);
}
@@ -693,7 +693,7 @@
* @param COMPx Comparator instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx)
{
return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL);
}
@@ -718,7 +718,7 @@
* @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
* @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
*/
-__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
>> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
@@ -734,7 +734,7 @@
*/
ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
-ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct);
void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
/**
diff --git a/Inc/stm32wlxx_ll_cortex.h b/Inc/stm32wlxx_ll_cortex.h
index 6fb22c0..a69d406 100644
--- a/Inc/stm32wlxx_ll_cortex.h
+++ b/Inc/stm32wlxx_ll_cortex.h
@@ -169,7 +169,7 @@
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+
/**
* @}
*/
@@ -583,7 +583,7 @@
* or @ref LL_MPU_REGION_SIZE_4GB
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO
* or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
- * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+ * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
diff --git a/Inc/stm32wlxx_ll_dac.h b/Inc/stm32wlxx_ll_dac.h
index a9264e7..943184a 100644
--- a/Inc/stm32wlxx_ll_dac.h
+++ b/Inc/stm32wlxx_ll_dac.h
@@ -52,19 +52,23 @@
/* - channel register offset of data holding register DHRx */
/* - channel register offset of data output register DORx */
/* - channel register offset of sample-and-hold sample time register SHSRx */
-#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
+ CR, MCR, CCR, SHHR, SHRR of channel 1 */
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET)
#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 24 bits) */
#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
-#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
+ | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
@@ -72,18 +76,33 @@
#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET)
-#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
-#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted to position 0 */
-#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted to position 0 */
+#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
+ DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
+#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
+ to position 0 */
+#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
+ to position 0 */
-#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
-#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
-#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
+#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 28 bits) */
+#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 20 bits) */
+#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 24 bits) */
+#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
+ channel 1 or 2 versus DORx channel 1
+ (shifted left of 5 bits) */
+#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
+ channel 1 or 2 versus SHSRx channel 1
+ (shifted left of 6 bits) */
/* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
+ bits (voltage range determined by analog voltage
+ references Vref+ and Vref-, refer to reference manual) */
/**
* @}
@@ -102,7 +121,7 @@
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
-*/
+ */
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
@@ -122,38 +141,50 @@
*/
typedef struct
{
- uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
+ uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
+ internal (SW start) or from external peripheral
+ (timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetTriggerSource(). */
uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveAutoGeneration(). */
uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
- If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
- If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
- @note If waveform automatic generation mode is disabled, this parameter is discarded.
+ If waveform automatic generation mode is set to noise, this parameter
+ can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+ If waveform automatic generation mode is set to triangle,
+ this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+ @note If waveform automatic generation mode is disabled,
+ this parameter is discarded.
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude()
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveNoiseLFSR(),
+ @ref LL_DAC_SetWaveTriangleAmplitude()
depending on the wave automatic generation selected. */
uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputBuffer(). */
uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputConnection(). */
- uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
- This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
+ uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
+ channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputMode(). */
} LL_DAC_InitTypeDef;
/**
@@ -174,7 +205,6 @@
#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
-
/**
* @}
*/
@@ -336,7 +366,7 @@
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
-#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
/* Delay for DAC channel voltage settling time. */
/* Note: DAC channel startup time depends on board application environment: */
@@ -403,7 +433,7 @@
* number is returned.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
- * @retval 1...2
+ * @retval 1
*/
#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
((__CHANNEL__) & DAC_SWTR_CHX_MASK)
@@ -454,7 +484,7 @@
* @ref LL_DAC_ConvertData12RightAligned().
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
* (unit: mVolt).
@@ -466,9 +496,9 @@
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
__DAC_VOLTAGE__,\
__DAC_RESOLUTION__) \
- ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- / (__VREFANALOG_VOLTAGE__) \
- )
+((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+)
/**
* @}
@@ -483,6 +513,7 @@
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
* @{
*/
+
/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
* @{
*/
@@ -517,7 +548,7 @@
* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
* @arg @ref LL_DAC_MODE_CALIBRATION
*/
-__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -552,7 +583,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
*/
-__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -607,7 +638,7 @@
* @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
*/
-__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -646,7 +677,7 @@
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
*/
-__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -708,7 +739,7 @@
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
*/
-__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -771,7 +802,7 @@
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
*/
-__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -863,7 +894,7 @@
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
*/
-__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -902,7 +933,7 @@
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
*/
-__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -957,7 +988,7 @@
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
*/
-__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -980,11 +1011,10 @@
*/
__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_SHSR1_TSAMPLE1,
- SampleTime);
+ MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
}
/**
@@ -996,9 +1026,10 @@
* @arg @ref LL_DAC_CHANNEL_1
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
}
@@ -1029,7 +1060,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1062,7 +1093,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1118,7 +1149,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1138,7 +1169,8 @@
* LL_DMA_ConfigAddresses(DMA1,
* LL_DMA_CHANNEL_1,
* (uint32_t)&< array or variable >,
- * LL_DAC_DMA_GetRegAddr(DAC, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+ * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
+ * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
@@ -1152,12 +1184,12 @@
* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
* @retval DAC register address
*/
-__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
{
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
/* DAC channel selected. */
- return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1,
- ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
+ return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
}
/**
* @}
@@ -1207,7 +1239,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1259,7 +1291,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1304,11 +1336,10 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_DHR12R1_DACC1DHR,
- Data);
+ MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
}
/**
@@ -1324,11 +1355,10 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_DHR12L1_DACC1DHR,
- Data);
+ MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
}
/**
@@ -1344,11 +1374,10 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_DHR8R1_DACC1DHR,
- Data);
+ MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
}
/**
@@ -1363,9 +1392,10 @@
* @arg @ref LL_DAC_CHANNEL_1
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
}
@@ -1377,13 +1407,14 @@
/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
* @{
*/
+
/**
* @brief Get DAC calibration offset flag for DAC channel 1
* @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
}
@@ -1394,19 +1425,18 @@
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
}
-
/**
* @brief Get DAC underrun flag for DAC channel 1
* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
}
@@ -1458,7 +1488,7 @@
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
}
@@ -1473,7 +1503,7 @@
*/
ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
/**
diff --git a/Inc/stm32wlxx_ll_exti.h b/Inc/stm32wlxx_ll_exti.h
index d796f21..b5c4323 100644
--- a/Inc/stm32wlxx_ll_exti.h
+++ b/Inc/stm32wlxx_ll_exti.h
@@ -124,13 +124,13 @@
#if defined(DUAL_CORE)
#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */
-#endif
+#endif /* DUAL_CORE */
#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */
#if defined(DUAL_CORE)
#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */
#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */
#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */
-#endif
+#endif /* DUAL_CORE */
#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */
#define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */
#define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */
@@ -138,14 +138,14 @@
#define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */
#if defined(DUAL_CORE)
#define LL_EXTI_LINE_ALL_32_63 (EXTI_IMR2_IM34 | EXTI_IMR2_IM36 | EXTI_IMR2_IM37 | \
- EXTI_IMR2_IM38 | EXTI_IMR2_IM39 | EXTI_IMR2_IM40 | \
- EXTI_IMR2_IM41 | EXTI_IMR2_IM42 | EXTI_IMR2_IM43 | \
- EXTI_IMR2_IM44 | EXTI_IMR2_IM45 | EXTI_IMR2_IM46) /*!< All Extended line not reserved*/
+ EXTI_IMR2_IM38 | EXTI_IMR2_IM39 | EXTI_IMR2_IM40 | \
+ EXTI_IMR2_IM41 | EXTI_IMR2_IM42 | EXTI_IMR2_IM43 | \
+ EXTI_IMR2_IM44 | EXTI_IMR2_IM45 | EXTI_IMR2_IM46) /*!< All Extended line not reserved*/
#else
#define LL_EXTI_LINE_ALL_32_63 (EXTI_IMR2_IM34 | EXTI_IMR2_IM38 | EXTI_IMR2_IM42 | \
- EXTI_IMR2_IM43 | EXTI_IMR2_IM44 | EXTI_IMR2_IM45 | \
- EXTI_IMR2_IM46) /*!< All Extended line not reserved*/
-#endif
+ EXTI_IMR2_IM43 | EXTI_IMR2_IM44 | EXTI_IMR2_IM45 | \
+ EXTI_IMR2_IM46) /*!< All Extended line not reserved*/
+#endif /* DUAL_CORE */
#if defined(USE_FULL_LL_DRIVER)
#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
@@ -217,8 +217,8 @@
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
+ * @{
+ */
/** @defgroup EXTI_LL_EF_IT_Management IT_Management
* @{
*/
@@ -311,7 +311,7 @@
{
SET_BIT(EXTI->C2IMR1, ExtiLine);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63
@@ -363,7 +363,7 @@
{
SET_BIT(EXTI->C2IMR2, ExtiLine);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
@@ -453,7 +453,7 @@
{
CLEAR_BIT(EXTI->C2IMR1, ExtiLine);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63
@@ -505,7 +505,7 @@
{
CLEAR_BIT(EXTI->C2IMR2, ExtiLine);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
@@ -595,7 +595,7 @@
{
return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
@@ -647,7 +647,7 @@
{
return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @}
@@ -721,7 +721,7 @@
{
SET_BIT(EXTI->C2EMR1, ExtiLine);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Enable ExtiLine Event request for Lines in range 32 to 63
@@ -751,7 +751,7 @@
{
SET_BIT(EXTI->C2EMR2, ExtiLine);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
@@ -817,7 +817,7 @@
{
CLEAR_BIT(EXTI->C2EMR1, ExtiLine);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Disable ExtiLine Event request for Lines in range 32 to 63
@@ -847,7 +847,7 @@
{
CLEAR_BIT(EXTI->C2EMR2, ExtiLine);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
@@ -913,7 +913,7 @@
{
return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
@@ -943,7 +943,7 @@
{
return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
-#endif
+#endif /* DUAL_CORE */
/**
* @}
@@ -1406,7 +1406,7 @@
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_45
+ * @arg @ref LL_EXTI_LINE_45
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
diff --git a/Inc/stm32wlxx_ll_lptim.h b/Inc/stm32wlxx_ll_lptim.h
index fea44c5..d695f94 100644
--- a/Inc/stm32wlxx_ll_lptim.h
+++ b/Inc/stm32wlxx_ll_lptim.h
@@ -332,6 +332,19 @@
* @{
*/
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
+#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
+#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
+#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
+#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
+#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
+/**
+@endcond
+ */
+
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
* @{
@@ -339,7 +352,7 @@
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
-ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
/**
* @}
@@ -369,7 +382,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
@@ -422,7 +435,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
}
@@ -465,7 +478,7 @@
* @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
* @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
}
@@ -480,7 +493,7 @@
* @note autoreload value be strictly greater than the compare value.
* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
* @param LPTIMx Low-Power Timer instance
- * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
@@ -492,9 +505,9 @@
* @brief Get actual auto reload value
* @rmtoll ARR ARR LL_LPTIM_GetAutoReload
* @param LPTIMx Low-Power Timer instance
- * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
}
@@ -518,7 +531,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
}
@@ -545,7 +558,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
}
@@ -560,7 +573,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval Counter value
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
}
@@ -588,7 +601,7 @@
* @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
* @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
}
@@ -637,7 +650,7 @@
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
}
@@ -664,7 +677,7 @@
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
}
@@ -708,7 +721,7 @@
* @arg @ref LL_LPTIM_PRESCALER_DIV64
* @arg @ref LL_LPTIM_PRESCALER_DIV128
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
}
@@ -788,7 +801,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
@@ -863,7 +876,7 @@
* (*) Value not defined in all devices. \n
*
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
}
@@ -878,7 +891,7 @@
* @arg @ref LL_LPTIM_TRIG_FILTER_4
* @arg @ref LL_LPTIM_TRIG_FILTER_8
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
}
@@ -892,7 +905,7 @@
* @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
}
@@ -928,7 +941,7 @@
* @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
* @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
}
@@ -970,7 +983,7 @@
* @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
* @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
}
@@ -985,7 +998,7 @@
* @arg @ref LL_LPTIM_CLK_FILTER_4
* @arg @ref LL_LPTIM_CLK_FILTER_8
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
}
@@ -1023,7 +1036,7 @@
* @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
* @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
}
@@ -1062,7 +1075,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
@@ -1075,13 +1088,14 @@
* @{
*/
+
/**
* @brief Clear the compare match flag (CMPMCF)
- * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
+ * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
-__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
}
@@ -1092,18 +1106,18 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
}
/**
* @brief Clear the autoreload match flag (ARRMCF)
- * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
+ * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
-__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
}
@@ -1114,7 +1128,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
@@ -1136,7 +1150,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
@@ -1159,7 +1173,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
}
@@ -1182,7 +1196,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
@@ -1205,7 +1219,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
@@ -1228,7 +1242,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
@@ -1251,7 +1265,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
{
return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
}
@@ -1273,7 +1287,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
{
return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
}
@@ -1314,7 +1328,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
}
@@ -1347,7 +1361,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
}
@@ -1380,7 +1394,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
}
@@ -1413,7 +1427,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
}
@@ -1446,7 +1460,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
}
@@ -1479,7 +1493,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
}
@@ -1512,7 +1526,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
{
return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
}
@@ -1545,7 +1559,7 @@
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
{
return ((READ_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE) == (LPTIM_IER_REPOKIE)) ? 1UL : 0UL);
}
@@ -1578,7 +1592,7 @@
* @param LPTIMx Low-Power Timer instance
*@ retval State of bit(1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
{
return ((READ_BIT(LPTIMx->IER, LPTIM_IER_UEIE) == (LPTIM_IER_UEIE)) ? 1UL : 0UL);
}
diff --git a/Inc/stm32wlxx_ll_lpuart.h b/Inc/stm32wlxx_ll_lpuart.h
index 467a6be..1e952b4 100644
--- a/Inc/stm32wlxx_ll_lpuart.h
+++ b/Inc/stm32wlxx_ll_lpuart.h
@@ -522,7 +522,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
@@ -555,7 +555,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
}
@@ -590,7 +590,7 @@
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
}
@@ -625,7 +625,7 @@
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
}
@@ -689,7 +689,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
}
@@ -767,7 +767,7 @@
* @arg @ref LL_LPUART_DIRECTION_TX
* @arg @ref LL_LPUART_DIRECTION_TX_RX
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
}
@@ -801,7 +801,7 @@
* @arg @ref LL_LPUART_PARITY_EVEN
* @arg @ref LL_LPUART_PARITY_ODD
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
}
@@ -828,7 +828,7 @@
* @arg @ref LL_LPUART_WAKEUP_IDLELINE
* @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
}
@@ -857,7 +857,7 @@
* @arg @ref LL_LPUART_DATAWIDTH_8B
* @arg @ref LL_LPUART_DATAWIDTH_9B
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
}
@@ -890,7 +890,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
}
@@ -937,7 +937,7 @@
* @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
}
@@ -964,7 +964,7 @@
* @arg @ref LL_LPUART_STOPBITS_1
* @arg @ref LL_LPUART_STOPBITS_2
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
}
@@ -1022,7 +1022,7 @@
* @arg @ref LL_LPUART_TXRX_STANDARD
* @arg @ref LL_LPUART_TXRX_SWAPPED
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
}
@@ -1049,7 +1049,7 @@
* @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
}
@@ -1076,7 +1076,7 @@
* @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
}
@@ -1106,7 +1106,7 @@
* @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
}
@@ -1137,7 +1137,7 @@
* @arg @ref LL_LPUART_BITORDER_LSBFIRST
* @arg @ref LL_LPUART_BITORDER_MSBFIRST
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
}
@@ -1181,7 +1181,7 @@
* @param LPUARTx LPUART Instance
* @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
}
@@ -1194,7 +1194,7 @@
* @arg @ref LL_LPUART_ADDRESS_DETECT_4B
* @arg @ref LL_LPUART_ADDRESS_DETECT_7B
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
}
@@ -1271,7 +1271,7 @@
* @arg @ref LL_LPUART_HWCONTROL_CTS
* @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
}
@@ -1304,7 +1304,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
@@ -1333,7 +1333,7 @@
* @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
* @arg @ref LL_LPUART_WAKEUP_ON_RXNE
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
}
@@ -1398,7 +1398,8 @@
* @arg @ref LL_LPUART_PRESCALER_DIV256
* @retval Baud Rate
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
+ uint32_t PrescalerValue)
{
uint32_t lpuartdiv;
uint32_t brrresult;
@@ -1454,7 +1455,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
}
@@ -1485,7 +1486,7 @@
* @param LPUARTx LPUART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : c
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
}
@@ -1508,7 +1509,7 @@
* @param LPUARTx LPUART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
}
@@ -1541,7 +1542,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
}
@@ -1568,7 +1569,7 @@
* @arg @ref LL_LPUART_DE_POLARITY_HIGH
* @arg @ref LL_LPUART_DE_POLARITY_LOW
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
}
@@ -1587,7 +1588,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
}
@@ -1598,7 +1599,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
}
@@ -1609,7 +1610,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
}
@@ -1620,7 +1621,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
}
@@ -1631,7 +1632,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
}
@@ -1645,7 +1646,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
}
@@ -1656,7 +1657,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
}
@@ -1670,7 +1671,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
}
@@ -1681,7 +1682,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
}
@@ -1692,7 +1693,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
}
@@ -1703,7 +1704,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
}
@@ -1714,7 +1715,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
}
@@ -1725,7 +1726,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
}
@@ -1736,7 +1737,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
@@ -1747,7 +1748,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
}
@@ -1758,7 +1759,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
@@ -1769,7 +1770,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
}
@@ -1780,7 +1781,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
}
@@ -1791,7 +1792,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
}
@@ -1802,7 +1803,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
}
@@ -1813,7 +1814,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
}
@@ -2237,7 +2238,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
}
@@ -2251,7 +2252,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
}
@@ -2262,7 +2263,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
}
@@ -2276,7 +2277,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
}
@@ -2287,7 +2288,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
}
@@ -2298,7 +2299,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
}
@@ -2309,7 +2310,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
}
@@ -2320,7 +2321,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
}
@@ -2331,7 +2332,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
}
@@ -2342,7 +2343,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
@@ -2353,7 +2354,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
}
@@ -2364,7 +2365,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
}
@@ -2375,7 +2376,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
}
@@ -2416,7 +2417,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
}
@@ -2449,7 +2450,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
}
@@ -2482,7 +2483,7 @@
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
}
@@ -2497,7 +2498,7 @@
* @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
-__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
{
uint32_t data_reg_addr;
@@ -2529,7 +2530,7 @@
* @param LPUARTx LPUART Instance
* @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
{
return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
@@ -2540,7 +2541,7 @@
* @param LPUARTx LPUART Instance
* @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
*/
-__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
{
return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
}
@@ -2620,8 +2621,8 @@
/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
* @{
*/
-ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
-ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
+ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
/**
* @}
diff --git a/Inc/stm32wlxx_ll_rcc.h b/Inc/stm32wlxx_ll_rcc.h
index 919de37..1febd50 100644
--- a/Inc/stm32wlxx_ll_rcc.h
+++ b/Inc/stm32wlxx_ll_rcc.h
@@ -345,8 +345,8 @@
/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
* @{
*/
-#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
-#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
+#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
+#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
/**
* @}
*/
@@ -427,10 +427,10 @@
/** @defgroup RCC_LL_EC_ADC_CLKSRC ADC CLKSRC
* @{
*/
-#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock*/
-#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock*/
-#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock*/
-#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock*/
+#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock */
+#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock */
+#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock */
+#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock */
/**
* @}
*/
@@ -438,10 +438,10 @@
/** @defgroup RCC_LL_EC_RNG_CLKSRC RNG CLKSRC
* @{
*/
-#define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL selected as RNG Clock */
-#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as RNG clock*/
-#define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as RNG clock*/
-#define LL_RCC_RNG_CLKSOURCE_MSI (RCC_CCIPR_RNGSEL_1 | RCC_CCIPR_RNGSEL_0) /*!< MSI selected as RNG clock*/
+#define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL selected as RNG Clock */
+#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as RNG clock */
+#define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as RNG clock */
+#define LL_RCC_RNG_CLKSOURCE_MSI (RCC_CCIPR_RNGSEL_1 | RCC_CCIPR_RNGSEL_0) /*!< MSI selected as RNG clock */
/**
* @}
*/
@@ -524,7 +524,7 @@
/** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
* @{
*/
-#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
+#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */
#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */
#define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */
@@ -617,7 +617,7 @@
* @{
*/
#define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */
-#define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */
+#define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */
/**
* @}
*/
diff --git a/Inc/stm32wlxx_ll_system.h b/Inc/stm32wlxx_ll_system.h
index e8db15e..0d5523b 100644
--- a/Inc/stm32wlxx_ll_system.h
+++ b/Inc/stm32wlxx_ll_system.h
@@ -591,7 +591,7 @@
#if defined(CORE_CM0PLUS)
return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (SYSCFG_EXTICR1_EXTI0 << ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL))) >> ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL));
#else
- return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)) >> ((POSITION_VAL(Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)) & 0x0000000FUL)));
+ return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)) >> POSITION_VAL(Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT));
#endif
}
diff --git a/Inc/stm32wlxx_ll_tim.h b/Inc/stm32wlxx_ll_tim.h
index d276353..f9cea59 100644
--- a/Inc/stm32wlxx_ll_tim.h
+++ b/Inc/stm32wlxx_ll_tim.h
@@ -1199,8 +1199,8 @@
/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
* @{
*/
-#define LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR1_RMP_MASK /* !< No internal trigger on TIM2_ITR1 */
-#define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */
+#define LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR1_RMP_MASK /*!< No internal trigger on TIM2_ITR1 */
+#define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR1_ITR1_RMP) /*!< TIM2_ITR1 is connected to USB SOF */
/**
* @}
*/
@@ -1294,10 +1294,6 @@
* @}
*/
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
- * @{
- */
-
/**
* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
@@ -1441,7 +1437,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
}
@@ -1474,7 +1470,7 @@
* @param TIMx Timer instance
* @retval Inverted state of bit (0 or 1).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
}
@@ -1508,7 +1504,7 @@
* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
*/
-__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
}
@@ -1535,7 +1531,7 @@
* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
*/
-__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
}
@@ -1579,7 +1575,7 @@
* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
*/
-__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
{
uint32_t counter_mode;
@@ -1621,7 +1617,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
}
@@ -1658,7 +1654,7 @@
* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
*/
-__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
}
@@ -1685,7 +1681,7 @@
* @param TIMx Timer instance
* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
*/
-__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CNT));
}
@@ -1698,7 +1694,7 @@
* @arg @ref LL_TIM_COUNTERDIRECTION_UP
* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
*/
-__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
}
@@ -1725,7 +1721,7 @@
* @param TIMx Timer instance
* @retval Prescaler value between Min_Data=0 and Max_Data=65535
*/
-__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->PSC));
}
@@ -1754,7 +1750,7 @@
* @param TIMx Timer instance
* @retval Auto-reload value
*/
-__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->ARR));
}
@@ -1782,7 +1778,7 @@
* @param TIMx Timer instance
* @retval Repetition counter value
*/
-__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->RCR));
}
@@ -1816,7 +1812,7 @@
* @param Counter Counter value
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
{
return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
}
@@ -1895,7 +1891,7 @@
* @arg @ref LL_TIM_CCDMAREQUEST_CC
* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
*/
-__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
}
@@ -2130,7 +2126,7 @@
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2196,7 +2192,7 @@
* @arg @ref LL_TIM_OCPOLARITY_HIGH
* @arg @ref LL_TIM_OCPOLARITY_LOW
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
@@ -2265,7 +2261,7 @@
* @arg @ref LL_TIM_OCIDLESTATE_LOW
* @arg @ref LL_TIM_OCIDLESTATE_HIGH
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
@@ -2634,7 +2630,7 @@
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR1));
}
@@ -2650,7 +2646,7 @@
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR2));
}
@@ -2666,7 +2662,7 @@
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR3));
}
@@ -2682,7 +2678,7 @@
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR4));
}
@@ -2695,7 +2691,7 @@
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
}
@@ -2708,7 +2704,7 @@
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR6));
}
@@ -2828,7 +2824,7 @@
* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
* @arg @ref LL_TIM_ACTIVEINPUT_TRC
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2879,7 +2875,7 @@
* @arg @ref LL_TIM_ICPSC_DIV4
* @arg @ref LL_TIM_ICPSC_DIV8
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2954,7 +2950,7 @@
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -3011,7 +3007,7 @@
* @arg @ref LL_TIM_IC_POLARITY_FALLING
* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
@@ -3068,7 +3064,7 @@
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR1));
}
@@ -3084,7 +3080,7 @@
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR2));
}
@@ -3100,7 +3096,7 @@
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR3));
}
@@ -3116,7 +3112,7 @@
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR4));
}
@@ -3163,7 +3159,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
}
@@ -3343,7 +3339,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
}
@@ -3669,7 +3665,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
}
@@ -3712,7 +3708,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
}
@@ -3977,7 +3973,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
}
@@ -3999,7 +3995,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
}
@@ -4021,7 +4017,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
}
@@ -4043,7 +4039,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
}
@@ -4065,7 +4061,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
}
@@ -4087,7 +4083,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
}
@@ -4109,7 +4105,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
}
@@ -4131,7 +4127,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
}
@@ -4153,7 +4149,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
}
@@ -4175,7 +4171,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
}
@@ -4197,7 +4193,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
}
@@ -4220,7 +4216,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
}
@@ -4243,7 +4239,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
}
@@ -4266,7 +4262,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
}
@@ -4289,7 +4285,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
}
@@ -4311,7 +4307,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
}
@@ -4351,7 +4347,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
}
@@ -4384,7 +4380,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
}
@@ -4417,7 +4413,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
}
@@ -4450,7 +4446,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
}
@@ -4483,7 +4479,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
}
@@ -4516,7 +4512,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
}
@@ -4549,7 +4545,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
}
@@ -4582,7 +4578,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
}
@@ -4622,7 +4618,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
}
@@ -4655,7 +4651,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
}
@@ -4688,7 +4684,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
}
@@ -4721,7 +4717,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
}
@@ -4754,7 +4750,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
}
@@ -4787,7 +4783,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
}
@@ -4820,7 +4816,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
}
@@ -4942,17 +4938,17 @@
ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
/**
* @}
*/
diff --git a/Inc/stm32wlxx_ll_usart.h b/Inc/stm32wlxx_ll_usart.h
index 0249b36..07f4200 100644
--- a/Inc/stm32wlxx_ll_usart.h
+++ b/Inc/stm32wlxx_ll_usart.h
@@ -648,7 +648,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
@@ -687,7 +687,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
}
@@ -726,7 +726,7 @@
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
*/
-__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
}
@@ -765,7 +765,7 @@
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
*/
-__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
}
@@ -836,7 +836,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
}
@@ -914,7 +914,7 @@
* @arg @ref LL_USART_DIRECTION_TX
* @arg @ref LL_USART_DIRECTION_TX_RX
*/
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
}
@@ -948,7 +948,7 @@
* @arg @ref LL_USART_PARITY_EVEN
* @arg @ref LL_USART_PARITY_ODD
*/
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
}
@@ -975,7 +975,7 @@
* @arg @ref LL_USART_WAKEUP_IDLELINE
* @arg @ref LL_USART_WAKEUP_ADDRESSMARK
*/
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
}
@@ -1006,7 +1006,7 @@
* @arg @ref LL_USART_DATAWIDTH_8B
* @arg @ref LL_USART_DATAWIDTH_9B
*/
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
}
@@ -1039,7 +1039,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
}
@@ -1066,7 +1066,7 @@
* @arg @ref LL_USART_OVERSAMPLING_16
* @arg @ref LL_USART_OVERSAMPLING_8
*/
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
}
@@ -1098,7 +1098,7 @@
* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
*/
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
}
@@ -1129,7 +1129,7 @@
* @arg @ref LL_USART_PHASE_1EDGE
* @arg @ref LL_USART_PHASE_2EDGE
*/
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
}
@@ -1160,7 +1160,7 @@
* @arg @ref LL_USART_POLARITY_LOW
* @arg @ref LL_USART_POLARITY_HIGH
*/
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
}
@@ -1239,7 +1239,7 @@
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
*/
-__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
}
@@ -1278,7 +1278,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
}
@@ -1309,7 +1309,7 @@
* @arg @ref LL_USART_STOPBITS_1_5
* @arg @ref LL_USART_STOPBITS_2
*/
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
}
@@ -1370,7 +1370,7 @@
* @arg @ref LL_USART_TXRX_STANDARD
* @arg @ref LL_USART_TXRX_SWAPPED
*/
-__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
}
@@ -1397,7 +1397,7 @@
* @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
*/
-__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
}
@@ -1424,7 +1424,7 @@
* @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
*/
-__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
}
@@ -1453,7 +1453,7 @@
* @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
*/
-__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
}
@@ -1484,7 +1484,7 @@
* @arg @ref LL_USART_BITORDER_LSBFIRST
* @arg @ref LL_USART_BITORDER_MSBFIRST
*/
-__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
}
@@ -1523,7 +1523,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
}
@@ -1591,7 +1591,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
}
@@ -1635,7 +1635,7 @@
* @param USARTx USART Instance
* @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
*/
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
}
@@ -1648,7 +1648,7 @@
* @arg @ref LL_USART_ADDRESS_DETECT_4B
* @arg @ref LL_USART_ADDRESS_DETECT_7B
*/
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
}
@@ -1737,7 +1737,7 @@
* @arg @ref LL_USART_HWCONTROL_CTS
* @arg @ref LL_USART_HWCONTROL_RTS_CTS
*/
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
}
@@ -1770,7 +1770,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
}
@@ -1803,7 +1803,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
@@ -1836,7 +1836,7 @@
* @arg @ref LL_USART_WAKEUP_ON_STARTBIT
* @arg @ref LL_USART_WAKEUP_ON_RXNE
*/
-__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
}
@@ -1924,7 +1924,7 @@
* @arg @ref LL_USART_OVERSAMPLING_8
* @retval Baud Rate
*/
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling)
{
uint32_t usartdiv;
@@ -1973,7 +1973,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
*/
-__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
}
@@ -1996,7 +1996,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
}
@@ -2043,7 +2043,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
}
@@ -2074,7 +2074,7 @@
* @arg @ref LL_USART_IRDA_POWER_NORMAL
* @arg @ref LL_USART_PHASE_2EDGE
*/
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
}
@@ -2091,7 +2091,7 @@
*/
__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
- MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
@@ -2103,7 +2103,7 @@
* @param USARTx USART Instance
* @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
*/
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
}
@@ -2150,7 +2150,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
}
@@ -2189,7 +2189,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
}
@@ -2221,7 +2221,7 @@
* @param USARTx USART Instance
* @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
*/
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
}
@@ -2238,7 +2238,7 @@
*/
__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
- MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
@@ -2250,7 +2250,7 @@
* @param USARTx USART Instance
* @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
*/
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
}
@@ -2267,7 +2267,7 @@
*/
__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
{
- MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
}
/**
@@ -2279,7 +2279,7 @@
* @param USARTx USART Instance
* @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
*/
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
}
@@ -2326,7 +2326,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
}
@@ -2372,7 +2372,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
}
@@ -2414,7 +2414,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
}
@@ -2453,7 +2453,7 @@
* @arg @ref LL_USART_LINBREAK_DETECT_10B
* @arg @ref LL_USART_LINBREAK_DETECT_11B
*/
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
}
@@ -2492,7 +2492,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
}
@@ -2527,7 +2527,7 @@
* @param USARTx USART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
*/
-__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
}
@@ -2554,7 +2554,7 @@
* @param USARTx USART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
*/
-__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
}
@@ -2593,7 +2593,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
}
@@ -2624,7 +2624,7 @@
* @arg @ref LL_USART_DE_POLARITY_HIGH
* @arg @ref LL_USART_DE_POLARITY_LOW
*/
-__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
}
@@ -2920,7 +2920,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
}
@@ -2931,7 +2931,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
}
@@ -2942,7 +2942,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
}
@@ -2953,7 +2953,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
}
@@ -2964,7 +2964,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
}
@@ -2980,7 +2980,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
}
@@ -2991,7 +2991,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
}
@@ -3007,7 +3007,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
}
@@ -3020,7 +3020,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
}
@@ -3033,7 +3033,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
}
@@ -3046,7 +3046,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
}
@@ -3057,7 +3057,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
}
@@ -3070,7 +3070,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
}
@@ -3083,7 +3083,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
}
@@ -3096,7 +3096,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
}
@@ -3109,7 +3109,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
}
@@ -3120,7 +3120,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
}
@@ -3131,7 +3131,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
}
@@ -3142,7 +3142,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
}
@@ -3153,7 +3153,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
@@ -3166,7 +3166,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
}
@@ -3177,7 +3177,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
@@ -3188,7 +3188,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
}
@@ -3201,7 +3201,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
}
@@ -3214,7 +3214,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
}
@@ -3225,7 +3225,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
}
@@ -3238,7 +3238,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
}
@@ -3251,7 +3251,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
}
@@ -3883,7 +3883,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
}
@@ -3899,7 +3899,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
}
@@ -3910,7 +3910,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
}
@@ -3926,7 +3926,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
}
@@ -3937,7 +3937,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
}
@@ -3948,7 +3948,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
}
@@ -3959,7 +3959,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
}
@@ -3972,7 +3972,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
}
@@ -3985,7 +3985,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
}
@@ -3998,7 +3998,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
}
@@ -4011,7 +4011,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
}
@@ -4022,7 +4022,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
}
@@ -4035,7 +4035,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
@@ -4048,7 +4048,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
}
@@ -4061,7 +4061,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
}
@@ -4074,7 +4074,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
}
@@ -4087,7 +4087,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
}
@@ -4128,7 +4128,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
}
@@ -4161,7 +4161,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
}
@@ -4194,7 +4194,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
}
@@ -4209,7 +4209,7 @@
* @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
{
uint32_t data_reg_addr;
@@ -4241,7 +4241,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
{
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
@@ -4252,7 +4252,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x1FF
*/
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
{
return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
}
@@ -4360,10 +4360,10 @@
/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
* @{
*/
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct);
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
/**
* @}
diff --git a/README.md b/README.md
index db18681..26425a7 100644
--- a/README.md
+++ b/README.md
@@ -28,16 +28,7 @@
## Compatibility information
-In this table, you can find the successive versions of this HAL-LL Driver component, in line with the corresponding versions of the full MCU package:
-
-It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in this table.
-
-HAL Driver WL | CMSIS Device WL | CMSIS Core | Was delivered in the full MCU package
-------------- | --------------- | -------------- | -------------------------------------
-Tag v1.0.0 | Tag v1.0.0 | Tag V5.6.0_cm4 | Tag v1.0.0
-Tag v1.1.0 | Tag v1.1.0 | Tag V5.6.0_cm4 | Tag v1.1.0
-Tag v1.2.0 | Tag v1.1.1 | Tag V5.6.0_cm4 | Tag v1.2.0 (and following, if any, till next tag)
-
+It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeWL/blob/main/Release_Notes.html) release note.
The full **STM32CubeWL** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWL).
diff --git a/Release_Notes.html b/Release_Notes.html
index 4b7da10..d0cf121 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -40,16 +40,155 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.2.0 / 4-February-2022</strong></label>
+<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 09-November-2022</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
+<li>Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (DAC, IRDA, LPTIM, SMARTCARD, TIM, UART, USART)</li>
+<li>Enhance code quality (MISRA-C rules 8.13, 11.9) for some drivers: ADC, COMP, DMA, IRDA, LPTIM, SMARTCARD, TIM, UART, USART</li>
+</ul>
+<h2 id="contents">Contents</h2>
+<h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3>
+<ul>
+<li><strong>HAL ADC</strong> driver
+<ul>
+<li>Disable AutoPowerOff when performing calibration</li>
+<li>Rename ADC_TRx registers to AWDxTR to be in accordance with the Reference Manual</li>
+</ul></li>
+<li><strong>HAL CORTEX</strong> driver
+<ul>
+<li>Remove #define LL_MPU_TEX_LEVEL4 (no Level 2 cache for STM32 SoC with Armv7-M cortex)</li>
+</ul></li>
+<li><strong>HAL CRC</strong> driver
+<ul>
+<li>Add filter in HAL_CRCEx_Polynomial_Set() function to exclude even polynomials</li>
+</ul></li>
+<li><strong>HAL CRYP</strong> driver
+<ul>
+<li>Add interleaved mode</li>
+</ul></li>
+<li><strong>HAL DAC</strong> driver
+<ul>
+<li>Fix HAL_GetTick() timeout vulnerability</li>
+<li>Return HAL_ERROR if configuration is not available on device</li>
+</ul></li>
+<li><strong>HAL EXTI</strong> driver
+<ul>
+<li>Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine()</li>
+</ul></li>
+<li><strong>HAL Generic</strong> driver
+<ul>
+<li>Add HAL_RADIO APIs to handle Radio services (only for STM32WL5M)</li>
+</ul></li>
+<li><strong>HAL I2C</strong> driver
+<ul>
+<li>Fix Timeout issue using HAL MEM interface through FreeRTOS</li>
+<li>Fix I2C_IsErrorOccurred returning error if timeout is detected</li>
+<li>Fix ADDRF flag cleared too early when the restart is received but the direction has changed</li>
+</ul></li>
+<li><strong>HAL IRDA</strong> driver
+<ul>
+<li>Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig()</li>
+</ul></li>
+<li><strong>HAL LPTIM</strong> driver
+<ul>
+<li>Enhance LPTIM state management</li>
+<li>Fix IS_LPTIM_AUTORELOAD & IS_LPTIM_PERIOD macros to check that AutoReload value must be strictly greater than 0</li>
+</ul></li>
+<li><strong>HAL RCC</strong> driver
+<ul>
+<li>Optimize HAL_RCC_OscConfig function when checking if oscillator is ready</li>
+<li>Optimize HAL_RCC_GetOscConfig function</li>
+<li>Remove GPIO configuration in HAL_RCCEx_EnableLSCO & HAL_RCCEx_DisableLSCO functions</li>
+</ul></li>
+<li><strong>HAL RTC</strong> driver
+<ul>
+<li>Improve HAL_RTC_Init function to avoid initialization if already done</li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong> driver
+<ul>
+<li>Fix wrong cast when computing the USARTDIV value in SMARTCARD_SetConfig() function</li>
+</ul></li>
+<li><strong>HAL SUBGHZ</strong> driver
+<ul>
+<li>Clear the interrupt CR register just after having read it</li>
+<li>Support new feature LoraFHSS (Lora Frequency Hopping Spread Spectrum)</li>
+<li>Add new state HAL_SUBGHZ_STATE_RESET_RF_READY to avoid to reinitialize RF on existing from Standby mode</li>
+</ul></li>
+<li><strong>HAL TIM</strong> driver
+<ul>
+<li>Improve driver robustness against wrong period values</li>
+<li>Improve driver robustness against wrong DMA related parameters</li>
+<li>Add new __HAL_TIM_SELECT_CCDMAREQUEST() macro to select CCx DMA source</li>
+</ul></li>
+<li><strong>HAL UART</strong> driver
+<ul>
+<li>Fix wrong cast when computing the USARTDIV value in UART_SetConfig() function</li>
+<li>Add HAL_UARTEx_GetRxEventType function to retrieve the type of event that has led the RxEventCallback execution</li>
+<li>Remove HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs to fix a concurrent access issue</li>
+<li>Disable the Receiver Timeout Interrupt when data reception is completed</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<ul>
+<li><strong>LL LPTIM</strong> driver
+<ul>
+<li>Enhance code quality by renaming all functions LL_LPTIM_ClearFLAG_Xxxxx with LL_LPTIM_ClearFlag_Xxxxx</li>
+</ul></li>
+<li><strong>LL System</strong> driver
+<ul>
+<li>Fix LL_SYSCFG_GetEXTISource function which returned wrong result on M4 core</li>
+</ul></li>
+<li><strong>LL USART</strong> driver
+<ul>
+<li>Fix compilation warnings generated with ARMV6 compiler</li>
+</ul></li>
+<li><strong>LL Utils</strong> driver
+<ul>
+<li>Fix a wrong parameter of __LL_RCC_CALC_MSI_FREQ given erroneous PLL frequency</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h2 id="known-limitations">Known Limitations</h2>
+<p>None</p>
+<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1 + <a href="./../../Utilities/PC_Software/EWARMv8_STM32WLxx_V4.9_Signed.zip">Patch EWARM</a></li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.36 + <a href="./../../Utilities/PC_Software/Keil.STM32WLxx_DFP.1.1.1.zip">Keil DFP V1.1.1 Pack</a></li>
+<li>STM32CubeIDE 1.11.0 (GNU Tools for STM32 10.3-2021.10)</li>
+</ul>
+<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<p>Supported Devices:</p>
+<ul>
+<li>STM32WL55xx</li>
+<li>STM32WL54xx</li>
+<li>STM32WLE5xx</li>
+<li>STM32WLE4xx</li>
+<li>STM32WL5Mxx</li>
+</ul>
+<h2 id="backward-compatibility">Backward Compatibility</h2>
+<p>Not applicable</p>
+<h2 id="dependencies">Dependencies</h2>
+<p>None</p>
+<p><br />
+</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 4-February-2022</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
<li>All source files: update disclaimer to add reference to the new license agreement</li>
<li>Correct English spelling errors and typos</li>
</ul>
-<h2 id="contents">Contents</h2>
-<h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-1">Contents</h2>
+<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL ADC</strong> driver
<ul>
@@ -113,7 +252,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL ADC</strong> driver
<ul>
@@ -146,15 +285,15 @@
</li>
</ul></li>
</ul>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-1">Known Limitations</h2>
<p>None</p>
-<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31</li>
<li>STM32CubeIDE 1.9.0 (native GNU ARM 10.3-2021-10 or optional GNU ARM 9-2020-q2-update)</li>
</ul>
-<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
<li>STM32WL55xx</li>
@@ -162,9 +301,9 @@
<li>STM32WLE5xx</li>
<li>STM32WLE4xx</li>
</ul>
-<h2 id="backward-compatibility">Backward Compatibility</h2>
+<h2 id="backward-compatibility-1">Backward Compatibility</h2>
<p>Not applicable</p>
-<h2 id="dependencies">Dependencies</h2>
+<h2 id="dependencies-1">Dependencies</h2>
<p>None</p>
<p><br />
</p>
@@ -173,7 +312,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 16-June-2021</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
<li>Update of HAL SMBUS driver to introduce fast mode and fast mode plus
@@ -185,8 +324,8 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="contents-1">Contents</h2>
-<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-2">Contents</h2>
+<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL ADC</strong> driver
<ul>
@@ -309,7 +448,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL RCC</strong> driver
<ul>
@@ -342,44 +481,13 @@
</ul>
<p><br />
</p>
-<h2 id="known-limitations-1">Known Limitations</h2>
-<p>None</p>
-<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
-<ul>
-<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1</li>
-<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31</li>
-<li>STM32CubeIDE 1.7.0</li>
-</ul>
-<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
-<p>Supported Devices:</p>
-<ul>
-<li>STM32WL55xx</li>
-<li>STM32WL54xx</li>
-<li>STM32WLE5xx</li>
-<li>STM32WLE4xx</li>
-</ul>
-<h2 id="backward-compatibility-1">Backward Compatibility</h2>
-<p>Not applicable</p>
-<h2 id="dependencies-1">Dependencies</h2>
-<p>None</p>
-<p><br />
-</p>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 28-October-2020</strong></label>
-<div>
-<h2 id="main-changes-2">Main Changes</h2>
-<p><strong>First Official Release</strong></p>
-<h2 id="contents-2">Contents</h2>
-<p>First official release of LL / HAL Drivers for STM32WLxx series.</p>
<h2 id="known-limitations-2">Known Limitations</h2>
<p>None</p>
<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1</li>
-<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.28</li>
-<li>STM32CubeIDE 1.5.0</li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31</li>
+<li>STM32CubeIDE 1.7.0</li>
</ul>
<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
<p>Supported Devices:</p>
@@ -397,6 +505,37 @@
</p>
</div>
</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 28-October-2020</strong></label>
+<div>
+<h2 id="main-changes-3">Main Changes</h2>
+<p><strong>First Official Release</strong></p>
+<h2 id="contents-3">Contents</h2>
+<p>First official release of LL / HAL Drivers for STM32WLxx series.</p>
+<h2 id="known-limitations-3">Known Limitations</h2>
+<p>None</p>
+<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1</li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.28</li>
+<li>STM32CubeIDE 1.5.0</li>
+</ul>
+<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2>
+<p>Supported Devices:</p>
+<ul>
+<li>STM32WL55xx</li>
+<li>STM32WL54xx</li>
+<li>STM32WLE5xx</li>
+<li>STM32WLE4xx</li>
+</ul>
+<h2 id="backward-compatibility-3">Backward Compatibility</h2>
+<p>Not applicable</p>
+<h2 id="dependencies-3">Dependencies</h2>
+<p>None</p>
+<p><br />
+</p>
+</div>
+</div>
</div>
</div>
<footer class="sticky">
diff --git a/Src/stm32wlxx_hal.c b/Src/stm32wlxx_hal.c
index 31e7dde..bb438f4 100644
--- a/Src/stm32wlxx_hal.c
+++ b/Src/stm32wlxx_hal.c
@@ -53,19 +53,30 @@
* @{
*/
/**
- * @brief STM32WLxx HAL Driver version number
- */
+ * @brief STM32WLxx HAL Driver version number
+ */
#define __STM32WLxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32WLxx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
+#define __STM32WLxx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32WLxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WLxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WLxx_HAL_VERSION ((__STM32WLxx_HAL_VERSION_MAIN << 24U)\
- |(__STM32WLxx_HAL_VERSION_SUB1 << 16U)\
- |(__STM32WLxx_HAL_VERSION_SUB2 << 8U )\
- |(__STM32WLxx_HAL_VERSION_RC))
+ |(__STM32WLxx_HAL_VERSION_SUB1 << 16U)\
+ |(__STM32WLxx_HAL_VERSION_SUB2 << 8U )\
+ |(__STM32WLxx_HAL_VERSION_RC))
#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */
+#if defined(STM32WL5Mxx)
+#define RADIO_SWITCH_CTRL_GPIO_PORT GPIOC
+#define RADIO_SWITCH_CTRL_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
+#define RADIO_SWITCH_CTRL_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
+
+#define RADIO_SWITCH_CTRL3_PIN GPIO_PIN_3
+#define RADIO_SWITCH_CTRL1_PIN GPIO_PIN_4
+#define RADIO_SWITCH_CTRL2_PIN GPIO_PIN_5
+
+#endif /* STM32WL5Mxx */
+
/**
* @}
*/
@@ -90,8 +101,8 @@
*/
/** @addtogroup HAL_Exported_Functions_Group1
- * @brief HAL Initialization and Configuration functions
- *
+ * @brief HAL Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### HAL Initialization and Configuration functions #####
@@ -304,8 +315,8 @@
*/
/** @addtogroup HAL_Exported_Functions_Group2
- * @brief HAL Control functions
- *
+ * @brief HAL Control functions
+ *
@verbatim
===============================================================================
##### HAL Control functions #####
@@ -329,7 +340,7 @@
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in SysTick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
+ * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
@@ -520,8 +531,8 @@
*/
/** @addtogroup HAL_Exported_Functions_Group3
- * @brief HAL Debug functions
- *
+ * @brief HAL Debug functions
+ *
@verbatim
===============================================================================
##### HAL Debug functions #####
@@ -601,8 +612,8 @@
*/
/** @defgroup HAL_Exported_Functions_Group4 HAL System Configuration functions
- * @brief HAL System Configuration functions
- *
+ * @brief HAL System Configuration functions
+ *
@verbatim
===============================================================================
##### HAL system configuration functions #####
@@ -649,17 +660,17 @@
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
-
+
LL_VREFBUF_SetVoltageScaling(VoltageScaling);
-
+
/* Restrieve Calibration data and store them into trimming field */
if (VoltageScaling == SYSCFG_VREFBUF_VOLTAGE_SCALE0)
{
- TrimmingValue = ((uint32_t) *VREFBUF_SC0_CAL_ADDR) & 0x3FU;
+ TrimmingValue = ((uint32_t) * VREFBUF_SC0_CAL_ADDR) & 0x3FU;
}
else
{
- TrimmingValue = ((uint32_t) *VREFBUF_SC1_CAL_ADDR) & 0x3FU;
+ TrimmingValue = ((uint32_t) * VREFBUF_SC1_CAL_ADDR) & 0x3FU;
}
assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
@@ -687,7 +698,7 @@
* @brief Tune the Internal Voltage Reference buffer (VREFBUF).
* @note Each VrefBuf voltage scale is calibrated in production for each device,
* data stored in flash memory.
- * Function @ref HAL_SYSCFG_VREFBUF_VoltageScalingConfig retrieves and
+ * Function @ref HAL_SYSCFG_VREFBUF_VoltageScalingConfig retrieves and
* applies this calibration data as trimming value at each scale change.
* Therefore, optionally, function @ref HAL_SYSCFG_VREFBUF_TrimmingConfig
* can be used in a second time to fine tune the trimming.
@@ -816,6 +827,181 @@
* @}
*/
+#if defined(STM32WL5Mxx)
+/** @defgroup HAL_Exported_Functions_Group5 HAL Radio Configuration functions
+ * @brief HAL Radio Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Radio configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Enable/Disable the Radio
+ (+) Configure the Radio to Rx, Tx Low Power or Tx High Power
+
+@endverbatim
+ * @{
+ */
+
+/* RADIO Control functions ****************************************************/
+/**
+ * @brief Init Radio Switch
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RADIO_Init(void)
+{
+ HAL_StatusTypeDef status;
+ GPIO_InitTypeDef gpio_init_structure;
+
+ /* Enable the Radio Switch Clock */
+ RADIO_SWITCH_CTRL_GPIO_CLK_ENABLE();
+
+ /* Configure the Radio Switch pin */
+ gpio_init_structure.Pin = (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN);
+ gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
+ gpio_init_structure.Pull = GPIO_NOPULL;
+ gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+
+ HAL_GPIO_Init(RADIO_SWITCH_CTRL_GPIO_PORT, &gpio_init_structure);
+
+ /* Lock RF Switch GPIOs configuration to avoid any user change */
+ /* Only a MCU reset will unlock this configuration */
+ status = HAL_GPIO_LockPin(RADIO_SWITCH_CTRL_GPIO_PORT, (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN));
+ if (status == HAL_OK)
+ {
+ /* By default, the RF Switch is off */
+ HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT,
+ (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_RESET);
+ }
+
+ return status;
+}
+
+/**
+ * @brief DeInit Radio Switch
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RADIO_DeInit(void)
+{
+ /* Enable the Radio Switch Clock */
+ RADIO_SWITCH_CTRL_GPIO_CLK_ENABLE();
+
+ /* Turn off switch */
+ HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT,
+ (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_RESET);
+
+ /* Disable the Radio Switch Clock */
+ RADIO_SWITCH_CTRL_GPIO_CLK_DISABLE();
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure Radio Switch.
+ * @param Config: Specifies the Radio RF switch path to be set.
+ * This parameter can be one of following parameters:
+ * @arg RADIO_SWITCH_OFF
+ * @arg RADIO_SWITCH_RX
+ * @arg RADIO_SWITCH_RFO_LP
+ * @arg RADIO_SWITCH_RFO_HP
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RADIO_SetSwitchConfig(HAL_RADIO_SwitchConfig_TypeDef Config)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (Config)
+ {
+ case RADIO_SWITCH_OFF:
+ {
+ /* Turn off switch */
+ HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT,
+ (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_RESET);
+ break;
+ }
+ case RADIO_SWITCH_RX:
+ {
+ /* Turns On in Rx Mode the RF Switch */
+ HAL_GPIO_WritePin(RADIO_SWITCH_CTRL_GPIO_PORT,
+ (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN), GPIO_PIN_SET);
+
+ break;
+ }
+ case RADIO_SWITCH_RFO_LP:
+ {
+ /* Turns On in Tx Low Power the RF Switch */
+ HAL_GPIO_WriteMultipleStatePin(RADIO_SWITCH_CTRL_GPIO_PORT, RADIO_SWITCH_CTRL2_PIN,
+ (RADIO_SWITCH_CTRL1_PIN | RADIO_SWITCH_CTRL3_PIN));
+ break;
+ }
+ case RADIO_SWITCH_RFO_HP:
+ {
+ /* Turns On in Tx High Power the RF Switch */
+ HAL_GPIO_WriteMultipleStatePin(RADIO_SWITCH_CTRL_GPIO_PORT, RADIO_SWITCH_CTRL1_PIN,
+ (RADIO_SWITCH_CTRL2_PIN | RADIO_SWITCH_CTRL3_PIN));
+ break;
+ }
+ default:
+ {
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Get If TCXO is to be present on board
+ * @note never remove called by MW,
+ * @retval
+ * RADIO_CONF_TCXO_NOT_SUPPORTED
+ * RADIO_CONF_TCXO_SUPPORTED
+ */
+uint8_t HAL_RADIO_IsTCXO(void)
+{
+ return RADIO_CONF_TCXO_SUPPORTED;
+}
+
+/**
+ * @brief Get If DCDC is to be present on board
+ * @note never remove called by MW,
+ * @retval
+ * RADIO_CONF_DCDC_NOT_SUPPORTED
+ * RADIO_CONF_DCDC_SUPPORTED
+ */
+uint8_t HAL_RADIO_IsDCDC(void)
+{
+ return RADIO_CONF_DCDC_SUPPORTED;
+}
+
+/**
+ * @brief Return RF Output Max Power Configuration
+ * @retval
+ * RADIO_CONF_RFO_LP_MAX_15_dBm for LP mode
+ * RADIO_CONF_RFO_HP_MAX_22_dBm for HP mode
+ */
+int32_t HAL_RADIO_GetRFOMaxPowerConfig(HAL_RADIO_RFOMaxPowerConfig_TypeDef Config)
+{
+ int32_t ret;
+
+ if (Config == RADIO_RFO_LP_MAXPOWER)
+ {
+ ret = RADIO_CONF_RFO_LP_MAX_15_dBm;
+ }
+ else
+ {
+ ret = RADIO_CONF_RFO_HP_MAX_22_dBm;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32WL5Mxx */
+
/**
* @}
*/
diff --git a/Src/stm32wlxx_hal_adc.c b/Src/stm32wlxx_hal_adc.c
index 6a07dcd..03068bd 100644
--- a/Src/stm32wlxx_hal_adc.c
+++ b/Src/stm32wlxx_hal_adc.c
@@ -656,44 +656,20 @@
}
else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
{
- /* Count number of ranks available in HAL ADC handle variable */
- uint32_t ADCGroupRegularSequencerRanksCount;
-
- /* Parse all ranks from 1 to 8 */
- for (ADCGroupRegularSequencerRanksCount = 0UL; ADCGroupRegularSequencerRanksCount < (8UL); ADCGroupRegularSequencerRanksCount++)
- {
- /* Check each sequencer rank until value of end of sequence */
- if (((hadc->ADCGroupRegularSequencerRanks >> (ADCGroupRegularSequencerRanksCount * 4UL)) & ADC_CHSELR_SQ1) ==
- ADC_CHSELR_SQ1)
- {
- break;
- }
- }
-
- if (ADCGroupRegularSequencerRanksCount == 1UL)
- {
- /* Set ADC group regular sequencer: */
- /* Set sequencer scan length by clearing ranks above rank 1 */
- /* and do not modify rank 1 value. */
- SET_BIT(hadc->Instance->CHSELR,
- ADC_CHSELR_SQ2_TO_SQ8);
- }
- else
- {
- /* Set ADC group regular sequencer: */
- /* - Set ADC group regular sequencer to value memorized */
- /* in HAL ADC handle */
- /* Note: This value maybe be initialized at a unknown value, */
- /* therefore after the first call of "HAL_ADC_Init()", */
- /* each rank corresponding to parameter "NbrOfConversion" */
- /* must be set using "HAL_ADC_ConfigChannel()". */
- /* - Set sequencer scan length by clearing ranks above maximum rank */
- /* and do not modify other ranks value. */
- MODIFY_REG(hadc->Instance->CHSELR,
- ADC_CHSELR_SQ_ALL,
- (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) | (hadc->ADCGroupRegularSequencerRanks)
- );
- }
+ /* Set ADC group regular sequencer: */
+ /* - Set ADC group regular sequencer to value memorized */
+ /* in HAL ADC handle */
+ /* Note: This value maybe be initialized at a unknown value, */
+ /* therefore after the first call of "HAL_ADC_Init()", */
+ /* each rank corresponding to parameter "NbrOfConversion" */
+ /* must be set using "HAL_ADC_ConfigChannel()". */
+ /* - Set sequencer scan length by clearing ranks above maximum rank */
+ /* and do not modify other ranks value. */
+ MODIFY_REG(hadc->Instance->CHSELR,
+ ADC_CHSELR_SQ_ALL,
+ (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL))
+ | (hadc->ADCGroupRegularSequencerRanks)
+ );
}
/* Check back that ADC registers have effectively been configured to */
@@ -822,8 +798,10 @@
/* Reset register SMPR */
hadc->Instance->SMPR &= ~ADC_SMPR_SMP1;
- /* Reset register TR1 */
- hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1);
+ /* Reset registers AWDxTR */
+ hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1);
+ hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2);
+ hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3);
/* Reset register CHSELR */
hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
@@ -1392,9 +1370,12 @@
* @param EventType the ADC event type.
* This parameter can be one of the following values:
* @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
- * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
- * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
- * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
+ * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all
+ * STM32 series)
+ * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all
+ * STM32 series)
+ * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all
+ * STM32 series)
* @arg @ref ADC_OVR_EVENT ADC Overrun event
* @param Timeout Timeout value in millisecond.
* @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
@@ -2282,7 +2263,8 @@
wait_loop_index--;
}
}
- else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
@@ -2442,7 +2424,8 @@
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
- __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR));
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+ LL_ADC_GROUP_REGULAR));
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
@@ -2500,7 +2483,9 @@
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
- LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG);
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
+ pAnalogWDGConfig->WatchdogNumber,
+ LL_ADC_AWD_ALL_CHANNELS_REG);
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
@@ -2736,14 +2721,16 @@
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
- if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
+ if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ != 0UL)
{
/* Delay for temperature sensor buffer stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL)
+ * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
diff --git a/Src/stm32wlxx_hal_adc_ex.c b/Src/stm32wlxx_hal_adc_ex.c
index fd77ac5..86332a7 100644
--- a/Src/stm32wlxx_hal_adc_ex.c
+++ b/Src/stm32wlxx_hal_adc_ex.c
@@ -125,9 +125,9 @@
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
- /* Manage settings impacting calibration */
- /* - Disable ADC mode auto power-off */
- /* - Disable ADC DMA transfer request during calibration */
+ /* Manage settings impacting calibration */
+ /* - Disable ADC mode auto power-off */
+ /* - Disable ADC DMA transfer request during calibration */
/* Note: Specificity of this STM32 series: Calibration factor is */
/* available in data register and also transferred by DMA. */
/* To not insert ADC calibration factor among ADC conversion data */
diff --git a/Src/stm32wlxx_hal_comp.c b/Src/stm32wlxx_hal_comp.c
index 33596fc..c5b40c6 100644
--- a/Src/stm32wlxx_hal_comp.c
+++ b/Src/stm32wlxx_hal_comp.c
@@ -914,7 +914,7 @@
* @arg COMP_OUTPUT_LEVEL_HIGH
*
*/
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
+uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp)
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
@@ -962,7 +962,7 @@
* @param hcomp COMP handle
* @retval HAL state
*/
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
+HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp)
{
/* Check the COMP handle allocation */
if(hcomp == NULL)
@@ -982,7 +982,7 @@
* @param hcomp COMP handle
* @retval COMP error code
*/
-uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
+uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
diff --git a/Src/stm32wlxx_hal_crc_ex.c b/Src/stm32wlxx_hal_crc_ex.c
index 2414a2f..cc543d7 100644
--- a/Src/stm32wlxx_hal_crc_ex.c
+++ b/Src/stm32wlxx_hal_crc_ex.c
@@ -94,44 +94,53 @@
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
- /* check polynomial definition vs polynomial size:
- * polynomial length must be aligned with polynomial
- * definition. HAL_ERROR is reported if Pol degree is
- * larger than that indicated by PolyLength.
- * Look for MSB position: msb will contain the degree of
- * the second to the largest polynomial member. E.g., for
- * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
- while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+ /* Ensure that the generating polynomial is odd */
+ if ((Pol & (uint32_t)(0x1U)) == 0U)
{
+ status = HAL_ERROR;
}
-
- switch (PolyLength)
+ else
{
- case CRC_POLYLENGTH_7B:
- if (msb >= HAL_CRC_LENGTH_7B)
- {
- status = HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_8B:
- if (msb >= HAL_CRC_LENGTH_8B)
- {
- status = HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_16B:
- if (msb >= HAL_CRC_LENGTH_16B)
- {
- status = HAL_ERROR;
- }
- break;
+ /* check polynomial definition vs polynomial size:
+ * polynomial length must be aligned with polynomial
+ * definition. HAL_ERROR is reported if Pol degree is
+ * larger than that indicated by PolyLength.
+ * Look for MSB position: msb will contain the degree of
+ * the second to the largest polynomial member. E.g., for
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+ {
+ }
- case CRC_POLYLENGTH_32B:
- /* no polynomial definition vs. polynomial length issue possible */
- break;
- default:
- status = HAL_ERROR;
- break;
+ switch (PolyLength)
+ {
+
+ case CRC_POLYLENGTH_7B:
+ if (msb >= HAL_CRC_LENGTH_7B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_8B:
+ if (msb >= HAL_CRC_LENGTH_8B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_16B:
+ if (msb >= HAL_CRC_LENGTH_16B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ case CRC_POLYLENGTH_32B:
+ /* no polynomial definition vs. polynomial length issue possible */
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
}
if (status == HAL_OK)
{
diff --git a/Src/stm32wlxx_hal_cryp.c b/Src/stm32wlxx_hal_cryp.c
index 6585d84..42e2cff 100644
--- a/Src/stm32wlxx_hal_cryp.c
+++ b/Src/stm32wlxx_hal_cryp.c
@@ -432,6 +432,8 @@
ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
(+++) for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
(+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
+ (+) For interleave mode, API HAL_CRYP_SaveContext and HAL_CRYP_RestoreContext to be used to save then Restore CRYP
+ configuration and parameters. CRYP_IVCONFIG_ONCE should be selected for KeyIVConfigSkip parameter.
@endverbatim
* @{
@@ -1083,6 +1085,111 @@
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
/**
+ * @brief CRYP peripheral parameters storage when processing Interleaved mode .
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pcont pointer to a CRYP_ContextTypeDef structure where CRYP parameters will be stored.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_SaveContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont)
+{
+ /* Check the CRYP handle allocation */
+ if ((hcryp == NULL) || (pcont == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Save CRYP handle parameters */
+ pcont->DataType = (uint32_t)(hcryp->Init.DataType);
+ pcont->KeySize = (uint32_t)(hcryp->Init.KeySize);
+ pcont->pKey = hcryp->Init.pKey;
+ pcont->pInitVect = hcryp->Init.pInitVect;
+ pcont->Algorithm = (uint32_t)(hcryp->Init.Algorithm);
+ pcont->DataWidthUnit = (uint32_t)(hcryp->Init.DataWidthUnit);
+ pcont->KeyIVConfigSkip = (uint32_t)(hcryp->Init.KeyIVConfigSkip);
+ pcont->Phase = (uint32_t)(hcryp->Phase);
+ pcont->KeyIVConfig = (uint32_t)(hcryp->KeyIVConfig);
+
+ /* Save CRYP CR register content */
+ pcont->CR_Reg = READ_REG(hcryp->Instance->CR);
+
+ if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
+ (hcryp->Init.Algorithm == CRYP_AES_CTR))
+ {
+ /* Save Initialisation Vector registers */
+ pcont->IVR0_Reg = READ_REG(hcryp->Instance->IVR0);
+ pcont->IVR1_Reg = READ_REG(hcryp->Instance->IVR1);
+ pcont->IVR2_Reg = READ_REG(hcryp->Instance->IVR2);
+ pcont->IVR3_Reg = READ_REG(hcryp->Instance->IVR3);
+ }
+
+ /* To load Key for next piece of message */
+ hcryp->KeyIVConfig = 0;
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+
+}
+
+/**
+ * @brief Restore CRYP parameters needed for Interleaved mode.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pcont pointer to a CRYP_ContextTypeDef structure that contains CRYP parameters stored.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont)
+{
+ /* Check the CRYP handle allocation */
+ if ((hcryp == NULL) || (pcont == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Restore CRYP handle parameters */
+ hcryp->Init.DataType = pcont->DataType;
+ hcryp->Init.KeySize = pcont->KeySize;
+ hcryp->Init.pKey = pcont->pKey;
+ hcryp->Init.pInitVect = pcont->pInitVect;
+ hcryp->Init.Algorithm = pcont->Algorithm;
+ hcryp->Init.DataWidthUnit = pcont->DataWidthUnit;
+ hcryp->Init.KeyIVConfigSkip = pcont->KeyIVConfigSkip;
+ hcryp->Phase = pcont->Phase;
+ hcryp->KeyIVConfig = pcont->KeyIVConfig;
+
+ /* Restore CRYP CR register content */
+ WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg));
+
+ if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
+ (hcryp->Init.Algorithm == CRYP_AES_CTR))
+ {
+ /* Restore Initialisation Vector registers */
+ WRITE_REG(hcryp->Instance->IVR0, (uint32_t)(pcont->IVR0_Reg));
+ WRITE_REG(hcryp->Instance->IVR1, (uint32_t)(pcont->IVR1_Reg));
+ WRITE_REG(hcryp->Instance->IVR2, (uint32_t)(pcont->IVR2_Reg));
+ WRITE_REG(hcryp->Instance->IVR3, (uint32_t)(pcont->IVR3_Reg));
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
* @}
*/
@@ -1994,7 +2101,7 @@
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
- if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)|| (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE))
{
if (hcryp->KeyIVConfig == 1U)
{
@@ -2025,7 +2132,15 @@
hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
}
} /* if (DoKeyIVConfig == 1U) */
-
+ else
+ {
+ /* interleave mode Key configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)
+ {
+ /* Set the Key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ }
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -2141,7 +2256,7 @@
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
- if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE))
{
if (hcryp->KeyIVConfig == 1U)
{
@@ -2219,7 +2334,62 @@
hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
}
} /* if (DoKeyIVConfig == 1U) */
-
+ else /* if (dokeyivconfig == 0U) */
+ {
+ /* interleave mode Key configuration */
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)
+ {
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
+ {
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
+ {
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state & error code*/
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & Key preparation*/
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set decryption & Key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+ }
+ else /*Algorithm CTR */
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+ }
+ }
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
diff --git a/Src/stm32wlxx_hal_dac.c b/Src/stm32wlxx_hal_dac.c
index 497e809..8f489dc 100644
--- a/Src/stm32wlxx_hal_dac.c
+++ b/Src/stm32wlxx_hal_dac.c
@@ -10,6 +10,7 @@
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
+ *
******************************************************************************
* @attention
*
@@ -63,13 +64,6 @@
(@) Refer to the device datasheet for more details about output
impedance value with and without output buffer.
- *** DAC connect feature ***
- ===============================
- [..]
- Each DAC channel can be connected internally.
- To connect, use
- sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
-
*** GPIO configurations guidelines ***
=====================
[..]
@@ -152,7 +146,7 @@
DAC_OUTx = VREF+ * DOR / 4095
(+) with DOR is the Data Output Register
[..]
- VEF+ is the input voltage reference (refer to the device datasheet)
+ VREF+ is the input voltage reference (refer to the device datasheet)
[..]
e.g. To set DAC_OUT1 to 0.7V, use
(+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
@@ -219,7 +213,7 @@
The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions HAL_DAC_RegisterCallback() to register a user callback,
+ Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
@@ -230,7 +224,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
+ Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
@@ -241,12 +235,12 @@
(+) All Callbacks
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
+ By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
- and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
+ and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -254,8 +248,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
- or HAL_DAC_Init function.
+ using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
+ or @ref HAL_DAC_Init function.
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -275,6 +269,7 @@
(@) You can refer to the DAC HAL driver header file for more useful macros
@endverbatim
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -353,8 +348,6 @@
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
-
-
if (hdac->MspInitCallback == NULL)
{
hdac->MspInitCallback = HAL_DAC_MspInit;
@@ -556,7 +549,7 @@
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @param pData The destination peripheral Buffer address.
+ * @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to DAC peripheral
* @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
@@ -565,7 +558,7 @@
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment)
{
HAL_StatusTypeDef status;
@@ -606,16 +599,13 @@
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
break;
- case DAC_ALIGN_8B_R:
+ default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
break;
- default:
- break;
}
}
- /* Enable the DMA channel */
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
@@ -650,8 +640,6 @@
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
- HAL_StatusTypeDef status;
-
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -664,25 +652,16 @@
/* Disable the DMA channel */
/* Disable the DMA channel */
- status = HAL_DMA_Abort(hdac->DMA_Handle1);
+ (void)HAL_DMA_Abort(hdac->DMA_Handle1);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
- /* Check if DMA Channel effectively disabled */
- if (status != HAL_OK)
- {
- /* Update DAC state machine to error */
- hdac->State = HAL_DAC_STATE_ERROR;
- }
- else
- {
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
- }
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -695,22 +674,25 @@
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
{
- if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+ uint32_t itsource = hdac->Instance->CR;
+ uint32_t itflag = hdac->Instance->SR;
+
+ if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
{
/* Check underrun flag of DAC channel 1 */
- if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
- /* Set DAC error code to chanel1 DMA underrun error */
+ /* Set DAC error code to channel1 DMA underrun error */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
/* Disable the selected DAC channel1 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -739,7 +721,7 @@
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
- __IO uint32_t tmp = 0;
+ __IO uint32_t tmp = 0UL;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -851,13 +833,17 @@
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @retval The selected DAC channel data output value.
*/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
+uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
{
+ uint32_t result;
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
+ result = hdac->Instance->DOR1;
+
/* Returns the DAC channel data output register value */
- return hdac->Instance->DOR1;
+ return result;
}
/**
@@ -870,8 +856,10 @@
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
+ const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpreg1;
uint32_t tmpreg2;
uint32_t tickstart;
@@ -900,10 +888,9 @@
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
+ /* Sample and hold configuration */
if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
- /* Sample on old configuration */
{
- /* SampleTime */
/* Get timeout */
tickstart = HAL_GetTick();
@@ -913,22 +900,27 @@
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
- /* Update error code */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
+ /* New check to avoid false timeout detection in case of preemption */
+ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
+ {
+ /* Update error code */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
- /* Change the DMA state */
- hdac->State = HAL_DAC_STATE_TIMEOUT;
+ /* Change the DMA state */
+ hdac->State = HAL_DAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
- HAL_Delay(1);
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
/* HoldTime */
- MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
+ (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
/* RefreshTime */
- MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
+ (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
}
if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
@@ -974,7 +966,7 @@
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
/* Disable wave generation */
- hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL));
+ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -983,7 +975,7 @@
__HAL_UNLOCK(hdac);
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1012,7 +1004,7 @@
* the configuration information for the specified DAC.
* @retval HAL state
*/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
+HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
{
/* Return DAC handle state */
return hdac->State;
@@ -1025,7 +1017,7 @@
* the configuration information for the specified DAC.
* @retval DAC Error Code
*/
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
{
return hdac->ErrorCode;
}
@@ -1049,6 +1041,8 @@
/**
* @brief Register a User DAC Callback
* To be used instead of the weak (surcharged) predefined callback
+ * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
+ * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1075,9 +1069,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hdac);
-
if (hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
@@ -1134,14 +1125,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hdac);
return status;
}
/**
* @brief Unregister a User DAC Callback
* DAC Callback is redirected to the weak (surcharged) predefined callback
+ * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
+ * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1158,9 +1149,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hdac);
-
if (hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
@@ -1225,8 +1213,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hdac);
return status;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
@@ -1312,7 +1298,6 @@
#endif /* DAC */
#endif /* HAL_DAC_MODULE_ENABLED */
-
/**
* @}
*/
diff --git a/Src/stm32wlxx_hal_dac_ex.c b/Src/stm32wlxx_hal_dac_ex.c
index 1b1406e..f5c872a 100644
--- a/Src/stm32wlxx_hal_dac_ex.c
+++ b/Src/stm32wlxx_hal_dac_ex.c
@@ -2,10 +2,11 @@
******************************************************************************
* @file stm32wlxx_hal_dac_ex.c
* @author MCD Application Team
- * @brief DAC HAL module driver.
+ * @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.
*
+ *
******************************************************************************
* @attention
*
@@ -22,15 +23,9 @@
##### How to use this driver #####
==============================================================================
[..]
- *** Dual mode IO operation ***
- ==============================
- (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
- Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
- HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
- Channel 1 and Channel 2.
-
*** Signal generation operation ***
===================================
+ [..]
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
@@ -41,6 +36,7 @@
at least one time after reset).
@endverbatim
+ ******************************************************************************
*/
@@ -62,6 +58,16 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+
+/* Delay for DAC minimum trimming time. */
+/* Note: minimum time needed between two calibration steps */
+/* The delay below is specified under conditions: */
+/* - DAC channel output buffer enabled */
+/* Literal set to maximum value (refer to device datasheet, */
+/* electrical characteristics, parameter "tTRIM"). */
+/* Unit: us */
+#define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -126,7 +132,8 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the triangle wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+ (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -174,7 +181,8 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the noise wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+ (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -199,7 +207,6 @@
* @retval HAL status
* @note Calibration runs about 7 ms.
*/
-
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -207,6 +214,7 @@
__IO uint32_t tmp;
uint32_t trimmingvalue;
uint32_t delta;
+ __IO uint32_t wait_loop_index;
/* store/restore channel configuration structure purpose */
uint32_t oldmodeconfiguration;
@@ -261,9 +269,15 @@
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
- /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
- /* i.e. minimum time needed between two calibration steps */
- HAL_Delay(1);
+ /* Wait minimum time needed between two calibration steps (OTRIM) */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
+ /* 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while(wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
{
@@ -283,13 +297,19 @@
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
- /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
- /* i.e. minimum time needed between two calibration steps */
- HAL_Delay(1U);
+ /* Wait minimum time needed between two calibration steps (OTRIM) */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
+ /* 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while(wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
- /* OPAMP_CSR_OUTCAL is actually one value more */
+ /* Trimming is actually one value more */
trimmingvalue++;
/* Set right trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
@@ -323,7 +343,6 @@
* @param NewTrimmingValue DAC new trimming value
* @retval HAL status
*/
-
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue)
{
@@ -365,7 +384,7 @@
* @retval Trimming value : range: 0->31
*
*/
-uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
+uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameter */
assert_param(IS_DAC_CHANNEL(Channel));
diff --git a/Src/stm32wlxx_hal_dma.c b/Src/stm32wlxx_hal_dma.c
index 8fd1548..96b01d1 100644
--- a/Src/stm32wlxx_hal_dma.c
+++ b/Src/stm32wlxx_hal_dma.c
@@ -229,8 +229,8 @@
}
else
{
- hdma->DMAmuxRequestGen = 0U;
- hdma->DMAmuxRequestGenStatus = 0U;
+ hdma->DMAmuxRequestGen = NULL;
+ hdma->DMAmuxRequestGenStatus = NULL;
hdma->DMAmuxRequestGenStatusMask = 0U;
}
@@ -312,8 +312,8 @@
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
- hdma->DMAmuxRequestGen = 0U;
- hdma->DMAmuxRequestGenStatus = 0U;
+ hdma->DMAmuxRequestGen = NULL;
+ hdma->DMAmuxRequestGenStatus = NULL;
hdma->DMAmuxRequestGenStatusMask = 0U;
/* Clean callbacks */
@@ -460,7 +460,7 @@
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
- if (hdma->DMAmuxRequestGen != 0U)
+ if (hdma->DMAmuxRequestGen != NULL)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
@@ -526,7 +526,7 @@
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
- if (hdma->DMAmuxRequestGen != 0U)
+ if (hdma->DMAmuxRequestGen != NULL)
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
@@ -580,7 +580,7 @@
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
- if (hdma->DMAmuxRequestGen != 0U)
+ if (hdma->DMAmuxRequestGen != NULL)
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
@@ -688,7 +688,7 @@
}
/*Check for DMAMUX Request generator (if used) overrun status */
- if (hdma->DMAmuxRequestGen != 0U)
+ if (hdma->DMAmuxRequestGen != NULL)
{
/* if using DMAMUX request generator Check for DMAMUX request generator overrun */
if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
@@ -1211,7 +1211,7 @@
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
- if (hdma->DMAmuxRequestGen != 0U)
+ if (hdma->DMAmuxRequestGen != NULL)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
diff --git a/Src/stm32wlxx_hal_dma_ex.c b/Src/stm32wlxx_hal_dma_ex.c
index 13fe57c..b6c33ef 100644
--- a/Src/stm32wlxx_hal_dma_ex.c
+++ b/Src/stm32wlxx_hal_dma_ex.c
@@ -158,7 +158,7 @@
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
- if (hdma->DMAmuxRequestGen == 0U)
+ if (hdma->DMAmuxRequestGen == NULL)
{
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
diff --git a/Src/stm32wlxx_hal_exti.c b/Src/stm32wlxx_hal_exti.c
index 113283a..b5f69c2 100644
--- a/Src/stm32wlxx_hal_exti.c
+++ b/Src/stm32wlxx_hal_exti.c
@@ -107,8 +107,8 @@
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
-#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
-#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */
+#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
+#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */
/**
* @}
*/
@@ -123,8 +123,8 @@
*/
/** @addtogroup EXTI_Exported_Functions_Group1
- * @brief Configuration functions
- *
+ * @brief Configuration functions
+ *
@verbatim
===============================================================================
##### Configuration functions #####
@@ -223,7 +223,7 @@
regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
#else
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
-#endif
+#endif /* DUAL_CORE && CORE_CM0PLUS */
regval = *regaddr;
/* Mask or set line */
@@ -244,7 +244,7 @@
regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
#else
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
-#endif
+#endif /* DUAL_CORE && CORE_CM0PLUS */
regval = *regaddr;
/* Mask or set line */
@@ -289,7 +289,7 @@
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
- /* Store handle line number to configiguration structure */
+ /* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* compute line register offset and line mask */
@@ -302,7 +302,7 @@
regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
#else
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
-#endif
+#endif /* DUAL_CORE && CORE_CM0PLUS */
regval = *regaddr;
/* Check if selected line is enable */
@@ -320,7 +320,7 @@
regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
#else
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
-#endif
+#endif /* DUAL_CORE && CORE_CM0PLUS */
regval = *regaddr;
/* Check if selected line is enable */
@@ -359,7 +359,7 @@
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
regval = SYSCFG->EXTICR[linepos >> 2u];
- pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24u);
+ pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
}
}
@@ -399,7 +399,7 @@
regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
#else
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
-#endif
+#endif /* DUAL_CORE && CORE_CM0PLUS */
regval = (*regaddr & ~maskline);
*regaddr = regval;
@@ -408,7 +408,7 @@
regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
#else
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
-#endif
+#endif /* DUAL_CORE && CORE_CM0PLUS */
regval = (*regaddr & ~maskline);
*regaddr = regval;
@@ -495,8 +495,8 @@
*/
/** @addtogroup EXTI_Exported_Functions_Group2
- * @brief EXTI IO functions.
- *
+ * @brief EXTI IO functions.
+ *
@verbatim
===============================================================================
##### IO operation functions #####
diff --git a/Src/stm32wlxx_hal_i2c.c b/Src/stm32wlxx_hal_i2c.c
index a9a9aa1..8b698e2 100644
--- a/Src/stm32wlxx_hal_i2c.c
+++ b/Src/stm32wlxx_hal_i2c.c
@@ -438,10 +438,14 @@
/* Private functions for I2C transfer IRQ handler */
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
@@ -707,6 +711,8 @@
/**
* @brief Register a User I2C Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+ * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param CallbackID ID of the callback to be registered
@@ -737,8 +743,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
@@ -827,14 +831,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
/**
* @brief Unregister an I2C Callback
* I2C callback is redirected to the weak predefined callback
+ * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+ * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param CallbackID ID of the callback to be unregistered
@@ -857,9 +861,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hi2c);
-
if (HAL_I2C_STATE_READY == hi2c->State)
{
switch (CallbackID)
@@ -947,8 +948,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -971,8 +970,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
@@ -987,8 +984,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -1003,9 +998,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hi2c);
-
if (HAL_I2C_STATE_READY == hi2c->State)
{
hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
@@ -1019,8 +1011,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -2647,9 +2637,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
-
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2669,9 +2656,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2680,30 +2664,29 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
+ hi2c->XferISR = I2C_Mem_ISR_IT;
+ hi2c->Devaddress = DevAddress;
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
}
+ /* If Memory address size is 16Bit */
else
{
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
- != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2741,9 +2724,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
-
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2763,9 +2743,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2774,29 +2751,29 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
+ hi2c->XferISR = I2C_Mem_ISR_IT;
+ hi2c->Devaddress = DevAddress;
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
}
+ /* If Memory address size is 16Bit */
else
{
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2809,7 +2786,7 @@
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+ I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
return HAL_OK;
}
@@ -2833,8 +2810,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -2856,9 +2831,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2867,28 +2839,36 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
+ hi2c->XferISR = I2C_Mem_ISR_DMA;
+ hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
}
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
- != HAL_OK)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
if (hi2c->hdmatx != NULL)
{
@@ -2923,12 +2903,8 @@
if (dmaxferstatus == HAL_OK)
{
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Send Slave Address and Memory Address */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2936,11 +2912,11 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
else
{
@@ -2980,8 +2956,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -3003,9 +2977,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -3014,25 +2985,35 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
+ hi2c->XferISR = I2C_Mem_ISR_DMA;
+ hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
}
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
}
if (hi2c->hdmarx != NULL)
@@ -3068,11 +3049,8 @@
if (dmaxferstatus == HAL_OK)
{
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Send Slave Address and Memory Address */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3080,11 +3058,11 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
else
{
@@ -3327,6 +3305,10 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
@@ -3773,6 +3755,9 @@
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ FlagStatus tmp;
+
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3832,7 +3817,8 @@
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_IT;
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -3869,6 +3855,8 @@
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ FlagStatus tmp;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -4010,7 +3998,8 @@
return HAL_ERROR;
}
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4050,6 +4039,9 @@
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ FlagStatus tmp;
+
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -4109,7 +4101,8 @@
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_IT;
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4146,6 +4139,8 @@
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ FlagStatus tmp;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -4287,7 +4282,8 @@
return HAL_ERROR;
}
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4879,6 +4875,143 @@
}
/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint32_t direction = I2C_GENERATE_START_WRITE;
+ uint32_t tmpITFlags = ITFlags;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ /* Error callback will be send during stop flag treatment */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ {
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ if (hi2c->Memaddress == 0xFFFFFFFFU)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else
+ {
+ /* Write LSB part of Memory Address */
+ hi2c->Instance->TXDR = hi2c->Memaddress;
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ direction = I2C_GENERATE_START_READ;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, direction);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Set NBYTES to write and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, direction);
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, tmpITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -5160,6 +5293,145 @@
}
/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint32_t direction = I2C_GENERATE_START_WRITE;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* No need to generate STOP, it is automatically done */
+ /* But enable STOP interrupt, to treat it */
+ /* Error callback will be send during stop flag treatment */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ /* Write LSB part of Memory Address */
+ hi2c->Instance->TXDR = hi2c->Memaddress;
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ /* Enable only Error interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ if (hi2c->XferCount != 0U)
+ {
+ /* Prepare the new XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ direction = I2C_GENERATE_START_READ;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, direction);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Set NBYTES to write and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, direction);
+ }
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, ITFlags);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -6575,24 +6847,21 @@
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
+
/* Update Tick with new reference */
tickstart = HAL_GetTick();
}
-
+
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
+ error_code |=HAL_I2C_ERROR_TIMEOUT;
+
status = HAL_ERROR;
+
+ break;
}
}
}
@@ -6696,14 +6965,14 @@
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
- (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, \
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
- I2C_CR2_START | I2C_CR2_STOP)), tmp);
+ I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
/**
@@ -6764,6 +7033,12 @@
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
diff --git a/Src/stm32wlxx_hal_irda.c b/Src/stm32wlxx_hal_irda.c
index 309f548..c6db81d 100644
--- a/Src/stm32wlxx_hal_irda.c
+++ b/Src/stm32wlxx_hal_irda.c
@@ -463,6 +463,8 @@
/**
* @brief Register a User IRDA Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+ * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -491,8 +493,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hirda);
if (hirda->gState == HAL_IRDA_STATE_READY)
{
@@ -577,15 +577,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hirda);
-
return status;
}
/**
* @brief Unregister an IRDA callback
* IRDA callback is redirected to the weak predefined callback
+ * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+ * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -605,9 +604,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hirda);
-
if (HAL_IRDA_STATE_READY == hirda->gState)
{
switch (CallbackID)
@@ -693,9 +689,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hirda);
-
return status;
}
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
@@ -1425,7 +1418,7 @@
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
if (hirda->Init.Parity != IRDA_PARITY_NONE)
- {
+ {
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
}
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -2318,7 +2311,7 @@
* the configuration information for the specified IRDA module.
* @retval HAL state
*/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
uint32_t temp1;
@@ -2335,7 +2328,7 @@
* the configuration information for the specified IRDA module.
* @retval IRDA Error Code
*/
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda)
{
return hirda->ErrorCode;
}
@@ -2423,21 +2416,21 @@
{
case IRDA_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_HSI:
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_LSE:
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
default:
ret = HAL_ERROR;
@@ -2447,7 +2440,7 @@
/* USARTDIV must be greater than or equal to 0d16 */
if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
{
- hirda->Instance->BRR = tmpreg;
+ hirda->Instance->BRR = (uint16_t)tmpreg;
}
else
{
diff --git a/Src/stm32wlxx_hal_lptim.c b/Src/stm32wlxx_hal_lptim.c
index b9b82f6..ac67d9f 100644
--- a/Src/stm32wlxx_hal_lptim.c
+++ b/Src/stm32wlxx_hal_lptim.c
@@ -507,7 +507,7 @@
* @brief Start the LPTIM PWM generation.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -555,7 +555,7 @@
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -572,7 +572,7 @@
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- /* Set the LPTIM state */
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
@@ -583,7 +583,7 @@
return HAL_TIMEOUT;
}
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -594,7 +594,7 @@
* @brief Start the LPTIM PWM generation in interrupt mode.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF
+ * This parameter must be a value between 0x0001 and 0xFFFF
* @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF
* @retval HAL status
@@ -678,7 +678,7 @@
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -695,7 +695,7 @@
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- /* Set the LPTIM state */
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
@@ -731,7 +731,7 @@
/* Enable Update Event interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UPDATE);
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -742,7 +742,7 @@
* @brief Start the LPTIM One pulse generation.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -790,7 +790,7 @@
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -818,7 +818,7 @@
return HAL_TIMEOUT;
}
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -829,7 +829,7 @@
* @brief Start the LPTIM One pulse generation in interrupt mode.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -913,7 +913,7 @@
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -933,6 +933,7 @@
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@@ -966,7 +967,7 @@
/* Enable Update Event interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UPDATE);
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -977,7 +978,7 @@
* @brief Start the LPTIM in Set once mode.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -1025,7 +1026,7 @@
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1053,7 +1054,7 @@
return HAL_TIMEOUT;
}
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1142,7 +1143,7 @@
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1189,7 +1190,7 @@
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1200,7 +1201,7 @@
* @brief Start the Encoder interface.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
@@ -1250,7 +1251,7 @@
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1281,7 +1282,7 @@
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1360,7 +1361,7 @@
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1397,7 +1398,7 @@
/* Disable "switch to up direction" interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1410,7 +1411,7 @@
* trigger event will reset the counter and the timer restarts.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Timeout Specifies the TimeOut value to reset the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -1458,7 +1459,7 @@
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1489,7 +1490,7 @@
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1502,7 +1503,7 @@
* trigger event will reset the counter and the timer restarts.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Timeout Specifies the TimeOut value to reset the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -1567,7 +1568,7 @@
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1584,12 +1585,13 @@
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- /* Set the LPTIM state */
- hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance);
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@@ -1604,7 +1606,7 @@
/* Disable Compare match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1615,7 +1617,7 @@
* @brief Start the Counter mode.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
@@ -1655,7 +1657,7 @@
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1683,7 +1685,7 @@
return HAL_TIMEOUT;
}
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1694,7 +1696,7 @@
* @brief Start the Counter mode in interrupt mode.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
@@ -1760,7 +1762,7 @@
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1777,12 +1779,13 @@
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- /* Set the LPTIM state */
- hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance);
+ /* Set the LPTIM state */
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@@ -1802,7 +1805,7 @@
/* Disable Update Event interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UPDATE);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1833,7 +1836,7 @@
* @param hlptim LPTIM handle
* @retval Counter value.
*/
-uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
+uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -1846,7 +1849,7 @@
* @param hlptim LPTIM handle
* @retval Autoreload value.
*/
-uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
+uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -1859,7 +1862,7 @@
* @param hlptim LPTIM handle
* @retval Compare value.
*/
-uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
+uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -2221,9 +2224,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hlptim);
-
if (hlptim->State == HAL_LPTIM_STATE_READY)
{
switch (CallbackID)
@@ -2302,9 +2302,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hlptim);
-
return status;
}
@@ -2332,9 +2329,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hlptim);
-
if (hlptim->State == HAL_LPTIM_STATE_READY)
{
switch (CallbackID)
@@ -2426,9 +2420,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hlptim);
-
return status;
}
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
diff --git a/Src/stm32wlxx_hal_pwr.c b/Src/stm32wlxx_hal_pwr.c
index f1d6c59..a77a262 100644
--- a/Src/stm32wlxx_hal_pwr.c
+++ b/Src/stm32wlxx_hal_pwr.c
@@ -111,22 +111,26 @@
#endif
/* Clear all flags */
+#if defined(DUAL_CORE)
LL_PWR_WriteReg(SCR,
LL_PWR_SCR_CWUF
| LL_PWR_SCR_CWRFBUSYF
| LL_PWR_SCR_CWPVDF
-#if defined(DUAL_CORE)
| LL_PWR_SCR_CC2HF
-#endif
);
-
- LL_PWR_WriteReg(EXTSCR,
-#ifdef CORE_CM0PLUS
- LL_PWR_EXTSCR_C2CSSF
#else
- LL_PWR_EXTSCR_C1CSSF
-#endif
+ LL_PWR_WriteReg(SCR,
+ LL_PWR_SCR_CWUF
+ | LL_PWR_SCR_CWRFBUSYF
+ | LL_PWR_SCR_CWPVDF
);
+#endif /* DUAL_CORE */
+
+#ifdef CORE_CM0PLUS
+ LL_PWR_WriteReg(EXTSCR, LL_PWR_EXTSCR_C2CSSF);
+#else
+ LL_PWR_WriteReg(EXTSCR, LL_PWR_EXTSCR_C1CSSF);
+#endif /* CORE_CM0PLUS */
}
diff --git a/Src/stm32wlxx_hal_rcc.c b/Src/stm32wlxx_hal_rcc.c
index dd9e3ef..08f8ffd 100644
--- a/Src/stm32wlxx_hal_rcc.c
+++ b/Src/stm32wlxx_hal_rcc.c
@@ -363,7 +363,7 @@
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI)))
{
- if ((LL_RCC_MSI_IsReady() != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
+ if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)
{
return HAL_ERROR;
}
@@ -389,7 +389,7 @@
else
{
/* Else, keep current flash latency while decreasing applies */
- /* Selects the Multiple Speed oscillator (MSI) clock range .*/
+ /* Selects the Multiple Speed oscillator (MSI) clock range. */
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
@@ -404,7 +404,7 @@
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetHCLKFreq();
- /* Configure the source of time base considering new system clocks settings*/
+ /* Configure the source of time base considering new system clocks settings */
status = HAL_InitTick(uwTickPrio);
if (status != HAL_OK)
{
@@ -432,9 +432,9 @@
}
}
- /* Selects the Multiple Speed oscillator (MSI) clock range .*/
+ /* Selects the Multiple Speed oscillator (MSI) clock range. */
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
- /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
+ /* Adjusts the Multiple Speed oscillator (MSI) calibration value. */
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
}
@@ -468,7 +468,7 @@
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) ||
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
{
- if ((LL_RCC_HSE_IsReady() != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
{
return HAL_ERROR;
}
@@ -487,7 +487,7 @@
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSE is ready */
@@ -501,7 +501,7 @@
}
else
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSE is disabled */
@@ -528,14 +528,14 @@
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
{
/* When HSI is used as system clock it will not be disabled */
- if ((LL_RCC_HSI_IsReady() != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+ if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
{
return HAL_ERROR;
}
/* Otherwise, just the calibration is allowed */
else
{
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
}
}
@@ -559,7 +559,7 @@
}
}
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
}
else
@@ -602,7 +602,7 @@
((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION))
{
/* If LSIRDY is set while LSION is not enabled,
- LSIPRE can't be updated */
+ LSIPRE can't be updated */
return HAL_ERROR;
}
@@ -631,7 +631,7 @@
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
@@ -648,7 +648,7 @@
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSI is disabled */
@@ -699,7 +699,7 @@
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* LSE oscillator enable */
@@ -718,7 +718,7 @@
if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON)
|| (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS))
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
@@ -734,7 +734,7 @@
}
else
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
@@ -751,7 +751,7 @@
}
else
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
@@ -765,7 +765,7 @@
}
}
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* LSE oscillator disable */
@@ -804,7 +804,7 @@
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
@@ -830,7 +830,7 @@
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
@@ -847,13 +847,7 @@
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- /* Disable all PLL outputs to save power */
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE);
-
- __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_RNGCLK | RCC_PLL_ADCCLK);
-
-
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till PLL is disabled */
@@ -864,6 +858,9 @@
return HAL_TIMEOUT;
}
}
+
+ /* Disable the PLL source and outputs to save power when PLL is off */
+ CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN));
}
}
else
@@ -949,7 +946,7 @@
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Check that the new number of wait states is taken into account to access the Flash
@@ -1096,7 +1093,7 @@
/* apply system clock switch */
LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource);
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* check system clock source switch status */
@@ -1115,7 +1112,7 @@
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Check that the new number of wait states is taken into account to access the Flash
@@ -1134,7 +1131,7 @@
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetHCLKFreq();
- /* Configure the source of time base considering new system clocks settings*/
+ /* Configure the source of time base considering new system clocks settings */
return HAL_InitTick(uwTickPrio);
}
@@ -1266,7 +1263,7 @@
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsource == RCC_PLLSOURCE_MSI)))
{
/* MSI or PLL with MSI source used as system clock source */
- /*Retrieve MSI frequency range in HZ*/
+ /* Retrieve MSI frequency range in Hz */
msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
LL_RCC_MSI_GetRange() :
@@ -1394,6 +1391,10 @@
*/
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
+ uint32_t regvalue;
+ uint32_t regICSRvalue;
+ uint32_t regPLLCFGRvalue;
+
/* Check the parameters */
if (RCC_OscInitStruct != NULL)
{
@@ -1401,116 +1402,45 @@
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+ /* Get register values */
+ regvalue = RCC->CR; /* Control register */
+ regICSRvalue = RCC->ICSCR; /* Get Internal Clock Sources Calibration register */
+ regPLLCFGRvalue = RCC->PLLCFGR; /* Get PLL Configuration register */
/* Get the HSE configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_HSEBYPPWR) == RCC_CR_HSEBYPPWR)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_PWR;
- }
- else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;
- }
- else
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
- }
-
- if ((RCC->CR & RCC_CR_HSEPRE) == RCC_CR_HSEPRE)
- {
- RCC_OscInitStruct->HSEDiv = RCC_HSE_DIV2;
- }
- else
- {
- RCC_OscInitStruct->HSEDiv = RCC_HSE_DIV1;
- }
+ RCC_OscInitStruct->HSEState = (regvalue & RCC_HSE_BYPASS_PWR);
+ RCC_OscInitStruct->HSEDiv = (regvalue & RCC_CR_HSEPRE);
/* Get the MSI configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION)
- {
- RCC_OscInitStruct->MSIState = RCC_MSI_ON;
- }
- else
- {
- RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
- }
- RCC_OscInitStruct->MSICalibrationValue = LL_RCC_MSI_GetCalibTrimming();
- RCC_OscInitStruct->MSIClockRange = LL_RCC_MSI_GetRange();
+ RCC_OscInitStruct->MSIState = (regvalue & RCC_CR_MSION);
+ RCC_OscInitStruct->MSICalibrationValue = ((regICSRvalue & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
+ RCC_OscInitStruct->MSIClockRange = (regvalue & RCC_CR_MSIRANGE);
/* Get the HSI configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_ON;
- }
- else
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
- }
-
- RCC_OscInitStruct->HSICalibrationValue = LL_RCC_HSI_GetCalibTrimming();
-
- /* Get the LSE configuration -----------------------------------------------*/
- if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
- {
- if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
- {
- if ((RCC->BDCR & RCC_BDCR_LSESYSEN) == RCC_BDCR_LSESYSEN)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
- }
- else
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_RTC_ONLY;
- }
- }
- else if ((RCC->BDCR & RCC_BDCR_LSESYSEN) == RCC_BDCR_LSESYSEN)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_ON;
- }
- else
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_ON_RTC_ONLY;
- }
- }
- else
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
- }
-
- /* Get the LSI configuration -----------------------------------------------*/
- if (((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION))
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_ON;
- }
- else
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
- }
-
- if ((RCC->CSR & RCC_CSR_LSIPRE) == RCC_CSR_LSIPRE)
- {
- RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV128;
- }
- else
- {
- RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV1;
- }
+ RCC_OscInitStruct->HSIState = (regvalue & RCC_CR_HSION);
+ RCC_OscInitStruct->HSICalibrationValue = ((regICSRvalue & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
/* Get the PLL configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
- }
- else
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
- }
- RCC_OscInitStruct->PLL.PLLSource = LL_RCC_PLL_GetMainSource();
- RCC_OscInitStruct->PLL.PLLM = LL_RCC_PLL_GetDivider();
- RCC_OscInitStruct->PLL.PLLN = LL_RCC_PLL_GetN();
- RCC_OscInitStruct->PLL.PLLP = LL_RCC_PLL_GetP();
- RCC_OscInitStruct->PLL.PLLQ = LL_RCC_PLL_GetQ();
- RCC_OscInitStruct->PLL.PLLR = LL_RCC_PLL_GetR();
+ RCC_OscInitStruct->PLL.PLLState = ((regvalue & RCC_CR_PLLON) >> RCC_CR_PLLON_Pos) + 1U;
+ RCC_OscInitStruct->PLL.PLLSource = (regPLLCFGRvalue & RCC_PLLCFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLM = (regPLLCFGRvalue & RCC_PLLCFGR_PLLM);
+ RCC_OscInitStruct->PLL.PLLN = ((regPLLCFGRvalue & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+ RCC_OscInitStruct->PLL.PLLP = (regPLLCFGRvalue & RCC_PLLCFGR_PLLP);
+ RCC_OscInitStruct->PLL.PLLQ = (regPLLCFGRvalue & RCC_PLLCFGR_PLLQ);
+ RCC_OscInitStruct->PLL.PLLR = (regPLLCFGRvalue & RCC_PLLCFGR_PLLR);
+
+ /* Get Backup Domain register */
+ regvalue = RCC->BDCR;
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ RCC_OscInitStruct->LSEState = (regvalue & RCC_LSE_BYPASS);
+
+ /* Get Control/Status register */
+ regvalue = RCC->CSR;
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ RCC_OscInitStruct->LSIState = (regvalue & RCC_LSI_ON);
+ RCC_OscInitStruct->LSIDiv = (regvalue & RCC_CSR_LSIPRE);
}
}
@@ -1524,6 +1454,8 @@
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
+ uint32_t regvalue;
+
/* Check the parameters */
if ((RCC_ClkInitStruct != NULL) && (pFLatency != NULL))
{
@@ -1534,25 +1466,31 @@
RCC_ClkInitStruct->ClockType |= RCC_CLOCKTYPE_HCLK2;
#endif /* DUAL_CORE */
+ /* Get Clock Configuration Register */
+ regvalue = RCC->CFGR;
+
/* Get the SYSCLK configuration --------------------------------------------*/
- RCC_ClkInitStruct->SYSCLKSource = LL_RCC_GetSysClkSource();
+ RCC_ClkInitStruct->SYSCLKSource = (regvalue & RCC_CFGR_SWS);
/* Get the HCLK configuration ----------------------------------------------*/
- RCC_ClkInitStruct->AHBCLKDivider = LL_RCC_GetAHBPrescaler();
+ RCC_ClkInitStruct->AHBCLKDivider = (regvalue & RCC_CFGR_HPRE);
/* Get the APB1 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB1CLKDivider = LL_RCC_GetAPB1Prescaler();
+ RCC_ClkInitStruct->APB1CLKDivider = (regvalue & RCC_CFGR_PPRE1);
/* Get the APB2 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB2CLKDivider = LL_RCC_GetAPB2Prescaler();
+ RCC_ClkInitStruct->APB2CLKDivider = (regvalue & RCC_CFGR_PPRE2);
+
+ /* Get Extended Clock Recovery Register */
+ regvalue = RCC->EXTCFGR;
#if defined(DUAL_CORE)
/* Get the AHBCLK2Divider configuration ------------------------------------*/
- RCC_ClkInitStruct->AHBCLK2Divider = LL_C2_RCC_GetAHBPrescaler();
+ RCC_ClkInitStruct->AHBCLK2Divider = (regvalue & RCC_EXTCFGR_C2HPRE);
#endif /* DUAL_CORE */
/* Get the AHBCLK3Divider configuration ------------------------------------*/
- RCC_ClkInitStruct->AHBCLK3Divider = LL_RCC_GetAHB3Prescaler();
+ RCC_ClkInitStruct->AHBCLK3Divider = ((regvalue & RCC_EXTCFGR_SHDHPRE) << 4);
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = __HAL_FLASH_GET_LATENCY();
diff --git a/Src/stm32wlxx_hal_rcc_ex.c b/Src/stm32wlxx_hal_rcc_ex.c
index 92ee56c..c1aa0f3 100644
--- a/Src/stm32wlxx_hal_rcc_ex.c
+++ b/Src/stm32wlxx_hal_rcc_ex.c
@@ -1017,36 +1017,11 @@
*/
void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
{
- GPIO_InitTypeDef GPIO_InitStruct;
- FlagStatus backupchanged = RESET;
-
/* Check the parameters */
assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
- /* LSCO Pin Clock Enable */
- __LSCO1_CLK_ENABLE();
-
- /* Configure the LSCO pin in analog mode */
- GPIO_InitStruct.Pin = LSCO1_PIN;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Alternate = GPIO_AF0_LSCO;
- HAL_GPIO_Init(LSCO1_GPIO_PORT, &GPIO_InitStruct);
-
- /* Update LSCOSEL clock source in Backup Domain control register */
- if (LL_PWR_IsEnabledBkUpAccess() == 0U)
- {
- HAL_PWR_EnableBkUpAccess();
- backupchanged = SET;
- }
-
+ /* Update LSCO selection according to parameter and enable LSCO */
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
-
- if (backupchanged == SET)
- {
- HAL_PWR_DisableBkUpAccess();
- }
}
/**
@@ -1055,23 +1030,8 @@
*/
void HAL_RCCEx_DisableLSCO(void)
{
- FlagStatus backupchanged = RESET;
-
- if (LL_PWR_IsEnabledBkUpAccess() == 0U)
- {
- /* Enable access to the backup domain */
- HAL_PWR_EnableBkUpAccess();
- backupchanged = SET;
- }
-
+ /* Clear LSCOEN in BDCR register */
LL_RCC_LSCO_Disable();
-
- /* Restore previous configuration */
- if (backupchanged == SET)
- {
- /* Disable access to the backup domain */
- HAL_PWR_DisableBkUpAccess();
- }
}
/**
diff --git a/Src/stm32wlxx_hal_rtc.c b/Src/stm32wlxx_hal_rtc.c
index a03f95d..3e84756 100644
--- a/Src/stm32wlxx_hal_rtc.c
+++ b/Src/stm32wlxx_hal_rtc.c
@@ -303,36 +303,46 @@
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Enter Initialization mode */
- status = RTC_EnterInitMode(hrtc);
- if (status == HAL_OK)
+ /* Check if the calendar has been not initialized */
+ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
{
- /* Clear RTC_CR FMT, OSEL and POL Bits */
- CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE));
- /* Set RTC_CR register */
- SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity));
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Configure the RTC PRER */
- WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos)));
-
- /* Configure the Binary mode */
- MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU);
-
- /* Exit Initialization mode */
- status = RTC_ExitInitMode(hrtc);
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
if (status == HAL_OK)
{
- MODIFY_REG(RTC->CR, \
- RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \
- hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
- }
- }
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE));
+ /* Set RTC_CR register */
+ SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity));
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Configure the RTC PRER */
+ WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos)));
+
+ /* Configure the Binary mode */
+ MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ if (status == HAL_OK)
+ {
+ MODIFY_REG(RTC->CR, \
+ RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \
+ hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ }
+ else
+ {
+ /* Calendar is already initialized */
+ /* Set flag to OK */
+ status = HAL_OK;
+ }
if (status == HAL_OK)
{
diff --git a/Src/stm32wlxx_hal_smartcard.c b/Src/stm32wlxx_hal_smartcard.c
index 2ffd24a..af5aaa5 100644
--- a/Src/stm32wlxx_hal_smartcard.c
+++ b/Src/stm32wlxx_hal_smartcard.c
@@ -46,7 +46,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
@@ -198,23 +199,24 @@
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
-#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
- USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE | USART_CR1_OVER8| \
+ USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
- USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+ USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
+ USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
- USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
+ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
-#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
/**
* @}
*/
@@ -466,6 +468,9 @@
/**
* @brief Register a User SMARTCARD Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init()
+ * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+ * and HAL_SMARTCARD_MSPDEINIT_CB_ID
* @param hsmartcard smartcard handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -483,7 +488,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
- HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -494,8 +500,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmartcard);
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
@@ -581,15 +585,15 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmartcard);
-
return status;
}
/**
* @brief Unregister an SMARTCARD callback
* SMARTCARD callback is redirected to the weak predefined callback
+ * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init()
+ * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+ * and HAL_SMARTCARD_MSPDEINIT_CB_ID
* @param hsmartcard smartcard handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -610,51 +614,50 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmartcard);
-
if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
{
switch (CallbackID)
{
case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
- hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
- hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_SMARTCARD_ERROR_CB_ID :
- hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
- hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
- hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback*/
break;
case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
- hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
break;
case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
- hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
break;
case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
- hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
break;
case HAL_SMARTCARD_MSPINIT_CB_ID :
- hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_SMARTCARD_MSPDEINIT_CB_ID :
- hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -696,9 +699,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmartcard);
-
return status;
}
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
@@ -725,62 +725,67 @@
(+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
[..]
- (+) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
+ (#) There are two modes of transfer:
+ (##) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) Non-Blocking mode: The communication is performed using Interrupts
+ (##) Non-Blocking mode: The communication is performed using Interrupts
or DMA, the relevant API's return the HAL status.
The end of the data processing will be indicated through the
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
- (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
will be executed respectively at the end of the Transmit or Receive process
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
error is detected.
- (+) Blocking mode APIs are :
- (++) HAL_SMARTCARD_Transmit()
- (++) HAL_SMARTCARD_Receive()
+ (#) Blocking mode APIs are :
+ (##) HAL_SMARTCARD_Transmit()
+ (##) HAL_SMARTCARD_Receive()
- (+) Non Blocking mode APIs with Interrupt are :
- (++) HAL_SMARTCARD_Transmit_IT()
- (++) HAL_SMARTCARD_Receive_IT()
- (++) HAL_SMARTCARD_IRQHandler()
+ (#) Non Blocking mode APIs with Interrupt are :
+ (##) HAL_SMARTCARD_Transmit_IT()
+ (##) HAL_SMARTCARD_Receive_IT()
+ (##) HAL_SMARTCARD_IRQHandler()
- (+) Non Blocking mode functions with DMA are :
- (++) HAL_SMARTCARD_Transmit_DMA()
- (++) HAL_SMARTCARD_Receive_DMA()
+ (#) Non Blocking mode functions with DMA are :
+ (##) HAL_SMARTCARD_Transmit_DMA()
+ (##) HAL_SMARTCARD_Receive_DMA()
- (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_SMARTCARD_TxCpltCallback()
- (++) HAL_SMARTCARD_RxCpltCallback()
- (++) HAL_SMARTCARD_ErrorCallback()
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (##) HAL_SMARTCARD_TxCpltCallback()
+ (##) HAL_SMARTCARD_RxCpltCallback()
+ (##) HAL_SMARTCARD_ErrorCallback()
[..]
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (++) HAL_SMARTCARD_Abort()
- (++) HAL_SMARTCARD_AbortTransmit()
- (++) HAL_SMARTCARD_AbortReceive()
- (++) HAL_SMARTCARD_Abort_IT()
- (++) HAL_SMARTCARD_AbortTransmit_IT()
- (++) HAL_SMARTCARD_AbortReceive_IT()
+ (##) HAL_SMARTCARD_Abort()
+ (##) HAL_SMARTCARD_AbortTransmit()
+ (##) HAL_SMARTCARD_AbortReceive()
+ (##) HAL_SMARTCARD_Abort_IT()
+ (##) HAL_SMARTCARD_AbortTransmit_IT()
+ (##) HAL_SMARTCARD_AbortReceive_IT()
- (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (++) HAL_SMARTCARD_AbortCpltCallback()
- (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
- (++) HAL_SMARTCARD_AbortReceiveCpltCallback()
+ (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
+ a set of Abort Complete Callbacks are provided:
+ (##) HAL_SMARTCARD_AbortCpltCallback()
+ (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (##) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
- If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+ (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer,
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
+ mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -828,7 +833,7 @@
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
@@ -855,8 +860,8 @@
hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
ptmpdata++;
}
- if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
- Timeout) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
+ tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -864,14 +869,14 @@
/* Disable the Peripheral first to update mode */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
for Transmit phase. Disable this receiver block. */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
- || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
@@ -1001,7 +1006,7 @@
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
@@ -1158,7 +1163,7 @@
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
@@ -1311,7 +1316,8 @@
*/
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
{
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
@@ -1373,8 +1379,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1465,7 +1471,8 @@
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
@@ -1505,8 +1512,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1533,14 +1540,16 @@
{
uint32_t abortcplt = 1U;
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
- /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
+ DMA Abort complete callbacks should be initialised before any call
+ to DMA Abort functions */
/* DMA Tx Handle is valid */
if (hsmartcard->hdmatx != NULL)
{
@@ -1634,8 +1643,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1767,7 +1776,8 @@
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
@@ -1806,8 +1816,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1832,8 +1842,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -2261,7 +2271,7 @@
* the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle state
*/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Return SMARTCARD handle state */
uint32_t temp1;
@@ -2278,7 +2288,7 @@
* the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle Error Code
*/
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard)
{
return hsmartcard->ErrorCode;
}
@@ -2304,14 +2314,18 @@
void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Init the SMARTCARD Callback settings */
- hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
- hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
- hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
- hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
- hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
- hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
- hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
- hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak
+ RxFifoFullCallback */
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak
+ TxFifoEmptyCallback */
}
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
@@ -2352,7 +2366,8 @@
* Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
- tmpreg = ((uint32_t)(hsmartcard->Init.Parity)) | ((uint32_t)(hsmartcard->Init.Mode)) | ((uint32_t)(hsmartcard->Init.WordLength));
+ tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
+ ((uint32_t)hsmartcard->Init.WordLength));
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
@@ -2400,21 +2415,26 @@
{
case SMARTCARD_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
- tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
- tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
default:
ret = HAL_ERROR;
@@ -2424,7 +2444,7 @@
/* USARTDIV must be greater than or equal to 0d16 */
if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
{
- hsmartcard->Instance->BRR = tmpreg;
+ hsmartcard->Instance->BRR = (uint16_t)tmpreg;
}
else
{
@@ -2576,7 +2596,8 @@
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -2770,8 +2791,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -2819,8 +2840,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -2881,8 +2902,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -2988,14 +3009,14 @@
/* Disable the Peripheral first to update mode */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
for Transmit phase. Disable this receiver block. */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
- || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
diff --git a/Src/stm32wlxx_hal_smbus.c b/Src/stm32wlxx_hal_smbus.c
index 89058d4..f6b2a79 100644
--- a/Src/stm32wlxx_hal_smbus.c
+++ b/Src/stm32wlxx_hal_smbus.c
@@ -584,6 +584,9 @@
/**
* @brief Register a User SMBUS Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in
+ * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+ * HAL_SMBUS_MSPDEINIT_CB_ID.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param CallbackID ID of the callback to be registered
@@ -613,9 +616,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
switch (CallbackID)
@@ -691,14 +691,15 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
/**
* @brief Unregister an SMBUS Callback
* SMBUS callback is redirected to the weak predefined callback
+ * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in
+ * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+ * HAL_SMBUS_MSPDEINIT_CB_ID
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param CallbackID ID of the callback to be unregistered
@@ -719,9 +720,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
switch (CallbackID)
@@ -797,8 +795,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
@@ -822,8 +818,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmbus);
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
@@ -838,8 +832,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
@@ -854,9 +846,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
@@ -870,8 +859,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
diff --git a/Src/stm32wlxx_hal_subghz.c b/Src/stm32wlxx_hal_subghz.c
index 3c9461c..c66c8db 100644
--- a/Src/stm32wlxx_hal_subghz.c
+++ b/Src/stm32wlxx_hal_subghz.c
@@ -82,6 +82,7 @@
(+) RxTxTimeoutCallback : callback for Rx Tx Timeout.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
+ (+) LrFhssHopCallback : callback for LoRa Frequency Hopping Spread Spectrum Hopping.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
@@ -103,6 +104,7 @@
(+) RxTxTimeoutCallback : callback for Rx Tx Timeout.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
+ (+) LrFhssHopCallback : callback for LoRa Frequency Hopping Spread Spectrum Hopping.
[..]
For specific callback CADStatusCallback use dedicated register callbacks :
@ref HAL_SUBGHZ_UnRegisterCadStatusCallback().
@@ -208,12 +210,16 @@
* in the SUBGHZ_HandleTypeDef and initialize the associated handle.
* @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains
* the handle information for SUBGHZ module.
+ * @note In case of exiting from Standby mode, before calling this function,
+ * set the state to HAL_SUBGHZ_STATE_RESET_RF_READY with __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY
+ * to avoid the reset of Radio peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz)
{
HAL_StatusTypeDef status;
__IO uint32_t count;
+ HAL_SUBGHZ_StateTypeDef subghz_state;
/* Check the hsubghz handle allocation */
if (hsubghz == NULL)
@@ -228,7 +234,9 @@
assert_param(IS_SUBGHZSPI_BAUDRATE_PRESCALER(hsubghz->Init.BaudratePrescaler));
- if (hsubghz->State == HAL_SUBGHZ_STATE_RESET)
+ subghz_state = hsubghz->State;
+ if ((subghz_state == HAL_SUBGHZ_STATE_RESET) ||
+ (subghz_state == HAL_SUBGHZ_STATE_RESET_RF_READY))
{
/* Allocate lock resource and initialize it */
hsubghz->Lock = HAL_UNLOCKED;
@@ -244,6 +252,7 @@
hsubghz->CRCErrorCallback = HAL_SUBGHZ_CRCErrorCallback;
hsubghz->CADStatusCallback = HAL_SUBGHZ_CADStatusCallback;
hsubghz->RxTxTimeoutCallback = HAL_SUBGHZ_RxTxTimeoutCallback;
+ hsubghz->LrFhssHopCallback = HAL_SUBGHZ_LrFhssHopCallback;
if (hsubghz->MspInitCallback == NULL)
{
@@ -256,43 +265,49 @@
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SUBGHZ_MspInit(hsubghz);
#endif /* USE_HAL_ SUBGHZ_REGISTER_CALLBACKS */
- }
-
- hsubghz->State = HAL_SUBGHZ_STATE_BUSY;
-
- /* De-asserts the reset signal of the Radio peripheral */
- LL_RCC_RF_DisableReset();
-
- /* Verify that Radio in reset status flag is set */
- count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME;
-
- do
- {
- if (count == 0U)
- {
- status = HAL_ERROR;
- hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT;
- break;
- }
- count--;
- } while (LL_RCC_IsRFUnderReset() != 0UL);
-
- /* Asserts the reset signal of the Radio peripheral */
- LL_PWR_UnselectSUBGHZSPI_NSS();
#if defined(CM0PLUS)
- /* Enable EXTI 44 : Radio IRQ ITs for CPU2 */
- LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44);
-
- /* Enable wakeup signal of the Radio peripheral */
- LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT);
+ /* Enable EXTI 44 : Radio IRQ ITs for CPU2 */
+ LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44);
#else
- /* Enable EXTI 44 : Radio IRQ ITs for CPU1 */
- LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44);
-
- /* Enable wakeup signal of the Radio peripheral */
- LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT);
+ /* Enable EXTI 44 : Radio IRQ ITs for CPU1 */
+ LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44);
#endif /* CM0PLUS */
+ }
+
+ if (subghz_state == HAL_SUBGHZ_STATE_RESET)
+ {
+ /* Reinitialize Radio peripheral only if SUBGHZ is in full RESET state */
+ hsubghz->State = HAL_SUBGHZ_STATE_BUSY;
+
+ /* De-asserts the reset signal of the Radio peripheral */
+ LL_RCC_RF_DisableReset();
+
+ /* Verify that Radio in reset status flag is set */
+ count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME;
+
+ do
+ {
+ if (count == 0U)
+ {
+ status = HAL_ERROR;
+ hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT;
+ break;
+ }
+ count--;
+ } while (LL_RCC_IsRFUnderReset() != 0UL);
+
+ /* Asserts the reset signal of the Radio peripheral */
+ LL_PWR_UnselectSUBGHZSPI_NSS();
+
+#if defined(CM0PLUS)
+ /* Enable wakeup signal of the Radio peripheral */
+ LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT);
+#else
+ /* Enable wakeup signal of the Radio peripheral */
+ LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT);
+#endif /* CM0PLUS */
+ }
/* Clear Pending Flag */
LL_PWR_ClearFlag_RFBUSY();
@@ -305,7 +320,8 @@
hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE;
hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_NONE;
}
- hsubghz->State = HAL_SUBGHZ_STATE_READY;
+
+ hsubghz->State = HAL_SUBGHZ_STATE_READY;
return status;
}
@@ -496,6 +512,10 @@
hsubghz->MspDeInitCallback = pCallback;
break;
+ case HAL_SUBGHZ_LR_FHSS_HOP_CB_ID :
+ hsubghz->LrFhssHopCallback = pCallback;
+ break;
+
default :
/* Update the error code */
hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK;
@@ -602,6 +622,10 @@
hsubghz->MspDeInitCallback = HAL_SUBGHZ_MspDeInit;
break;
+ case HAL_SUBGHZ_LR_FHSS_HOP_CB_ID :
+ hsubghz->LrFhssHopCallback = HAL_SUBGHZ_LrFhssHopCallback;
+ break;
+
default :
/* Update the error code */
hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_INVALID_CALLBACK;
@@ -703,7 +727,7 @@
if (HAL_SUBGHZ_STATE_READY == hsubghz->State)
{
- hsubghz->CADStatusCallback = HAL_SUBGHZ_CADStatusCallback; /* Legacy weak AddrCallback */
+ hsubghz->CADStatusCallback = HAL_SUBGHZ_CADStatusCallback; /* Legacy weak AddrCallback */
}
else
{
@@ -907,7 +931,6 @@
return (HAL_SUBGHZ_WriteRegisters(hsubghz, Address, &Value, 1U));
}
-
/**
* @brief Read data register at an Address in the peripheral
* @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains
@@ -923,7 +946,6 @@
return (HAL_SUBGHZ_ReadRegisters(hsubghz, Address, pValue, 1U));
}
-
/**
* @brief Send a command to configure the peripheral
* @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains
@@ -1205,6 +1227,9 @@
itsource = tmpisr[0U];
itsource = (itsource << 8U) | tmpisr[1U];
+ /* Clear SUBGHZ Irq Register */
+ (void)HAL_SUBGHZ_ExecSetCmd(hsubghz, RADIO_CLR_IRQSTATUS, tmpisr, 2U);
+
/* Packet transmission completed Interrupt */
if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_TX_CPLT) != RESET)
{
@@ -1311,8 +1336,15 @@
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
}
- /* Clear SUBGHZ Irq Register */
- (void)HAL_SUBGHZ_ExecSetCmd(hsubghz, RADIO_CLR_IRQSTATUS, tmpisr, 2);
+ /* LR_FHSS Hop interrupt */
+ if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_LR_FHSS_HOP) != RESET)
+ {
+#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U)
+ hsubghz->LrFhssHopCallback(hsubghz);
+#else
+ HAL_SUBGHZ_LrFhssHopCallback(hsubghz);
+#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
+ }
}
/**
@@ -1464,6 +1496,21 @@
}
/**
+ * @brief LR FHSS Hop callback.
+ * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains
+ * the configuration information for SUBGHZ module.
+ * @retval None
+ */
+__weak void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsubghz);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SUBGHZ_LrFhssHopCallback should be implemented in the user file
+ */
+}
+/**
* @}
*/
@@ -1762,4 +1809,3 @@
/**
* @}
*/
-
diff --git a/Src/stm32wlxx_hal_tim.c b/Src/stm32wlxx_hal_tim.c
index 71fd009..50b1468 100644
--- a/Src/stm32wlxx_hal_tim.c
+++ b/Src/stm32wlxx_hal_tim.c
@@ -205,11 +205,11 @@
/** @addtogroup TIM_Private_Functions
* @{
*/
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter);
@@ -225,7 +225,7 @@
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig);
+ const TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
* @}
*/
@@ -278,6 +278,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -525,7 +526,7 @@
* @param Length The length of data to be transferred from memory to peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
@@ -539,7 +540,7 @@
}
else if (htim->State == HAL_TIM_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -661,6 +662,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -1050,7 +1052,8 @@
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+ uint16_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
@@ -1065,7 +1068,7 @@
}
else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -1328,6 +1331,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -1717,7 +1721,8 @@
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+ uint16_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
@@ -1732,7 +1737,7 @@
}
else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -1994,6 +1999,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -2387,7 +2393,7 @@
else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -2643,6 +2649,7 @@
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -3046,6 +3053,7 @@
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
if (htim->State == HAL_TIM_STATE_RESET)
{
@@ -3555,7 +3563,7 @@
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData1 == NULL) && (Length > 0U))
+ if ((pData1 == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -3580,7 +3588,7 @@
else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData2 == NULL) && (Length > 0U))
+ if ((pData2 == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -3609,7 +3617,7 @@
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -4054,7 +4062,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
+ const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -4152,7 +4160,7 @@
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -4254,7 +4262,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
+ const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -4556,7 +4564,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
{
HAL_StatusTypeDef status;
@@ -4614,7 +4622,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -5269,7 +5277,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
- TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ const TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -5445,7 +5453,7 @@
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
@@ -5631,7 +5639,7 @@
* (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@@ -5672,7 +5680,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig)
+ const TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@@ -5714,7 +5722,7 @@
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval Captured value
*/
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpreg = 0U;
@@ -5989,8 +5997,6 @@
{
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(htim);
if (htim->State == HAL_TIM_STATE_READY)
{
@@ -6186,9 +6192,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
return status;
}
@@ -6232,9 +6235,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(htim);
-
if (htim->State == HAL_TIM_STATE_READY)
{
switch (CallbackID)
@@ -6471,9 +6471,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
return status;
}
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@@ -6502,7 +6499,7 @@
* @param htim TIM Base handle
* @retval HAL state
*/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@@ -6512,7 +6509,7 @@
* @param htim TIM Output Compare handle
* @retval HAL state
*/
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@@ -6522,7 +6519,7 @@
* @param htim TIM handle
* @retval HAL state
*/
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@@ -6532,7 +6529,7 @@
* @param htim TIM IC handle
* @retval HAL state
*/
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@@ -6542,7 +6539,7 @@
* @param htim TIM OPM handle
* @retval HAL state
*/
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@@ -6552,7 +6549,7 @@
* @param htim TIM Encoder Interface handle
* @retval HAL state
*/
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@@ -6562,7 +6559,7 @@
* @param htim TIM handle
* @retval Active channel
*/
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
{
return htim->Channel;
}
@@ -6580,7 +6577,7 @@
* @arg TIM_CHANNEL_6: TIM Channel 6
* @retval TIM Channel state
*/
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
{
HAL_TIM_ChannelStateTypeDef channel_state;
@@ -6597,7 +6594,7 @@
* @param htim TIM handle
* @retval DMA burst state
*/
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@@ -6940,7 +6937,7 @@
* @param Structure TIM Base configuration structure
* @retval None
*/
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
@@ -6988,7 +6985,7 @@
* @param OC_Config The output configuration structure
* @retval None
*/
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@@ -7063,7 +7060,7 @@
* @param OC_Config The output configuration structure
* @retval None
*/
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@@ -7139,7 +7136,7 @@
* @param OC_Config The output configuration structure
* @retval None
*/
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@@ -7213,7 +7210,7 @@
* @param OC_Config The output configuration structure
* @retval None
*/
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@@ -7274,7 +7271,7 @@
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
+ const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@@ -7327,7 +7324,7 @@
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
+ const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@@ -7381,7 +7378,7 @@
* @retval None
*/
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig)
+ const TIM_SlaveConfigTypeDef *sSlaveConfig)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
diff --git a/Src/stm32wlxx_hal_tim_ex.c b/Src/stm32wlxx_hal_tim_ex.c
index d94529e..cf36eef 100644
--- a/Src/stm32wlxx_hal_tim_ex.c
+++ b/Src/stm32wlxx_hal_tim_ex.c
@@ -159,7 +159,7 @@
* @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
{
TIM_OC_InitTypeDef OC_Config;
@@ -175,6 +175,7 @@
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@@ -525,7 +526,7 @@
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -890,7 +891,8 @@
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+ uint16_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
@@ -905,7 +907,7 @@
}
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -1371,7 +1373,8 @@
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+ uint16_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
@@ -1386,7 +1389,7 @@
}
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -1985,7 +1988,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig)
+ const TIM_MasterConfigTypeDef *sMasterConfig)
{
uint32_t tmpcr2;
uint32_t tmpsmcr;
@@ -2058,7 +2061,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+ const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
@@ -2141,7 +2144,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
uint32_t BreakInput,
- TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+ const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -2604,7 +2607,7 @@
* @param htim TIM Hall Sensor handle
* @retval HAL state
*/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@@ -2619,7 +2622,7 @@
* @arg TIM_CHANNEL_3: TIM Channel 3
* @retval TIM Complementary channel state
*/
-HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
{
HAL_TIM_ChannelStateTypeDef channel_state;
diff --git a/Src/stm32wlxx_hal_uart.c b/Src/stm32wlxx_hal_uart.c
index 655d8e2..ddb18e5 100644
--- a/Src/stm32wlxx_hal_uart.c
+++ b/Src/stm32wlxx_hal_uart.c
@@ -177,27 +177,22 @@
/** @defgroup UART_Private_Constants UART Private Constants
* @{
*/
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
- USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
+ USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
- USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
+ USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
-
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
-
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions
* @{
@@ -227,6 +222,16 @@
* @}
*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup UART_Private_variables
+ * @{
+ */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+ * @}
+ */
+
+/* Exported Constants --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UART_Exported_Functions UART Exported Functions
@@ -651,6 +656,7 @@
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart);
@@ -691,6 +697,9 @@
/**
* @brief Register a User UART Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+ * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
+ * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -722,8 +731,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
if (huart->gState == HAL_UART_STATE_READY)
{
switch (CallbackID)
@@ -813,14 +820,15 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(huart);
-
return status;
}
/**
* @brief Unregister an UART Callback
* UART callaback is redirected to the weak predefined callback
+ * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+ * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register
+ * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -843,8 +851,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- __HAL_LOCK(huart);
-
if (HAL_UART_STATE_READY == huart->gState)
{
switch (CallbackID)
@@ -936,8 +942,6 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(huart);
-
return status;
}
@@ -1073,7 +1077,8 @@
(+) HAL_UART_AbortTransmitCpltCallback()
(+) HAL_UART_AbortReceiveCpltCallback()
- (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services:
+ (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
+ reception services:
(+) HAL_UARTEx_RxEventCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
@@ -1145,8 +1150,6 @@
}
#endif /* CORE_CM0PLUS */
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
@@ -1168,8 +1171,6 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
while (huart->TxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
@@ -1216,8 +1217,8 @@
* RXNE are mapped on the same bit-field.
* @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor.
* When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
- * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required
* to ensure proper alignment for pData.
* @param huart UART handle.
@@ -1254,8 +1255,6 @@
}
#endif /* CORE_CM0PLUS */
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1282,8 +1281,6 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
@@ -1354,8 +1351,6 @@
}
#endif /* CORE_CM0PLUS */
- __HAL_LOCK(huart);
-
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
@@ -1377,8 +1372,6 @@
huart->TxISR = UART_TxISR_8BIT_FIFOEN;
}
- __HAL_UNLOCK(huart);
-
/* Enable the TX FIFO threshold interrupt */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
}
@@ -1394,8 +1387,6 @@
huart->TxISR = UART_TxISR_8BIT;
}
- __HAL_UNLOCK(huart);
-
/* Enable the Transmit Data Register Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
}
@@ -1415,8 +1406,8 @@
* of u16 available through pData.
* @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor.
* When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
- * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required
* to ensure proper alignment for pData.
* @param huart UART handle.
@@ -1447,22 +1438,20 @@
}
#endif /* CORE_CM0PLUS */
- __HAL_LOCK(huart);
-
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
/* Check that USART RTOEN bit is set */
- if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
- return(UART_Start_Receive_IT(huart, pData, Size));
+ return (UART_Start_Receive_IT(huart, pData, Size));
}
else
{
@@ -1509,8 +1498,6 @@
}
#endif /* CORE_CM0PLUS */
- __HAL_LOCK(huart);
-
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
@@ -1538,8 +1525,6 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- __HAL_UNLOCK(huart);
-
/* Restore huart->gState to ready */
huart->gState = HAL_UART_STATE_READY;
@@ -1549,8 +1534,6 @@
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
- __HAL_UNLOCK(huart);
-
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
@@ -1604,22 +1587,20 @@
}
#endif /* CORE_CM0PLUS */
- __HAL_LOCK(huart);
-
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
/* Check that USART RTOEN bit is set */
- if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
- return(UART_Start_Receive_DMA(huart, pData, Size));
+ return (UART_Start_Receive_DMA(huart, pData, Size));
}
else
{
@@ -1637,8 +1618,6 @@
const HAL_UART_StateTypeDef gstate = huart->gState;
const HAL_UART_StateTypeDef rxstate = huart->RxState;
- __HAL_LOCK(huart);
-
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
(gstate == HAL_UART_STATE_BUSY_TX))
{
@@ -1656,8 +1635,6 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
@@ -1668,8 +1645,6 @@
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
- __HAL_LOCK(huart);
-
if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
@@ -1691,8 +1666,6 @@
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
@@ -1789,9 +1762,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1814,9 +1788,10 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -1883,9 +1858,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1947,9 +1923,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -2048,7 +2025,7 @@
}
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
@@ -2072,9 +2049,10 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2160,9 +2138,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
@@ -2256,9 +2235,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2437,9 +2417,10 @@
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel */
@@ -2501,9 +2482,9 @@
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
- if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- &&((isrflags & USART_ISR_IDLE) != 0U)
- &&((cr1its & USART_ISR_IDLE) != 0U))
+ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ && ((isrflags & USART_ISR_IDLE) != 0U)
+ && ((cr1its & USART_ISR_IDLE) != 0U))
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
@@ -2515,8 +2496,8 @@
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
- if ( (nb_remaining_rx_data > 0U)
- &&(nb_remaining_rx_data < huart->RxXferSize))
+ if ((nb_remaining_rx_data > 0U)
+ && (nb_remaining_rx_data < huart->RxXferSize))
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
@@ -2541,13 +2522,18 @@
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
}
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
}
@@ -2557,8 +2543,8 @@
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
- if ( (huart->RxXferCount > 0U)
- &&(nb_rx_data > 0U) )
+ if ((huart->RxXferCount > 0U)
+ && (nb_rx_data > 0U))
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
@@ -2574,13 +2560,18 @@
huart->RxISR = NULL;
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
}
@@ -3058,7 +3049,7 @@
* the configuration information for the specified UART.
* @retval HAL state
*/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart)
{
uint32_t temp1;
uint32_t temp2;
@@ -3074,7 +3065,7 @@
* the configuration information for the specified UART.
* @retval UART Error Code
*/
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart)
{
return huart->ErrorCode;
}
@@ -3268,7 +3259,7 @@
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
{
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
@@ -3309,10 +3300,10 @@
if (pclk != 0U)
{
/* USARTDIV must be greater than or equal to 0d16 */
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
- huart->Instance->BRR = usartdiv;
+ huart->Instance->BRR = (uint16_t)usartdiv;
}
else
{
@@ -3447,6 +3438,7 @@
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart);
@@ -3556,8 +3548,6 @@
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
}
- __HAL_UNLOCK(huart);
-
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
{
@@ -3577,8 +3567,6 @@
huart->RxISR = UART_RxISR_8BIT;
}
- __HAL_UNLOCK(huart);
-
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
{
@@ -3587,7 +3575,7 @@
else
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
- }
+ }
}
return HAL_OK;
}
@@ -3631,15 +3619,12 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- __HAL_UNLOCK(huart);
-
/* Restore huart->RxState to ready */
huart->RxState = HAL_UART_STATE_READY;
return HAL_ERROR;
}
}
- __HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
@@ -3784,6 +3769,10 @@
}
}
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -3818,16 +3807,20 @@
{
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Half Transfer */
+ huart->RxEventType = HAL_UART_RXEVENT_HT;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
- huart->RxEventCallback(huart, huart->RxXferSize/2U);
+ huart->RxEventCallback(huart, huart->RxXferSize / 2U);
#else
/*Call legacy weak Rx Event callback*/
- HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U);
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
else
@@ -4278,6 +4271,19 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4293,13 +4299,14 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
@@ -4357,6 +4364,19 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4372,13 +4392,14 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
@@ -4487,6 +4508,19 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4502,13 +4536,14 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
@@ -4637,6 +4672,19 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4652,13 +4700,14 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
diff --git a/Src/stm32wlxx_hal_uart_ex.c b/Src/stm32wlxx_hal_uart_ex.c
index 2528b01..4e972f1 100644
--- a/Src/stm32wlxx_hal_uart_ex.c
+++ b/Src/stm32wlxx_hal_uart_ex.c
@@ -739,11 +739,10 @@
}
#endif /* CORE_CM0PLUS */
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
@@ -767,8 +766,6 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
/* Initialize output number of received elements */
*RxLen = 0U;
@@ -785,6 +782,7 @@
/* If Set, and data has already been received, this means Idle Event is valid : End reception */
if (*RxLen > 0U)
{
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
@@ -877,10 +875,9 @@
}
#endif /* CORE_CM0PLUS */
- __HAL_LOCK(huart);
-
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_IT(huart, pData, Size);
@@ -956,10 +953,9 @@
}
#endif /* CORE_CM0PLUS */
- __HAL_LOCK(huart);
-
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_DMA(huart, pData, Size);
@@ -990,6 +986,36 @@
}
/**
+ * @brief Provide Rx Event type that has lead to RxEvent callback execution.
+ * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
+ * of reception process is provided to application through calls of Rx Event callback (either default one
+ * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
+ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
+ * to Rx Event callback execution.
+ * @note This function is expected to be called within the user implementation of Rx Event Callback,
+ * in order to provide the accurate value :
+ * In Interrupt Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+ * received data is lower than expected one)
+ * In DMA Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+ * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+ * received data is lower than expected one).
+ * In DMA mode, RxEvent callback could be called several times;
+ * When DMA is configured in Normal Mode, HT event does not stop Reception process;
+ * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
+ * @param huart UART handle.
+ * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
+ */
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
+{
+ /* Return Rx Event type value, as stored in UART handle */
+ return(huart->RxEventType);
+}
+
+/**
* @}
*/
diff --git a/Src/stm32wlxx_hal_usart.c b/Src/stm32wlxx_hal_usart.c
index 5355ea7..0e59136 100644
--- a/Src/stm32wlxx_hal_usart.c
+++ b/Src/stm32wlxx_hal_usart.c
@@ -318,7 +318,8 @@
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.
+ */
husart->Instance->CR2 &= ~USART_CR2_LINEN;
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
@@ -2060,9 +2061,10 @@
USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
- /* Disable the USART DMA Tx request if enabled */
+ /* Abort the USART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the USART DMA Tx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -2085,9 +2087,10 @@
}
}
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -2189,7 +2192,7 @@
}
}
- /* Disable the USART DMA Tx request if enabled */
+ /* Abort the USART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at USART level */
@@ -2213,9 +2216,10 @@
}
}
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2290,7 +2294,8 @@
uint32_t errorcode;
/* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF |
+ USART_ISR_UDR));
if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
@@ -2386,9 +2391,10 @@
Disable Interrupts, and disable DMA requests, if ongoing */
USART_EndTransfer(husart);
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
/* Abort the USART DMA Tx channel */
@@ -2637,7 +2643,7 @@
* the configuration information for the specified USART.
* @retval USART handle state
*/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart)
{
return husart->State;
}
@@ -2648,7 +2654,7 @@
* the configuration information for the specified USART.
* @retval USART handle Error Code
*/
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart)
{
return husart->ErrorCode;
}
diff --git a/Src/stm32wlxx_ll_adc.c b/Src/stm32wlxx_ll_adc.c
index a34dd23..1f7c698 100644
--- a/Src/stm32wlxx_ll_adc.c
+++ b/Src/stm32wlxx_ll_adc.c
@@ -212,6 +212,9 @@
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ (void)(ADCxy_COMMON);
+
/* Force reset of ADC clock (core clock) */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
@@ -407,14 +410,14 @@
/* Reset register SMPR */
CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
- /* Reset register TR1 */
- MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
+ /* Reset register AWD1TR */
+ MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
- /* Reset register TR2 */
- MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
+ /* Reset register AWD2TR */
+ MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
- /* Reset register TR3 */
- MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
+ /* Reset register AWD3TR */
+ MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
/* Reset register CHSELR */
CLEAR_BIT(ADCx->CHSELR,
diff --git a/Src/stm32wlxx_ll_comp.c b/Src/stm32wlxx_ll_comp.c
index bdc80ba..fe0b9ba 100644
--- a/Src/stm32wlxx_ll_comp.c
+++ b/Src/stm32wlxx_ll_comp.c
@@ -164,7 +164,7 @@
* - SUCCESS: COMP registers are initialized
* - ERROR: COMP registers are not initialized
*/
-ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct)
{
ErrorStatus status = SUCCESS;
diff --git a/Src/stm32wlxx_ll_dac.c b/Src/stm32wlxx_ll_dac.c
index 257f713..c69d56b 100644
--- a/Src/stm32wlxx_ll_dac.c
+++ b/Src/stm32wlxx_ll_dac.c
@@ -25,7 +25,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32WLxx_LL_Driver
* @{
@@ -59,56 +59,56 @@
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
)
-#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
- ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
+ ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
)
#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \
( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
- && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \
+ && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \
) \
- ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
- && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \
- ) \
+ ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+ && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \
+ ) \
)
#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
- || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
+ || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
)
#define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \
( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \
- || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
+ || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
)
#define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \
( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \
- || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
+ || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
)
/**
@@ -173,7 +173,7 @@
* - SUCCESS: DAC registers are initialized
* - ERROR: DAC registers are not initialized
*/
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct)
{
ErrorStatus status = SUCCESS;
diff --git a/Src/stm32wlxx_ll_exti.c b/Src/stm32wlxx_ll_exti.c
index 00338a0..06b7271 100644
--- a/Src/stm32wlxx_ll_exti.c
+++ b/Src/stm32wlxx_ll_exti.c
@@ -23,7 +23,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32WLxx_LL_Driver
* @{
@@ -47,14 +47,14 @@
#define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
- || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
- || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
+ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
/**
* @}
@@ -81,56 +81,56 @@
{
/* Rising Trigger selection register set to default reset values */
LL_EXTI_WriteReg(RTSR1, 0x00000000U);
-
+
/* Falling Trigger selection register set to default reset values */
LL_EXTI_WriteReg(FTSR1, 0x00000000U);
-
+
/* Software interrupt event register set to default reset values */
LL_EXTI_WriteReg(SWIER1, 0x00000000U);
-
+
/* Pending register set to default reset values */
LL_EXTI_WriteReg(PR1, 0xFFFFFFFFU);
/* Rising Trigger selection register 2 set to default reset values */
LL_EXTI_WriteReg(RTSR2, 0x00000000U);
-
+
/* Falling Trigger selection register 2 set to default reset values */
LL_EXTI_WriteReg(FTSR2, 0x00000000U);
-
+
/* Software interrupt event register 2 set to default reset values */
LL_EXTI_WriteReg(SWIER2, 0x00000000U);
-
+
/* Pending register 2 set to default reset values */
LL_EXTI_WriteReg(PR2, 0xFFFFFFFFU);
-
+
/* Interrupt mask register set to default reset values */
#if defined(DUAL_CORE) && defined (CORE_CM0PLUS)
LL_EXTI_WriteReg(C2IMR1, 0x00000000U);
#else
LL_EXTI_WriteReg(IMR1, 0x00000000U);
-#endif
-
+#endif /* DUAL_CORE && CORE_CM0PLUS */
+
/* Event mask register set to default reset values */
#if defined(DUAL_CORE) && defined (CORE_CM0PLUS)
LL_EXTI_WriteReg(C2EMR1, 0x00000000U);
#else
LL_EXTI_WriteReg(EMR1, 0x00000000U);
-#endif
-
+#endif /* DUAL_CORE && CORE_CM0PLUS */
+
/* Interrupt mask register 2 set to default reset values */
#if defined(DUAL_CORE) && defined (CORE_CM0PLUS)
LL_EXTI_WriteReg(C2IMR2, 0x00000000U);
#else
LL_EXTI_WriteReg(IMR2, 0x00000000U);
-#endif
-
+#endif /* DUAL_CORE && CORE_CM0PLUS */
+
/* Event mask register 2 set to default reset values */
#if defined(DUAL_CORE) && defined (CORE_CM0PLUS)
LL_EXTI_WriteReg(C2EMR2, 0x00000000U);
#else
LL_EXTI_WriteReg(EMR2, 0x00000000U);
-#endif
-
+#endif /* DUAL_CORE && CORE_CM0PLUS */
+
return SUCCESS;
}
@@ -202,7 +202,7 @@
default:
status = ERROR;
break;
-#endif
+#endif /* DUAL_CORE && CORE_CM0PLUS */
}
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
{
@@ -277,7 +277,7 @@
default:
status = ERROR;
break;
-#endif
+#endif /* DUAL_CORE && CORE_CM0PLUS */
}
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
{
@@ -323,7 +323,7 @@
/* De-configure EXTI Lines in range from 32 to 63 */
LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
-#endif
+#endif /* DUAL_CORE && CORE_CM0PLUS */
}
return status;
}
diff --git a/Src/stm32wlxx_ll_lptim.c b/Src/stm32wlxx_ll_lptim.c
index b5b28bf..d575df6 100644
--- a/Src/stm32wlxx_ll_lptim.c
+++ b/Src/stm32wlxx_ll_lptim.c
@@ -147,7 +147,7 @@
* - SUCCESS: LPTIMx instance has been initialized
* - ERROR: LPTIMx instance hasn't been initialized
*/
-ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
{
ErrorStatus result = SUCCESS;
/* Check the parameters */
@@ -283,8 +283,7 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- }
- while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_ARROK(LPTIMx);
}
diff --git a/Src/stm32wlxx_ll_lpuart.c b/Src/stm32wlxx_ll_lpuart.c
index 88b7798..6720c5d 100644
--- a/Src/stm32wlxx_ll_lpuart.c
+++ b/Src/stm32wlxx_ll_lpuart.c
@@ -126,7 +126,7 @@
* - SUCCESS: LPUART registers are de-initialized
* - ERROR: not applicable
*/
-ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
+ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx)
{
ErrorStatus status = SUCCESS;
@@ -164,7 +164,7 @@
* - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
* - ERROR: Problem occurred during LPUART Registers initialization
*/
-ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
{
ErrorStatus status = ERROR;
uint32_t periphclk;
diff --git a/Src/stm32wlxx_ll_tim.c b/Src/stm32wlxx_ll_tim.c
index 6654b22..de9c89f 100644
--- a/Src/stm32wlxx_ll_tim.c
+++ b/Src/stm32wlxx_ll_tim.c
@@ -189,16 +189,16 @@
/** @defgroup TIM_LL_Private_Functions TIM Private Functions
* @{
*/
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
/**
* @}
*/
@@ -279,7 +279,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
{
uint32_t tmpcr1;
@@ -360,7 +360,7 @@
* - SUCCESS: TIMx output channel is initialized
* - ERROR: TIMx output channel is not initialized
*/
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
{
ErrorStatus result = ERROR;
@@ -421,7 +421,7 @@
* - SUCCESS: TIMx output channel is initialized
* - ERROR: TIMx output channel is not initialized
*/
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
{
ErrorStatus result = ERROR;
@@ -475,7 +475,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
{
uint32_t tmpccmr1;
uint32_t tmpccer;
@@ -568,7 +568,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
{
uint32_t tmpcr2;
uint32_t tmpccmr1;
@@ -682,7 +682,7 @@
* - SUCCESS: Break and Dead Time is initialized
* - ERROR: not applicable
*/
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
{
uint32_t tmpbdtr = 0;
@@ -707,13 +707,10 @@
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
- if (IS_TIM_ADVANCED_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
- assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
- }
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
if (IS_TIM_BKIN2_INSTANCE(TIMx))
{
@@ -754,7 +751,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
uint32_t tmpccmr1;
uint32_t tmpccer;
@@ -833,7 +830,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
uint32_t tmpccmr1;
uint32_t tmpccer;
@@ -912,7 +909,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
uint32_t tmpccmr2;
uint32_t tmpccer;
@@ -991,7 +988,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
uint32_t tmpccmr2;
uint32_t tmpccer;
@@ -1061,7 +1058,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
uint32_t tmpccmr3;
uint32_t tmpccer;
@@ -1122,7 +1119,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
uint32_t tmpccmr3;
uint32_t tmpccer;
@@ -1182,7 +1179,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
@@ -1215,7 +1212,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(TIMx));
@@ -1248,7 +1245,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(TIMx));
@@ -1281,7 +1278,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
*/
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(TIMx));
diff --git a/Src/stm32wlxx_ll_usart.c b/Src/stm32wlxx_ll_usart.c
index 2356f3f..1f22de9 100644
--- a/Src/stm32wlxx_ll_usart.c
+++ b/Src/stm32wlxx_ll_usart.c
@@ -125,7 +125,7 @@
* - SUCCESS: USART registers are de-initialized
* - ERROR: USART registers are not de-initialized
*/
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
{
ErrorStatus status = SUCCESS;
@@ -169,7 +169,7 @@
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
{
ErrorStatus status = ERROR;
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
@@ -293,7 +293,7 @@
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
ErrorStatus status = SUCCESS;
diff --git a/Src/stm32wlxx_ll_utils.c b/Src/stm32wlxx_ll_utils.c
index 9ccf832..af1a1a4 100644
--- a/Src/stm32wlxx_ll_utils.c
+++ b/Src/stm32wlxx_ll_utils.c
@@ -376,6 +376,7 @@
{
ErrorStatus status = SUCCESS;
uint32_t pllrfreq = 0;
+ uint32_t range_sel;
uint32_t msi_range;
#if defined(DUAL_CORE)
uint32_t hclk2freq;
@@ -385,8 +386,9 @@
if (UTILS_PLL_IsBusy() == SUCCESS)
{
/* Get the current MSI range */
- if (LL_RCC_MSI_IsEnabledRangeSelect() == 0U)
+ if (LL_RCC_MSI_IsEnabledRangeSelect() == 1U)
{
+ range_sel = LL_RCC_MSIRANGESEL_RUN;
msi_range = LL_RCC_MSI_GetRange();
switch (msi_range)
{
@@ -412,6 +414,7 @@
}
else
{
+ range_sel = LL_RCC_MSIRANGESEL_STANDBY;
msi_range = LL_RCC_MSI_GetRangeAfterStandby();
switch (msi_range)
{
@@ -433,7 +436,7 @@
{
/* Calculate the new PLL output frequency & verify all PLL stages are correct (VCO input ranges,
VCO output ranges & SYSCLK max) when assert activated */
- pllrfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), msi_range),
+ pllrfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(range_sel, msi_range),
UTILS_PLLInitStruct);
#if defined(DUAL_CORE)
