drivers/clock_control: stm32 common pll src support(g0,g4,l4,l5,wb,wl)
This commit adds support to select pll outputs as peripheral clock
sources to the stm32 common driver.
With this commit they are only available on
STM32G0, STM32G4, STM32L4, STM32L5, STM32WB, and STM32WL.
Support for STM32F2, and STM32F4, which also have p,q,r dividers,
is not enabled in this commit.
Also, stm32_clock_control_get_subsys_rate is extended to return
the configured frequency in case they are enabled, otherwise 0.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c
index 28e2319..b7e778e 100644
--- a/drivers/clock_control/clock_stm32_ll_common.c
+++ b/drivers/clock_control/clock_stm32_ll_common.c
@@ -53,6 +53,21 @@
#define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
#define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
+/**
+ * @brief Return frequency for pll with 2 dividers and a multiplier
+ */
+__unused
+static uint32_t get_pll_div_frequency(uint32_t pllsrc_freq,
+ int pllm_div,
+ int plln_mul,
+ int pllout_div)
+{
+ __ASSERT_NO_MSG(pllm_div && pllout_div);
+
+ return (pllsrc_freq * plln_mul) /
+ (pllm_div * pllout_div);
+}
+
static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
{
return clock / prescaler;
@@ -129,6 +144,27 @@
}
break;
#endif /* STM32_SRC_PLLCLK */
+#if defined(STM32_SRC_PLL_P)
+ case STM32_SRC_PLL_P:
+ if (!IS_ENABLED(STM32_PLL_P_ENABLED)) {
+ r = -ENOTSUP;
+ }
+ break;
+#endif /* STM32_SRC_PLL_P */
+#if defined(STM32_SRC_PLL_Q)
+ case STM32_SRC_PLL_Q:
+ if (!IS_ENABLED(STM32_PLL_Q_ENABLED)) {
+ r = -ENOTSUP;
+ }
+ break;
+#endif /* STM32_SRC_PLL_Q */
+#if defined(STM32_SRC_PLL_R)
+ case STM32_SRC_PLL_R:
+ if (!IS_ENABLED(STM32_PLL_R_ENABLED)) {
+ r = -ENOTSUP;
+ }
+ break;
+#endif /* STM32_SRC_PLL_R */
default:
return -ENOTSUP;
}
@@ -297,6 +333,33 @@
*rate = get_pllout_frequency();
break;
#endif
+#if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED
+ case STM32_SRC_PLL_P:
+ *rate = get_pll_div_frequency(get_pllsrc_frequency(),
+ STM32_PLL_M_DIVISOR,
+ STM32_PLL_N_MULTIPLIER,
+ STM32_PLL_P_DIVISOR);
+ break;
+#endif
+#if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED
+ case STM32_SRC_PLL_Q:
+ *rate = get_pll_div_frequency(get_pllsrc_frequency(),
+ STM32_PLL_M_DIVISOR,
+ STM32_PLL_N_MULTIPLIER,
+ STM32_PLL_Q_DIVISOR);
+ break;
+#endif
+#if defined(STM32_SRC_PLL_R) & STM32_PLL_R_ENABLED
+ case STM32_SRC_PLL_R:
+ *rate = get_pll_div_frequency(get_pllsrc_frequency(),
+ STM32_PLL_M_DIVISOR,
+ STM32_PLL_N_MULTIPLIER,
+ STM32_PLL_R_DIVISOR);
+ break;
+#endif
+/* PLLSAI1x not supported yet */
+/* PLLSAI2x not supported yet */
+/* PLLI2Sx not supported yet */
#if defined(STM32_SRC_LSE)
case STM32_SRC_LSE:
*rate = STM32_LSE_FREQ;
diff --git a/drivers/clock_control/clock_stm32_ll_common.h b/drivers/clock_control/clock_stm32_ll_common.h
index 02fe922..66fc491 100644
--- a/drivers/clock_control/clock_stm32_ll_common.h
+++ b/drivers/clock_control/clock_stm32_ll_common.h
@@ -48,6 +48,7 @@
#ifdef STM32_SYSCLK_SRC_PLL
void config_pll_sysclock(void);
uint32_t get_pllout_frequency(void);
+uint32_t get_pllsrc_frequency(void);
#endif
void config_enable_default_clocks(void);
diff --git a/drivers/clock_control/clock_stm32g0.c b/drivers/clock_control/clock_stm32g0.c
index 81afa90..830fb16 100644
--- a/drivers/clock_control/clock_stm32g0.c
+++ b/drivers/clock_control/clock_stm32g0.c
@@ -36,6 +36,22 @@
}
/**
+ * @brief get the pll source frequency
+ */
+__unused
+uint32_t get_pllsrc_frequency(void)
+{
+ if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
+ return STM32_HSI_FREQ;
+ } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
+ return STM32_HSE_FREQ;
+ }
+
+ __ASSERT(0, "Invalid source");
+ return 0;
+}
+
+/**
* @brief Set up pll configuration
*/
__unused
diff --git a/drivers/clock_control/clock_stm32g4.c b/drivers/clock_control/clock_stm32g4.c
index 1655e18..16cef5b 100644
--- a/drivers/clock_control/clock_stm32g4.c
+++ b/drivers/clock_control/clock_stm32g4.c
@@ -35,6 +35,22 @@
}
/**
+ * @brief get the pll source frequency
+ */
+__unused
+uint32_t get_pllsrc_frequency(void)
+{
+ if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
+ return STM32_HSI_FREQ;
+ } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
+ return STM32_HSE_FREQ;
+ }
+
+ __ASSERT(0, "Invalid source");
+ return 0;
+}
+
+/**
* @brief Set up pll configuration
*/
__unused
diff --git a/drivers/clock_control/clock_stm32l4_l5_wb_wl.c b/drivers/clock_control/clock_stm32l4_l5_wb_wl.c
index 2886b3b..4d04b5b 100644
--- a/drivers/clock_control/clock_stm32l4_l5_wb_wl.c
+++ b/drivers/clock_control/clock_stm32l4_l5_wb_wl.c
@@ -18,6 +18,13 @@
#if STM32_SYSCLK_SRC_PLL
+#if defined(LL_RCC_MSIRANGESEL_RUN)
+#define CALC_RUN_MSI_FREQ(range) __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN, \
+ range << RCC_CR_MSIRANGE_Pos);
+#else
+#define CALC_RUN_MSI_FREQ(range) __LL_RCC_CALC_MSI_FREQ(range << RCC_CR_MSIRANGE_Pos);
+#endif
+
/**
* @brief Return PLL source
*/
@@ -38,6 +45,26 @@
}
/**
+ * @brief get the pll source frequency
+ */
+__unused
+uint32_t get_pllsrc_frequency(void)
+{
+ if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
+ return STM32_HSI_FREQ;
+ } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
+ return STM32_HSE_FREQ;
+#if defined(STM32_MSI_ENABLED)
+ } else if (IS_ENABLED(STM32_PLL_SRC_MSI)) {
+ return CALC_RUN_MSI_FREQ(STM32_MSI_RANGE);
+#endif
+ }
+
+ __ASSERT(0, "Invalid source");
+ return 0;
+}
+
+/**
* @brief Set up pll configuration
*/
void config_pll_sysclock(void)
