| /* |
| * Copyright (c) 2025 ITE Corporation. All Rights Reserved. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h> |
| |
| &pinctrl { |
| /* ADC alternate function */ |
| adc0_ch0_gpi0_default: adc0_ch0_gpi0_default { |
| pinmuxs = <&pinctrli 0 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| adc0_ch1_gpi1_default: adc0_ch1_gpi1_default { |
| pinmuxs = <&pinctrli 1 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| adc0_ch2_gpi2_default: adc0_ch2_gpi2_default { |
| pinmuxs = <&pinctrli 2 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| adc0_ch3_gpi3_default: adc0_ch3_gpi3_default { |
| pinmuxs = <&pinctrli 3 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| adc0_ch4_gpi4_default: adc0_ch4_gpi4_default { |
| pinmuxs = <&pinctrli 4 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| adc0_ch5_gpi5_default: adc0_ch5_gpi5_default { |
| pinmuxs = <&pinctrli 5 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| adc0_ch6_gpi6_default: adc0_ch6_gpi6_default { |
| pinmuxs = <&pinctrli 6 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| adc0_ch7_gpi7_default: adc0_ch7_gpi7_default { |
| pinmuxs = <&pinctrli 7 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| /* FSPI alternate function */ |
| fspi_fsce_gpg3_default: fspi_fsce_gpg3_default { |
| pinmuxs = <&pinctrlg 3 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| fspi_fmosi_gpg4_default: fspi_fmosi_gpg4_default { |
| pinmuxs = <&pinctrlg 4 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| fspi_fmiso_gpg5_default: fspi_fmiso_gpg5_default { |
| pinmuxs = <&pinctrlg 5 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| fspi_fsce1_gpg6_default: fspi_fsce1_gpg6_default { |
| pinmuxs = <&pinctrlg 6 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| fspi_fsck_gpg7_default: fspi_fsck_gpg7_default { |
| pinmuxs = <&pinctrlg 7 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| fspi_fdio2_gph5_default: fspi_fdio2_gph5_default { |
| pinmuxs = <&pinctrlh 5 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| fspi_fdio3_gph6_default: fspi_fdio3_gph6_default { |
| pinmuxs = <&pinctrlh 6 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| /* I2C alternate function */ |
| i2c0_clk_gpf2_default: i2c0_clk_gpf2_default { |
| pinmuxs = <&pinctrlf 2 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i2c0_data_gpf3_default: i2c0_data_gpf3_default { |
| pinmuxs = <&pinctrlf 3 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i2c1_clk_gpc1_default: i2c1_clk_gpc1_default { |
| pinmuxs = <&pinctrlc 1 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i2c1_data_gpc2_default: i2c1_data_gpc2_default { |
| pinmuxs = <&pinctrlc 2 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { |
| pinmuxs = <&pinctrlf 6 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i2c2_data_gpf7_default: i2c2_data_gpf7_default { |
| pinmuxs = <&pinctrlf 7 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i2c3_clk_gph1_default: i2c3_clk_gph1_default { |
| pinmuxs = <&pinctrlh 1 IT8XXX2_ALT_FUNC_4>; |
| }; |
| |
| i2c3_data_gph2_default: i2c3_data_gph2_default { |
| pinmuxs = <&pinctrlh 2 IT8XXX2_ALT_FUNC_4>; |
| }; |
| |
| i2c4_clk_gpe0_default: i2c4_clk_gpe0_default { |
| pinmuxs = <&pinctrle 0 IT8XXX2_ALT_FUNC_4>; |
| }; |
| |
| i2c4_data_gpe7_default: i2c4_data_gpe7_default { |
| pinmuxs = <&pinctrle 7 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c5_clk_gpa4_default: i2c5_clk_gpa4_default { |
| pinmuxs = <&pinctrla 4 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c5_data_gpa5_default: i2c5_data_gpa5_default { |
| pinmuxs = <&pinctrla 5 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c6_clk_gpd0_default: i2c6_clk_gpd0_default { |
| pinmuxs = <&pinctrld 0 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c6_data_gpd1_default: i2c6_data_gpd1_default { |
| pinmuxs = <&pinctrld 1 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c7_clk_gpb2_default: i2c7_clk_gpb2_default { |
| pinmuxs = <&pinctrlb 2 IT8XXX2_ALT_FUNC_4>; |
| }; |
| |
| i2c7_data_gph0_default: i2c7_data_gph0_default { |
| pinmuxs = <&pinctrlh 0 IT8XXX2_ALT_FUNC_4>; |
| }; |
| |
| i2c8_clk_gpb5_default: i2c8_clk_gpb5_default { |
| pinmuxs = <&pinctrlb 5 IT8XXX2_ALT_FUNC_4>; |
| }; |
| |
| i2c8_data_gpj6_default: i2c8_data_gpj6_default { |
| pinmuxs = <&pinctrlj 6 IT8XXX2_ALT_FUNC_4>; |
| }; |
| |
| /* I2C switch to interface */ |
| i2c9_clk_gpj3_default: i2c9_clk_gpj3_default { |
| pinmuxs = <&pinctrlj 3 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c9_data_gpj4_default: i2c9_data_gpj4_default { |
| pinmuxs = <&pinctrlj 4 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c10_clk_gpj5_default: i2c10_clk_gpj5_default { |
| pinmuxs = <&pinctrlj 5 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c10_data_gpe1_default: i2c10_data_gpe1_default { |
| pinmuxs = <&pinctrle 1 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c11_clk_gpe2_default: i2c11_clk_gpe2_default { |
| pinmuxs = <&pinctrle 2 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c11_data_gpe3_default: i2c11_data_gpe3_default { |
| pinmuxs = <&pinctrle 3 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c12_clk_gpf0_default: i2c12_clk_gpf0_default { |
| pinmuxs = <&pinctrlf 0 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| i2c12_data_gpf1_default: i2c12_data_gpf1_default { |
| pinmuxs = <&pinctrlf 1 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| /* I3C alternate function */ |
| i3c0_clk_gpj3_default: i3c0_clk_gpj3_default { |
| pinmuxs = <&pinctrlj 3 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i3c0_data_gpj4_default: i3c0_data_gpj4_default { |
| pinmuxs = <&pinctrlj 4 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i3c1_clk_gpj5_default: i3c1_clk_gpj5_default { |
| pinmuxs = <&pinctrlj 5 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i3c1_data_gpe1_default: i3c1_data_gpe1_default { |
| pinmuxs = <&pinctrle 1 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i3c2_clk_gpe2_default: i3c2_clk_gpe2_default { |
| pinmuxs = <&pinctrle 2 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i3c2_data_gpe3_default: i3c2_data_gpe3_default { |
| pinmuxs = <&pinctrle 3 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i3c3_clk_gpf0_default: i3c3_clk_gpf0_default { |
| pinmuxs = <&pinctrlf 0 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| i3c3_data_gpf1_default: i3c3_data_gpf1_default { |
| pinmuxs = <&pinctrlf 1 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| /* Keyboard alternate function */ |
| kso0_default: kso0_gpk0_default: kso0_gpk0_default { |
| pinmuxs = <&pinctrlk 0 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso1_default: kso1_gpk1_default: kso1_gpk1_default { |
| pinmuxs = <&pinctrlk 1 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso2_default: kso2_gpk2_default: kso2_gpk2_default { |
| pinmuxs = <&pinctrlk 2 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso3_default: kso3_gpk3_default: kso3_gpk3_default { |
| pinmuxs = <&pinctrlk 3 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso4_default: kso4_gpk4_default: kso4_gpk4_default { |
| pinmuxs = <&pinctrlk 4 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso5_default: kso5_gpk5_default: kso5_gpk5_default { |
| pinmuxs = <&pinctrlk 5 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso6_default: kso6_gpk6_default: kso6_gpk6_default { |
| pinmuxs = <&pinctrlk 6 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso7_default: kso7_gpk7_default: kso7_gpk7_default { |
| pinmuxs = <&pinctrlk 7 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso8_default: kso8_gpl0_default: kso8_gpl0_default { |
| pinmuxs = <&pinctrll 0 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso9_default: kso9_gpl1_default: kso9_gpl1_default { |
| pinmuxs = <&pinctrll 1 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso10_default: kso10_gpl2_default: kso10_gpl2_default { |
| pinmuxs = <&pinctrll 2 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso11_default: kso11_gpl3_default: kso11_gpl3_default { |
| pinmuxs = <&pinctrll 3 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso12_default: kso12_gpl4_default: kso12_gpl4_default { |
| pinmuxs = <&pinctrll 4 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso13_default: kso13_gpl5_default: kso13_gpl5_default { |
| pinmuxs = <&pinctrll 5 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso14_default: kso14_gpl6_default: kso14_gpl6_default { |
| pinmuxs = <&pinctrll 6 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso15_default: kso15_gpl7_default: kso15_gpl7_default { |
| pinmuxs = <&pinctrll 7 IT8XXX2_ALT_FUNC_1>; |
| drive-open-drain; |
| bias-pull-up; |
| }; |
| |
| kso16_default: kso16_gpc3_default: kso16_gpc3_default { |
| pinmuxs = <&pinctrlc 3 IT8XXX2_ALT_FUNC_1>; |
| bias-pull-up; |
| }; |
| |
| kso17_default: kso17_gpc5_default: kso17_gpc5_default { |
| pinmuxs = <&pinctrlc 5 IT8XXX2_ALT_FUNC_1>; |
| bias-pull-up; |
| }; |
| |
| ksi0_default: ksi0_gpn0_default: ksi0_gpn0_default { |
| pinmuxs = <&pinctrln 0 IT8XXX2_ALT_FUNC_1>; |
| bias-pull-up; |
| }; |
| |
| ksi1_default: ksi1_gpn1_default: ksi1_gpn1_default { |
| pinmuxs = <&pinctrln 1 IT8XXX2_ALT_FUNC_1>; |
| bias-pull-up; |
| }; |
| |
| ksi2_default: ksi2_gpn2_default: ksi2_gpn2_default { |
| pinmuxs = <&pinctrln 2 IT8XXX2_ALT_FUNC_1>; |
| bias-pull-up; |
| }; |
| |
| ksi3_default: ksi3_gpn3_default: ksi3_gpn3_default { |
| pinmuxs = <&pinctrln 3 IT8XXX2_ALT_FUNC_1>; |
| bias-pull-up; |
| }; |
| |
| ksi4_default: ksi4_gpn4_default: ksi4_gpn4_default { |
| pinmuxs = <&pinctrln 4 IT8XXX2_ALT_FUNC_1>; |
| bias-pull-up; |
| }; |
| |
| ksi5_default: ksi5_gpn5_default: ksi5_gpn5_default { |
| pinmuxs = <&pinctrln 5 IT8XXX2_ALT_FUNC_1>; |
| bias-pull-up; |
| }; |
| |
| ksi6_default: ksi6_gpn6_default: ksi6_gpn6_default { |
| pinmuxs = <&pinctrln 6 IT8XXX2_ALT_FUNC_1>; |
| bias-pull-up; |
| }; |
| |
| ksi7_default: ksi7_gpn7_default: ksi7_gpn7_default { |
| pinmuxs = <&pinctrln 7 IT8XXX2_ALT_FUNC_1>; |
| bias-pull-up; |
| }; |
| |
| /* PECI alternate function */ |
| peci_gpf6_default: peci_gpf6_default { |
| pinmuxs = <&pinctrlf 6 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| /* PWM alternate function */ |
| pwm0_gpa0_default: pwm0_gpa0_default { |
| pinmuxs = <&pinctrla 0 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| pwm1_gpa1_default: pwm1_gpa1_default { |
| pinmuxs = <&pinctrla 1 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| pwm2_gpa2_default: pwm2_gpa2_default { |
| pinmuxs = <&pinctrla 2 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| pwm3_gpa3_default: pwm3_gpa3_default { |
| pinmuxs = <&pinctrla 3 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| pwm4_gpa4_default: pwm4_gpa4_default { |
| pinmuxs = <&pinctrla 4 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| pwm5_gpa5_default: pwm5_gpa5_default { |
| pinmuxs = <&pinctrla 5 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| pwm6_gpa6_default: pwm6_gpa6_default { |
| pinmuxs = <&pinctrla 6 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| pwm7_gpa7_default: pwm7_gpa7_default { |
| pinmuxs = <&pinctrla 7 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| /* SSPI alternate function */ |
| ssce0_gpj7_default: ssce0_gpj7_default { |
| pinmuxs = <&pinctrlj 7 IT8XXX2_ALT_FUNC_4>; |
| }; |
| |
| ssce1_gph7_default: ssce1_gph7_default { |
| pinmuxs = <&pinctrlh 7 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| ssck_gpa6_default: ssck_gpa6_default { |
| pinmuxs = <&pinctrla 6 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| smosi_gpc6_default: smosi_gpc6_default { |
| pinmuxs = <&pinctrlc 6 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| smiso_gpc4_default: smiso_gpc4_default { |
| pinmuxs = <&pinctrlc 4 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| /* Tachometer alternate function */ |
| tach0a_gpd6_default: tach0a_gpd6_default { |
| pinmuxs = <&pinctrld 6 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| tach1a_gpd7_default: tach1a_gpd7_default { |
| pinmuxs = <&pinctrld 7 IT8XXX2_ALT_FUNC_1>; |
| }; |
| |
| tach2a_gpj0_default: tach2a_gpj0_default { |
| pinmuxs = <&pinctrlj 0 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| tach0b_gpc6_default: tach0b_gpc6_default { |
| pinmuxs = <&pinctrlc 6 IT8XXX2_ALT_FUNC_4>; |
| }; |
| |
| tach1b_gpj6_default: tach1b_gpj6_default { |
| pinmuxs = <&pinctrlj 6 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| tach2b_gpj1_default: tach2b_gpj1_default { |
| pinmuxs = <&pinctrlj 1 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| /* UART alternate function */ |
| uart1_rx_gpc7_default: uart1_rx_gpc7_default { |
| pinmuxs = <&pinctrlc 7 IT8XXX2_ALT_FUNC_4>; |
| }; |
| |
| uart1_tx_gpe6_default: uart1_tx_gpe6_default { |
| pinmuxs = <&pinctrle 6 IT8XXX2_ALT_FUNC_4>; |
| }; |
| |
| uart2_rx_gph1_default: uart2_rx_gph1_default { |
| pinmuxs = <&pinctrlh 1 IT8XXX2_ALT_FUNC_3>; |
| }; |
| |
| uart2_tx_gph2_default: uart2_tx_gph2_default { |
| pinmuxs = <&pinctrlh 2 IT8XXX2_ALT_FUNC_3>; |
| }; |
| }; |
