dts/riscv/riscv32-litex-vexriscv.dtsi

/*
 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "litex,vexriscv", "litex-dev";
	model = "litex,vexriscv";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			clock-frequency = <100000000>;
			compatible = "litex,vexriscv-standard", "riscv";
			device_type = "cpu";
			reg = <0>;
			riscv,isa = "rv32im_zicsr_zifencei";
			status = "okay";
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "litex,vexriscv";
		ranges;

		intc0: interrupt-controller@bc0 {
			compatible = "litex,vexriscv-intc0";
			#address-cells = <0>;
			#interrupt-cells = <2>;
			interrupt-controller;
			reg = <0xbc0 0x4 0xfc0 0x4>;
			reg-names = "irq_mask", "irq_pending";
			riscv,max-priority = <7>;
		};
	};
};