| #include "skeleton.dtsi" |
| |
| #include <dt-bindings/i2c/i2c.h> |
| |
| #define __SIZE_K(x) (x * 1024) |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "snps,arcem4"; |
| reg = <1>; |
| }; |
| |
| core_intc: arcv2-intc@0 { |
| compatible = "snps,arcv2-intc"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| flash0: flash@DT_FLASH_ADDR { |
| reg = <DT_FLASH_ADDR DT_FLASH_SIZE>; |
| }; |
| |
| sram0: memory@a8000400 { |
| device_type = "memory"; |
| compatible = "mmio-sram"; |
| reg = <0xa8000400 DT_SRAM_SIZE>; |
| }; |
| |
| dccm0: dccm@80000000 { |
| device_type = "memory"; |
| compatible = "arc,dccm"; |
| reg = <0x80000000 DT_DCCM_SIZE>; |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| uart0: uart@b0002000 { |
| compatible = "intel,qmsi-uart"; |
| reg = <0xb0002000 0x400>; |
| interrupts = <41 0>; |
| interrupt-parent = <&core_intc>; |
| label = "UART_0"; |
| |
| status = "disabled"; |
| }; |
| |
| uart1: uart@b0002400 { |
| compatible = "intel,qmsi-uart"; |
| reg = <0xb0002400 0x400>; |
| interrupts = <42 0>; |
| interrupt-parent = <&core_intc>; |
| label = "UART_1"; |
| |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@80012000 { |
| compatible = "intel,qmsi-ss-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x80012000 0x100>; |
| interrupts = <22 1>, <25 1>, <24 1>, <23 1>; |
| interrupt-names = "error", "stop", "tx", "rx"; |
| interrupt-parent = <&core_intc>; |
| label = "I2C_0"; |
| |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@80012100 { |
| compatible = "intel,qmsi-ss-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x80012100 0x100>; |
| interrupts = <26 1>, <29 1>, <28 1>, <27 1>; |
| interrupt-names = "error", "stop", "tx", "rx"; |
| interrupt-parent = <&core_intc>; |
| label = "I2C_1"; |
| |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@b0002800 { |
| compatible = "intel,qmsi-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xb0002800 0x400>; |
| interrupts = <36 1>; |
| interrupt-parent = <&core_intc>; |
| label = "I2C_2"; |
| |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@b0002c00 { |
| compatible = "intel,qmsi-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xb0002c00 0x400>; |
| interrupts = <37 1>; |
| interrupt-parent = <&core_intc>; |
| label = "I2C_3"; |
| |
| status = "disabled"; |
| }; |
| }; |
| }; |