soc: rt1xxx: allow linking code to OCRAM region
Allow linking code into OCRAM region when building for RT1xxx SOCs. This
can be used on the RT11xx dual core SOCs as a shared memory region, when
the M7 core needs to load code into a region accessible to the M4 core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.series b/soc/arm/nxp_imx/rt/Kconfig.defconfig.series
index 7efc987..d613f52 100644
--- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.series
+++ b/soc/arm/nxp_imx/rt/Kconfig.defconfig.series
@@ -103,6 +103,15 @@
endif # CODE_SRAM0
+if CODE_OCRAM
+
+config FLASH_SIZE
+ default $(dt_node_reg_size_int,/soc/ocram@20200000,0,K)
+
+config FLASH_BASE_ADDRESS
+ default $(dt_node_reg_addr_hex,/soc/ocram@20200000)
+
+endif # CODE_OCRAM
if CODE_FLEXSPI
diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc
index c151ee6..6ab2aba 100644
--- a/soc/arm/nxp_imx/rt/Kconfig.soc
+++ b/soc/arm/nxp_imx/rt/Kconfig.soc
@@ -723,6 +723,10 @@
config CODE_SRAM0
bool "Link code into RAM_L memory (RAM_L)"
+
+config CODE_OCRAM
+ bool "Link code into OCRAM memory (OCRAM-M4)"
+
endchoice
config OCRAM_NOCACHE
