| /* |
| * Copyright (c) 2019 Lexmark International, Inc. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <mem.h> |
| #include <arm/armv7-r.dtsi> |
| #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> |
| #include <zephyr/dt-bindings/ethernet/xlnx_gem.h> |
| |
| / { |
| soc { |
| pinctrl: pinctrl@ff180000 { |
| reg = <0xff180000 0xc80>; |
| compatible = "xlnx,pinctrl-zynqmp"; |
| }; |
| flash0: flash@c0000000 { |
| compatible = "soc-nv-flash"; |
| reg = <0xc0000000 DT_SIZE_M(32)>; |
| }; |
| |
| sram0: memory@0 { |
| compatible = "mmio-sram"; |
| reg = <0 DT_SIZE_M(64)>; |
| }; |
| |
| ocm: memory@fffc0000 { |
| compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; |
| reg = <0xfffc0000 DT_SIZE_K(256)>; |
| zephyr,memory-region = "OCM"; |
| }; |
| |
| uart0: uart@ff000000 { |
| compatible = "xlnx,xuartps"; |
| reg = <0xff000000 0x4c>; |
| status = "disabled"; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0"; |
| }; |
| |
| uart1: uart@ff010000 { |
| compatible = "xlnx,xuartps"; |
| reg = <0xff010000 0x4c>; |
| status = "disabled"; |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0"; |
| }; |
| |
| ttc0: timer@ff110000 { |
| compatible = "xlnx,ttcps"; |
| status = "disabled"; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 37 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 38 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1", "irq_2"; |
| reg = <0xff110000 0x1000>; |
| }; |
| |
| ttc1: timer@ff120000 { |
| compatible = "xlnx,ttcps"; |
| status = "disabled"; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 40 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 41 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1", "irq_2"; |
| reg = <0xff120000 0x1000>; |
| }; |
| |
| ttc2: timer@ff130000 { |
| compatible = "xlnx,ttcps"; |
| status = "disabled"; |
| interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 43 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 44 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1", "irq_2"; |
| reg = <0xff130000 0x1000>; |
| }; |
| |
| ttc3: timer@ff140000 { |
| compatible = "xlnx,ttcps"; |
| status = "disabled"; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 46 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 47 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1", "irq_2"; |
| reg = <0xff140000 0x1000>; |
| }; |
| |
| gem0: ethernet@ff0b0000 { |
| compatible = "xlnx,gem"; |
| reg = <0xff0b0000 0x1000>, |
| <0xff5e0050 0x4>; |
| status = "disabled"; |
| interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 58 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1"; |
| mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; |
| phy-poll-interval = <1000>; |
| link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; |
| amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; |
| amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; |
| hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; |
| hw-rx-buffer-offset = <0>; |
| hw-tx-buffer-size-full; |
| rx-buffer-descriptors = <32>; |
| tx-buffer-descriptors = <32>; |
| rx-buffer-size = <512>; |
| tx-buffer-size = <512>; |
| discard-rx-fcs; |
| unicast-hash; |
| full-duplex; |
| }; |
| |
| gem1: ethernet@ff0c0000 { |
| compatible = "xlnx,gem"; |
| reg = <0xff0c0000 0x1000>, |
| <0xff5e0054 0x4>; |
| status = "disabled"; |
| interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 60 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1"; |
| mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; |
| phy-poll-interval = <1000>; |
| link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; |
| amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; |
| amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; |
| hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; |
| hw-rx-buffer-offset = <0>; |
| hw-tx-buffer-size-full; |
| rx-buffer-descriptors = <32>; |
| tx-buffer-descriptors = <32>; |
| rx-buffer-size = <512>; |
| tx-buffer-size = <512>; |
| discard-rx-fcs; |
| unicast-hash; |
| full-duplex; |
| }; |
| |
| gem2: ethernet@ff0d0000 { |
| compatible = "xlnx,gem"; |
| reg = <0xff0d0000 0x1000>, |
| <0xff5e0058 0x4>; |
| status = "disabled"; |
| interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 62 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1"; |
| mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; |
| phy-poll-interval = <1000>; |
| link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; |
| amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; |
| amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; |
| hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; |
| hw-rx-buffer-offset = <0>; |
| hw-tx-buffer-size-full; |
| rx-buffer-descriptors = <32>; |
| tx-buffer-descriptors = <32>; |
| rx-buffer-size = <512>; |
| tx-buffer-size = <512>; |
| discard-rx-fcs; |
| unicast-hash; |
| full-duplex; |
| }; |
| |
| gem3: ethernet@ff0e0000 { |
| compatible = "xlnx,gem"; |
| reg = <0xff0e0000 0x1000>, |
| <0xff5e005c 0x4>; |
| status = "disabled"; |
| interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 64 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1"; |
| mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; |
| phy-poll-interval = <1000>; |
| link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; |
| amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; |
| amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; |
| hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; |
| hw-rx-buffer-offset = <0>; |
| hw-tx-buffer-size-full; |
| rx-buffer-descriptors = <32>; |
| tx-buffer-descriptors = <32>; |
| rx-buffer-size = <512>; |
| tx-buffer-size = <512>; |
| discard-rx-fcs; |
| unicast-hash; |
| full-duplex; |
| }; |
| |
| psgpio: gpio@ff0a0000 { |
| compatible = "xlnx,ps-gpio"; |
| status = "disabled"; |
| reg = <0xff0a0000 0x1000>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| psgpio_bank0: psgpio_bank@0 { |
| compatible = "xlnx,ps-gpio-bank"; |
| reg = <0x0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <26>; |
| status = "okay"; |
| }; |
| |
| psgpio_bank1: psgpio_bank@1 { |
| compatible = "xlnx,ps-gpio-bank"; |
| reg = <0x1>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <26>; |
| status = "okay"; |
| }; |
| |
| psgpio_bank2: psgpio_bank@2 { |
| compatible = "xlnx,ps-gpio-bank"; |
| reg = <0x2>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <26>; |
| status = "okay"; |
| }; |
| |
| psgpio_bank3: psgpio_bank@3 { |
| compatible = "xlnx,ps-gpio-bank"; |
| reg = <0x3>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| status = "okay"; |
| }; |
| |
| psgpio_bank4: psgpio_bank@4 { |
| compatible = "xlnx,ps-gpio-bank"; |
| reg = <0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| status = "okay"; |
| }; |
| |
| psgpio_bank5: psgpio_bank@5 { |
| compatible = "xlnx,ps-gpio-bank"; |
| reg = <0x5>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| status = "okay"; |
| }; |
| }; |
| }; |
| |
| }; |
