tests/drivers/clock_control: stm32 add adc-pll_p overlays(g0,g4,wl)
For the STM32G0, STM32G4, and STM32WL enable the adc node in one
configuration, and select the PLL_P output as its clock source.
PLL_P divider is chosen to be 20 to make sure it's a unique frequency.
- g0, and g4 have pll as sysclk
- wl has hse as sysclock
The test configurations and the overlay-files are renamed accordingly.
All overlays that don't specify an alternative clock source still
make sure that the adc node is "okay" to be able to perform basic test.
The basic test only turns on and off the gate clock without checking the
frequency.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay
index b455df2..610cd80 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay
@@ -68,3 +68,7 @@
<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
status = "okay";
};
+
+&adc1 {
+ status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay
index f9c564c..a6a5f63 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay
@@ -40,6 +40,7 @@
/delete-property/ clock-frequency;
};
+
/* Core set up
* Aim of this part is to provide a base working clock config
*/
@@ -74,3 +75,7 @@
<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
status = "okay";
};
+
+&adc1 {
+ status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay
similarity index 88%
rename from tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse.overlay
rename to tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay
index 1232225..0737e15 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay
@@ -49,7 +49,7 @@
&pll {
div-m = <1>;
mul-n = <8>;
- div-p = <2>;
+ div-p = <20>; /* 6.4 MHz */
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
@@ -75,3 +75,9 @@
<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
status = "okay";
};
+
+&adc1 {
+ clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>,
+ <&rcc STM32_SRC_PLL_P ADC_SEL(1)>;
+ status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay
index 30c2362..46aa06b 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay
@@ -75,3 +75,7 @@
<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
status = "okay";
};
+
+&adc1 {
+ status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi.overlay
deleted file mode 100644
index eb31f73..0000000
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi.overlay
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2022 Linaro Limited
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/* Clocks clean up config
- * Aim is to avoid conflict with specific default board configuration
- */
-
-&clk_hse {
- status = "disabled";
- /delete-property/ hse-bypass;
- /delete-property/ clock-frequency;
-};
-
-&clk_hsi {
- status = "disabled";
-};
-
-&pll {
- /delete-property/ div-m;
- /delete-property/ mul-n;
- /delete-property/ div-p;
- /delete-property/ div-q;
- /delete-property/ div-r;
- /delete-property/ clocks;
- status = "disabled";
-};
-
-&rcc {
- /delete-property/ clocks;
- /delete-property/ clock-frequency;
-};
-
-
-/* Core set up
- * Aim of this part is to provide a base working clock config
- */
-
-&clk_hsi {
- status = "okay";
-};
-
-&pll {
- div-m = <1>;
- mul-n = <8>;
- div-p = <2>;
- div-q = <2>;
- div-r = <2>;
- clocks = <&clk_hsi>;
- status = "okay";
-};
-
-&rcc {
- clocks = <&pll>;
- clock-frequency = <DT_FREQ_M(64)>;
- ahb-prescaler = <1>;
- apb1-prescaler = <2>;
-};
-
-&i2c1 {
- /delete-property/ clocks;
- clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
- <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
- status = "okay";
-};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi_adc1_pllp.overlay
similarity index 85%
copy from tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse.overlay
copy to tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi_adc1_pllp.overlay
index 1232225..7f6bd50 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi_adc1_pllp.overlay
@@ -42,14 +42,10 @@
status = "okay";
};
-&clk_lse {
- status = "okay";
-};
-
&pll {
div-m = <1>;
mul-n = <8>;
- div-p = <2>;
+ div-p = <20>; /* 6.4 MHz */
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
@@ -70,8 +66,9 @@
status = "okay";
};
-&lptim1 {
- clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
- <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
+&adc1 {
+ /* changes clock source for both ADC1 and ADC2 */
+ clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>,
+ <&rcc STM32_SRC_PLL_P ADC12_SEL(1)>;
status = "okay";
};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay
index e288150..17224fd 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay
@@ -81,3 +81,7 @@
<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
status = "okay";
};
+
+&adc1 {
+ status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay
index ecd08bc..66f28d5 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay
@@ -81,3 +81,7 @@
<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
status = "okay";
};
+
+&adc1 {
+ status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay
index 263fa70..e28c47c 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay
@@ -81,3 +81,7 @@
<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
status = "okay";
};
+
+&adc1 {
+ status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay
index cf3d15c..a460261 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay
@@ -75,3 +75,7 @@
<&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
status = "okay";
};
+
+&adc1 {
+ status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay
similarity index 85%
rename from tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse.overlay
rename to tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay
index 6234e76..1629509 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay
@@ -60,6 +60,16 @@
status = "okay";
};
+&pll {
+ div-m = <1>;
+ mul-n = <8>;
+ div-p = <20>; /* 12.8 MHz */
+ div-q = <2>;
+ div-r = <2>;
+ clocks = <&clk_hse>;
+ status = "okay";
+};
+
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(32)>;
@@ -84,3 +94,9 @@
<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
status = "okay";
};
+
+&adc1 {
+ clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>,
+ <&rcc STM32_SRC_PLL_P ADC_SEL(2)>;
+ status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay
index ab869a8..6e00ee8 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay
@@ -80,3 +80,7 @@
<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
status = "okay";
};
+
+&adc1 {
+ status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/testcase.yaml
index 5b30247..c5b68b7 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/testcase.yaml
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/testcase.yaml
@@ -10,11 +10,11 @@
drivers.stm32_clock_configuration.common_device.g0.i2c1_sysclk_lptim1_lsi:
extra_args: DTC_OVERLAY_FILE="boards/g0_i2c1_sysclk_lptim1_lsi.overlay"
platform_allow: nucleo_g071rb
- drivers.stm32_clock_configuration.common_device.g0.i2c1_hsi_lptim1_lse:
- extra_args: DTC_OVERLAY_FILE="boards/g0_i2c1_hsi_lptim1_lse.overlay"
+ drivers.stm32_clock_configuration.common_device.g0.i2c1_hsi_lptim1_lse_adc1_pllp:
+ extra_args: DTC_OVERLAY_FILE="boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay"
platform_allow: nucleo_g071rb
- drivers.stm32_clock_configuration.common_device.wl.i2c1_hsi_lptim1_lse:
- extra_args: DTC_OVERLAY_FILE="boards/wl_i2c1_hsi_lptim1_lse.overlay"
+ drivers.stm32_clock_configuration.common_device.wl.i2c1_hsi_lptim1_lse_adc1_pllp:
+ extra_args: DTC_OVERLAY_FILE="boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay"
platform_allow: nucleo_wl55jc
drivers.stm32_clock_configuration.common_device.wl.i2c1_sysclk_lptim1_lsi:
extra_args: DTC_OVERLAY_FILE="boards/wl_i2c1_sysclk_lptim1_lsi.overlay"
@@ -25,8 +25,8 @@
drivers.stm32_clock_configuration.common_device.l4.i2c1_hsi_lptim1_lse:
extra_args: DTC_OVERLAY_FILE="boards/l4_i2c1_hsi_lptim1_lse.overlay"
platform_allow: disco_l475_iot1
- drivers.stm32_clock_configuration.common_device.g4.i2c1_hsi:
- extra_args: DTC_OVERLAY_FILE="boards/g4_i2c1_hsi.overlay"
+ drivers.stm32_clock_configuration.common_device.g4.i2c1_hsi_adc1_pllp:
+ extra_args: DTC_OVERLAY_FILE="boards/g4_i2c1_hsi_adc1_pllp.overlay"
platform_allow: nucleo_g474re
drivers.stm32_clock_configuration.common_device.f0.i2c1_hsi:
extra_args: DTC_OVERLAY_FILE="boards/f0_i2c1_hsi.overlay"
