| /* |
| * Copyright 2023 NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <dt-bindings/clock/nxp_s32k146_clock.h> |
| #include <nxp/nxp_s32k1xx.dtsi> |
| |
| / { |
| cpus { |
| cpu@0 { |
| compatible = "arm,cortex-m4f"; |
| }; |
| }; |
| |
| soc { |
| /* |
| * SRAM_L and SRAM_U ranges form a contiguous block but misaligned |
| * and burst accesses cannot occur across the 0x20000000 boundary |
| * that separates the two SRAM arrays. Hence, treat the two arrays |
| * as separate memory ranges. |
| */ |
| sram_l: sram@1fff0000 { |
| compatible = "mmio-sram"; |
| reg = <0x1fff0000 DT_SIZE_K(64)>; |
| }; |
| |
| sram_u: sram@20000000 { |
| compatible = "mmio-sram"; |
| reg = <0x20000000 DT_SIZE_K(60)>; |
| }; |
| }; |
| }; |
| |
| /delete-node/ &lpi2c1; |
| /delete-node/ &ftm6; |
| /delete-node/ &ftm7; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
| |
| &ftfc { |
| flash0: flash@0 { |
| compatible = "soc-nv-flash"; |
| reg = <0 DT_SIZE_M(1)>; |
| erase-block-size = <DT_SIZE_K(4)>; |
| write-block-size = <8>; |
| }; |
| }; |
| |
| &lpuart2 { |
| clocks = <&clock NXP_S32_LPUART2_CLK>; |
| }; |
| |
| &lpspi1 { |
| clocks = <&clock NXP_S32_LPSPI1_CLK>; |
| }; |
| |
| &lpspi2 { |
| clocks = <&clock NXP_S32_LPSPI2_CLK>; |
| }; |
| |
| &flexcan0 { |
| interrupts = <78 0>, <79 0>, <80 0>, <81 0>, <82 0>; |
| interrupt-names = "warning", "error", "wake-up", "mb-0-15", "mb-16-31"; |
| }; |
| |
| &flexcan1 { |
| interrupts = <85 0>, <86 0>, <88 0>, <89 0>; |
| interrupt-names = "warning", "error", "mb-0-15", "mb-16-31"; |
| clocks = <&clock NXP_S32_FLEXCAN1_CLK>; |
| }; |
| |
| &flexcan2 { |
| interrupts = <92 0>, <93 0>, <95 0>; |
| interrupt-names = "warning", "error", "mb-0-15"; |
| clocks = <&clock NXP_S32_FLEXCAN2_CLK>; |
| }; |