boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_m7.overlay

/*
 * Copyright (c) 2023 bytes at work AG
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/dt-bindings/display/panel.h>

/ {
	chosen {
		zephyr,display = &ltdc;
	};
};

&ltdc {
	status = "okay";
	ext-sdram = <&sdram2>;

	/* orisetech, otm8009a */
	width = <800>;
	height = <480>;
	display-timings {
		compatible = "zephyr,panel-timing";
		hsync-active = <0>;
		vsync-active = <0>;
		de-active = <0>;
		pixelclk-active = <0>;
		hsync-len = <2>;
		vsync-len = <1>;
		hback-porch = <34>;
		vback-porch = <15>;
		hfront-porch = <34>;
		vfront-porch = <16>;
	};

	def-back-color-red = <0>;
	def-back-color-green = <0>;
	def-back-color-blue = <0>;
	pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
};

/* ltdc uses pll3_r as pixel clock */
&pll3 {
	status = "okay";
	clocks = <&clk_hse>;
	div-m = <5>;
	mul-n = <132>;
	div-p = <2>;
	div-q = <2>;
	div-r = <24>; /* 27.5 MHz */
};

&mipi_dsi {
	status = "okay";

	/* DSI HOST dedicated PLL
	 * F_VCO = CLK_IN / pll-idf * 2 * pll-ndiv
	 * PHI = F_VCO / 2 / (1 << pll-odf) = lane_byte_clk
	 *     = 25 MHz / 5 * 2 * 100 / 2 / (1<<0) / 8 = 62.5 MHz
	 */
	pll-ndiv = <100>;
	pll-idf = <5>;
	pll-odf = <0>;

	vs-active-high;
	hs-active-high;
	de-active-high;
};

&otm8009a {
	data-lanes = <2>;
	pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
	rotation = <90>;
};